CN106449420B - It is embedded into formula encapsulating structure and its manufacturing method - Google Patents
It is embedded into formula encapsulating structure and its manufacturing method Download PDFInfo
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- CN106449420B CN106449420B CN201510472785.7A CN201510472785A CN106449420B CN 106449420 B CN106449420 B CN 106449420B CN 201510472785 A CN201510472785 A CN 201510472785A CN 106449420 B CN106449420 B CN 106449420B
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- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 239000011469 building brick Substances 0.000 claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 50
- 238000000034 method Methods 0.000 claims description 39
- 238000005516 engineering process Methods 0.000 claims description 32
- 238000009713 electroplating Methods 0.000 claims 16
- 239000010949 copper Substances 0.000 description 18
- 239000000463 material Substances 0.000 description 17
- 238000007740 vapor deposition Methods 0.000 description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 16
- 229910052802 copper Inorganic materials 0.000 description 16
- 239000000758 substrate Substances 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 14
- 230000008569 process Effects 0.000 description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 12
- 238000007747 plating Methods 0.000 description 12
- 238000012545 processing Methods 0.000 description 12
- 239000011347 resin Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- 239000006071 cream Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 238000004544 sputter deposition Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 7
- 238000010329 laser etching Methods 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 4
- 229920001296 polysiloxane Polymers 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- CPFNXHQBAHTVKB-UHFFFAOYSA-N [Ti].[Cu].[W] Chemical compound [Ti].[Cu].[W] CPFNXHQBAHTVKB-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
One kind being embedded into formula encapsulating structure, including one first dielectric layer, one first conductive pattern layer, one first conductive posts, an electronic building brick, one second dielectric layer, one second conductive pattern layer and one second conductive posts.First conductive pattern layer, the first conductive posts and electronic building brick are set in the first dielectric layer.Expose a first surface of the first dielectric layer in one surface of the first conductive pattern layer.Expose a second surface of the first dielectric layer in one surface of the first conductive posts.Second conductive pattern layer and the second conductive posts are set in the second dielectric layer.A third surface of the second dielectric layer is exposed on one surface of the second conductive pattern layer, and is electrically connected with the first conductive posts for exposing second surface.Expose the 4th surface of second dielectric layer in one surface of the second conductive posts.
Description
Technical field
The present invention relates to a kind of encapsulating structure and its manufacturing method, in particular to one kind is embedded into formula encapsulating structure and its manufacture
Method.
Background technique
In today of social advanced IT application, multimedia application market constantly explosion, integrated antenna package technology
Also therewith towards the digitlization of electronic device, networking, region connectionization and the trend development for using hommization.It is above-mentioned to meet
Requirement, electronic building brick must cooperate high speed processing, multifunction, productive set (Integrated) and miniaturization etc.
Various requirements, integrated antenna package technology is also therefore and then towards micromation, densification development.Wherein, ball lattice array
Formula constructs (Ball Grid Array, BGA), chip size construction (Chip-Scale Package, CSP), flip construction
The encapsulation of the high density integrated circuits such as (Flip Chip Package, F/C), multi-chip module (Multi-Chip Module, MCM)
Technology is also come into being.
Wherein, flip constructing technology is mainly contact (usually wafer external on the wafer for being formed with multiple chips
Weld pad) on formed ball bottom metal layer (UBM, Under Bump Metallurgy), it is then convex in the upper formation of ball bottom metal layer
The connecting interface of block or implantation soldered ball to electrically conduct as subsequent chip (or wafer) and substrate (substrate).Due to covering
Brilliant constructing technology can be applied to the chip-packaging structure of high pin number (High Pin Count), and have diminution encapsulating face simultaneously
The multiple advantages such as product and shortening signal transmission path, so flip constructing technology has been widely used in chip package field.
Also, in order to create bigger space in limited substrate area to promote the function of electronic device, now
There is technology that electronic building brick is embedded into substrate, is embedded into formula encapsulating structure to form one.User can select according to its demand
Baseplate material with suitable dielectric coefficient and resistance value, with adjustment circuit characteristic.It is non-embedding by shortening circuit layout, reduction
The usage quantity of buried electronic unit, and signal transmission distance is reduced to promote the working performance for being embedded into formula encapsulating structure.
Hereinafter, please referring to Figure 1A to Fig. 1 I to briefly describe the manufacturing method for being generally embedded into formula encapsulating structure.Firstly, as schemed
Shown in 1A, incited somebody to action in by drilling, one the first metal layer 11 of plating and consent on a substrate 10 and then with photolithography techniques
Partial the first metal layer 11 removes, with exposed portion substrate 10.Again as shown in Figure 1B, laser etching or punching press side are utilized
Formula removes the substrate 10 for exposing the first metal layer 11, to form multiple apertures 101.Again as shown in Figure 1 C, by above-mentioned by adding
The placement of substrate 10 of work is fixed on the carrier 12 of a such as adhesive tape, and electronic building brick 131 and 132 is directed at corresponding aperture
101 and be fixed on carrier 12.Again as shown in figure iD, it is inserted with a dielectric material 14 and fixes aforesaid substrate 10, the first metal
Layer 11 and electronic building brick 131,132, the first surface 141 then at dielectric material 14 form a second metal layer 15.For another example scheme
Shown in 1E, due to above-mentioned dielectric material 14 fixed substrate 10, the first metal layer 11 and electronic building brick 131,132,
Carrier 12 can be removed, and dielectric material 14 is equally inserted by the opposite other side of second metal layer 15, and in dielectric material 14
Second surface 142 forms a third metal layer 16.
Again as shown in fig. 1F, it is etched using laser and removes part second metal layer 15, part dielectric material 14 and part
Third metal layer 16, to be respectively formed hole H1 ~ H13.Again as shown in Figure 1 G, in hole H1 ~ H13 plating metal to fill up,
So that corresponding the first metal layer 11, second metal layer 15 and third metal layer 16 are electrically connected.Again as shown in fig. 1H,
Part second metal layer 15 and third metal layer 16 are removed again with photolithography techniques.It is last as shown in Figure 1 I, in the second metal
Position appropriate is respectively formed a soldermask layer 17 on layer 15 and third metal layer 16, so just completes one and is embedded into formula encapsulating structure 1.
Above-mentioned is embedded into formula encapsulating structure 1 with following several technological deficiencies: first, the center of electronic building brick 131,132
Distance to second metal layer 15 and third metal layer 16 is identical, and in other words, being embedded into formula encapsulating structure 1 is a symmetrical structure, must
Dual side build-up layers process must be executed, will so qualification rate be made to reduce as shown in Fig. 1 D and Fig. 1 E.
Second, as shown in fig. 1F, since the ball bottom metal layer (UBM) of electronic building brick has to pass through laser etch process, because
This its thickness need to usually reach 1 millimeter, could bear the destruction that the processing procedure is met with.In addition, being blind hole electricity as shown in Figure 1 G
Processing procedure is plated, and because of the reason of processing procedure thus, the ball bottom metal layer (UBM) of electronic building brick is necessarily limited to copper metal, and causes to set
It is insufficient to count elasticity.
Summary of the invention
In view of this, a purpose of the present invention is that providing one kind is embedded into formula encapsulating structure and its manufacturing method, so that tool
Having the chip of different ball bottom metal layers (UBM) can be applicable in.
Another object of the present invention is to provide one kind to be embedded into formula encapsulating structure and its manufacturing method, is not necessarily to limiting ball down payment
Belong to the thickness of layer, and may make that design is more elastic.
Another object of the present invention is to provide one kind to be embedded into formula encapsulating structure and its manufacturing method, when can shorten manufacture
Between.
In order to achieve the above object, the present invention provides a kind of manufacturing method for being embedded into formula encapsulating structure comprising the following steps: step
Rapid S01: in one first conductive pattern layer of formation on a support plate；Step S02: it is led in forming one first in first conductive pattern layer
Electric column layer, and exposed portion first conductive pattern layer；Step S03: it is led in forming one in first conductive pattern layer of exposing
It is electrically coupled layer；Step S04: an electronic building brick is connect with the conducting binding layer；Step S05: formed one cover the electronic building brick,
First dielectric layer of first conductive posts and first conductive pattern layer, and expose a surface of first conductive posts；Step
Rapid S06: in one second conductive pattern layer of formation on first dielectric layer and first conductive posts；Step S07: it second is led in this
One second conductive posts are formed in electrograph pattern layer；Step S08: covering first dielectric layer, second conductive pattern layer is formed
And the second dielectric layer of second conductive posts, and expose a surface of second conductive posts；Step S09: removing the support plate,
It is embedded into formula encapsulating structure to form one.
In addition, in order to achieve the above object, the present invention provides the manufacturing method that another kind is embedded into formula encapsulating structure comprising following
Step: step S11: in one first conductive pattern layer of formation on a support plate；Step S12: first conductive pattern of covering part is formed
The fixing layer of pattern layer；Step S13: an electronic building brick is set on the fixing layer, and exposes an at least electric connection pad；Step
S14: in one first conductive posts of formation in first conductive pattern layer of exposing and the electric connection pad；Step S15: one is formed
First dielectric layer of the electronic building brick, first conductive posts and first conductive pattern layer is covered, and exposes first conduction
One surface of column layer；Step S16: in one second conductive pattern layer of formation on first dielectric layer and first conductive posts；Step
Rapid S17: in one second conductive posts of formation in second conductive pattern layer；Step S18: formed one cover first dielectric layer,
Second dielectric layer of second conductive pattern layer and second conductive posts, and expose a surface of second conductive posts；Step
Rapid S19: removing the support plate, is embedded into formula encapsulating structure to form one.
Wherein, first conductive pattern layer, first conductive posts, second conductive pattern layer and second conductive posts
It is formed with plating, sputter, vapor deposition or photolithography techniques.
Wherein, first conductive pattern layer and at least one of thickness of the second conductive pattern layer are less than 7 microns.
Wherein, which is a metal support plate.
In order to achieve the above object, be embedded into formula encapsulating structure the present invention also provides one kind, including one first dielectric layer, one first lead
Electrograph pattern layer, one first conductive posts, an electronic building brick, one second dielectric layer, one second conductive pattern layer and one second lead
Electric column layer.First dielectric layer has opposite a first surface and a second surface.First conductive pattern layer be set to this first
In dielectric layer, and the first surface of first dielectric layer is exposed on a surface of first conductive pattern layer.First conductive posts
It is set in first dielectric layer, and is electrically connected with first conductive pattern layer, and the surface dew of first conductive posts
Second surface of first dielectric layer out.Electronic building brick is set in first dielectric layer.Second dielectric layer has opposite
One third surface and one the 4th surface.Second conductive pattern layer is set in second dielectric layer, and second conductive pattern layer
A surface expose second dielectric layer the third surface and with expose the second surface first conductive posts electrically connect
It connects.Second conductive posts are set in second dielectric layer, and are electrically connected with second conductive pattern layer, and second conduction
Expose the 4th surface of second dielectric layer in one surface of column layer.
An embodiment according to the present invention, wherein the first conductive pattern layer and second conductive pattern layer are at least within
One thickness is less than 7 microns.
An embodiment according to the present invention, wherein have between electronic building brick and the first surface of first dielectric layer
There is a second distance, the first distance between 4th surface of one first distance, the electronic building brick and second dielectric layer
Different from the second distance.
Wherein, the electronic building brick have an at least electric connection pad, the electric connection pad by a conducting binding layer with
Partially first conductive pattern layer is electrically connected.
Wherein, which has an at least electric connection pad, the electric connection pad and part first conductive posts
It is electrically connected.
Wherein, by a fixing layer, first conductive pattern layer links the electronic building brick with part.
From the above, according to the present invention be embedded into formula encapsulating structure and its processing procedure by stacking in the way of manufactured by, nothing
Substrate need to be used, does not need to produce using relatively time consuming processes such as laser etchings be embedded into electronic building brick in substrate
It is embedded into formula encapsulating structure.Process due to having given up laser etching, the selection of electronic building brick will not be limited to ball down payment
Belong to the thickness of layer and more elastic.
Detailed description of the invention
A kind of Figure 1A to Fig. 1 I: existing production process schematic diagram for being embedded into formula encapsulating structure.
Fig. 2: the one of first embodiment of the invention is embedded into a schematic diagram of formula encapsulating structure.
Fig. 3: another status diagram of the electronic building brick of first embodiment.
Fig. 4: the one of second embodiment of the invention is embedded into a schematic diagram of formula encapsulating structure.
Fig. 5 a: flow chart of the manufacturing method for being embedded into formula encapsulating structure of first embodiment of the invention.
Fig. 6 A to Fig. 6 I: first embodiment of the invention is embedded into the production process schematic diagram of formula encapsulating structure.
Fig. 7 a: flow chart of the manufacturing method for being embedded into formula encapsulating structure of second embodiment of the invention.
Fig. 8 A to Fig. 8 I: second embodiment of the invention is embedded into the production process schematic diagram of formula encapsulating structure.
Description of symbols
1,2,3 are embedded into formula encapsulating structure
10 substrates
101 apertures
11 the first metal layers
12 carriers
131,132 electronic building brick
14 dielectric materials
141,251,351 first surface
142,252,352 second surface
15 second metal layers
16 third metal layers
17 soldermask layers
20,30 support plate
21,31 first conductive pattern layer
211,221,261,271,311,321,361,371 surface
22,32 first conductive posts
23 conducting binding layers
24,24A, 34 electronic building bricks
241,341 electric connection pad
241A copper pillar bumps
25,35 first dielectric layer
26,36 second conductive pattern layer
27,37 second conductive posts
28,38 second dielectric layer
281,381 third surface
282,382 the 4th surface
33 fixing layers
D01, D11 first distance
D02, D12 second distance
H1 ~ H13 hole.
Specific embodiment
The contents of the present invention will be explained by embodiment below, the embodiment of the present invention is not intended to limit the invention palpus
It can implement in any specific environment, application or particular form as described embodiments.Accordingly, with respect to embodiment explanation only
To illustrate the present invention, rather than to limit the present invention.It should be noted that in following embodiment and attached drawing, it is non-straight with the present invention
Relevant component is connect to have been omitted from and be not painted；And the size relationship of each inter-module is only to be readily understood by attached drawing, it is non-to limit
Actual ratio.In addition, identical component will be illustrated in following embodiment with identical component symbol.
Shown in referring to figure 2., the one of first embodiment of the invention is embedded into a schematic diagram of formula encapsulating structure 2.It is embedded into formula envelope
Assembling structure 2 includes one first conductive pattern layer 21, one first conductive posts 22, a conducting binding layer 23, an electronic building brick 24, one
First dielectric layer 25, one second conductive pattern layer 26, one second conductive posts 27 and one second dielectric layer 28.
The material of first dielectric layer 25 may include phenolic group resin (Novolac-Based Resin), epoxy
(Epoxy-Based Resin), silicone (Silicone-Based Resin), with an opposite first surface 251
An and second surface 252.
First conductive pattern layer 21 is set in the first dielectric layer 25, and a surface 211 of the first conductive pattern layer 21 is sudden and violent
It is exposed to the first surface 251 of the first dielectric layer 25, and is exposed to the first conductive pattern of the first surface 251 of the first dielectric layer 25
Layer 21 is substantially same plane with the first surface 251 of the first dielectric layer 25.Wherein, the material of the first conductive pattern layer 21
It for metal, such as, but not limited to copper, can be electroplated, the modes such as sputter or vapor deposition are formed, therefore its thickness is smaller than 1 millimeter
(mm), preferably, less than 7 microns of the thickness of the first conductive pattern layer 21 (um).In this present embodiment, the first conductive pattern layer 21
It may include conducting wire and electric connection pad.
First conductive posts 22 are set in the first dielectric layer 25, and are electrically connected with the first conductive pattern layer 21.First
The second surface 252 of the first dielectric layer 25 is exposed on one surface 221 of conductive posts 22, and is exposed to the second of the first dielectric layer 25
First conductive posts 22 on surface 252 are substantially same plane with the second surface 252 of the first dielectric layer 25.Wherein, first
The modes such as conductive posts 22 can be electroplated, sputter or vapor deposition are formed, and material is metal, such as, but not limited to copper.
Electronic building brick 24 is set in the first dielectric layer 25, and has multiple electric connection pads 241, towards the of part
One conductive pattern layer 21 and be arranged, and be electrically connected by conducting binding layer 23 with corresponding first conductive pattern layer 21.Its
In, the material of electric connection pad 241 is such as, but not limited to copper (Cu), titanium tungsten copper (TiWCu), aluminium (Al) or other metals and electrically connects
Connection pad.In this present embodiment, electronic building brick 24 may include driving component and/or passive component, be not limited in this.It is so-called
Driving component, such as, but not limited to chip (chip), crystal grain (die) or integrated circuit (integrated circuit, IC).
And so-called passive component is then such as, but not limited to capacitor or resistor.In addition, conducting binding layer 23 is such as, but not limited to tin
The material for conductive connection such as cream, tin ball or golden convex block.For example tin cream, for example, to print, put tin cream or spray tin cream etc. side
Formula is formed in the first conductive pattern layer 21.
The material of second dielectric layer 28 may include phenolic group resin (Novolac-Based Resin), epoxy
(Epoxy-Based Resin), silicone (Silicone-Based Resin), with an opposite third surface 281
And one the 4th surface 282.
Second conductive pattern layer 26 is set in the second dielectric layer 28, and a surface 261 dew of the second conductive pattern layer 26
The third surface 281 of second dielectric layer 28 out.Second conductive pattern layer 26 and the second surface 252 of the first dielectric layer 25 of exposing
First conductive posts 22 are electrically connected.It is exposed to second conductive pattern layer 26 on the third surface 281 of the second dielectric layer 28, essence
The upper third surface 281 with the second dielectric layer 28 is same plane.Wherein, the material of the second conductive pattern layer 26 is metal, example
Such as, but not limited to, copper can be formed by modes such as plating, sputter or vapor depositions, therefore its thickness is smaller than 1 millimeter (mm), preferably
, less than 7 microns of the thickness (um) of the second conductive pattern layer 26.
Second conductive posts 27 are set in the second dielectric layer 28, and are electrically connected with the second conductive pattern layer 26, and the
Expose the 4th surface 282 of the second dielectric layer 28 in one surface 271 of two conductive posts 27.It is exposed to the 4th of the second dielectric layer 28 the
Second conductive posts 27 on surface 282 are substantially same plane with the 4th surface 282 of the second dielectric layer 28.Wherein, second
The modes such as conductive posts 27 can be electroplated, sputter or vapor deposition are formed, and material is metal, such as, but not limited to copper.
In addition, it is noted that having one first between electronic building brick 24 and the first surface 251 of the first dielectric layer 25
Distance D01, and there is a second distance D02 between electronic building brick 24 and the 4th surface 282 of the second dielectric layer 28, in this implementation
In example, first distance D01 is different from second distance D02.In other words, it is asymmetric for one by what is laterally seen to be embedded into formula encapsulating structure 2
Formula construction, also therefore the electric connection pad 241 of electronic building brick 24 and the distance between the first conductive pattern layer 21 are shorter, so as to
Shorten electronic transmission path, and then its electrical property efficiency can be increased.
Referring again to shown in Fig. 3, another state of the electronic building brick of first embodiment.In the present embodiment, electronics group
Part 24A can be a copper pillar bumps crystal grain (Cu post die/Cu-pillar die), have as the more of electric connection pad
A copper pillar bumps 241A can effectively shorten the spacing between tin ball or tin cream, thus can increase the pin number of electronic building brick 24A
Amount.
Hereinafter, shown in referring to figure 4., to illustrate that the one of second embodiment of the invention is embedded into formula encapsulating structure 3.
Being embedded into formula encapsulating structure 3 includes one first conductive pattern layer 31, one first conductive posts 32, a fixing layer 33, one
Electronic building brick 34, one first dielectric layer 35, one second conductive pattern layer 36, one second conductive posts 37 and one second dielectric layer
38。
The material of first dielectric layer 35 may include phenolic group resin, epoxy, silicone, with opposite one
First surface 351 and a second surface 352.
First conductive pattern layer 31 is set in the first dielectric layer 35, and a surface 311 of the first conductive pattern layer 31 is sudden and violent
It is exposed to the first surface 351 of the first dielectric layer 35, and is exposed to the first conductive pattern of the first surface 351 of the first dielectric layer 35
Layer 31 is substantially same plane with the first surface 351 of the first dielectric layer 35.Wherein, the material of the first conductive pattern layer 31
It for metal, such as, but not limited to copper, can be electroplated, the modes such as sputter or vapor deposition are formed, therefore its thickness is smaller than 1 millimeter
(mm), preferably, less than 7 microns of the thickness of the first conductive pattern layer 31 (um).In this present embodiment, the first conductive pattern layer 31
It may include conducting wire and electric connection pad.
First conductive posts 32 are set in the first dielectric layer 35, and are electrically connected with the first conductive pattern layer 31.First
The second surface 352 of the first dielectric layer 35 is exposed on one surface 321 of conductive posts 32, and is exposed to the second of the first dielectric layer 35
First conductive posts 32 on surface 352 are substantially same plane with the second surface 352 of the first dielectric layer 35.Wherein, first
The modes such as conductive posts 32 can be electroplated, sputter or vapor deposition are formed, and material is metal, such as, but not limited to copper.
Electronic building brick 34 is set in the first dielectric layer 35, and has multiple electric connection pads 341, conductive towards first
The other side of pattern layer 31 and be arranged.Electronic building brick 34 is connected by fixing layer 33 with corresponding first conductive pattern layer 31.
Fixing layer 33 such as, but not limited to combines glue (glue) or combination film (film).It is noted that the first conductive column of part
Layer 32 is electrically connected with electric connection pad 341.
The material of the electric connection pad 341 of electronic building brick 34 is such as, but not limited to copper, titanium tungsten copper, aluminium or other metals.In
In the present embodiment, electronic building brick 34 may include driving component and/or passive component, be not limited in this.So-called active set
Part, such as, but not limited to chip, crystal grain or integrated circuit.And so-called passive component is then such as, but not limited to capacitor or resistance
Device.
The material of second dielectric layer 38 may include phenolic group resin, epoxy, silicone, with opposite one
Third surface 381 and one the 4th surface 382.
Second conductive pattern layer 36 is set in the second dielectric layer 38, and a surface 361 dew of the second conductive pattern layer 36
The third surface 381 of second dielectric layer 38 out.Second conductive pattern layer 36 and the second surface 352 of the first dielectric layer 35 of exposing
First conductive posts 32 are electrically connected.It is exposed to second conductive pattern layer 36 on the third surface 381 of the second dielectric layer 38, essence
The upper third surface 381 with the second dielectric layer 38 is same plane.Wherein, the material of the second conductive pattern layer 36 is metal, example
Such as, but not limited to, copper, can be electroplated, the modes such as sputter or vapor deposition are formed, therefore its thickness is smaller than 1 millimeter (mm), preferably,
The thickness of second conductive pattern layer 36 is less than 7 microns (μm).
Second conductive posts 37 are set in the second dielectric layer 38, and are electrically connected with the second conductive pattern layer 36, and the
Expose the 4th surface 382 of the second dielectric layer 38 in one surface 371 of two conductive posts 37.It is exposed to the 4th of the second dielectric layer 38 the
Second conductive posts 37 on surface 382 are substantially same plane with the 4th surface 382 of the second dielectric layer 38.Wherein, second
The modes such as conductive posts 37 can be electroplated, sputter or vapor deposition are formed, and material is metal, such as, but not limited to copper.
In addition, being identical with the first embodiment, have one between electronic building brick 34 and the first surface 351 of the first dielectric layer 35
First distance D11, and there is a second distance D12, Yu Ben between electronic building brick 34 and the 4th surface 382 of the second dielectric layer 38
In embodiment, first distance D11 is different from second distance D12.In other words, it is non-for one by what is laterally seen to be embedded into formula encapsulating structure 3
Symmetrical expression construction, also therefore the electric connection pad 341 of electronic building brick 34 and the distance between the first conductive pattern layer 31 are shorter, and
Electronic transmission path can be shortened, and then its electrical property efficiency can be increased.
It is a process of the manufacturing method for being embedded into formula encapsulating structure 2 of first embodiment of the invention shown in referring to figure 5.
Figure comprising step S01 to step S09.Fig. 6 A to Fig. 6 I arrange in pairs or groups below to illustrate the manufacturing method for being embedded into formula encapsulating structure 2.
Step S01, as shown in Figure 6A, in one first conductive pattern layer 21 of formation on a support plate 20.Wherein, support plate 20 is one
Metal support plate, such as, but not limited to stainless steel copper facing.First conductive pattern layer 21 can be micro- using plating, sputter, vapor deposition or collocation
The technologies such as image etching procedure are formed on support plate 20.
Step S02, as shown in Figure 6B, in one first conductive posts 22 of formation in the first conductive pattern layer 21.Wherein, first
The first conductive pattern layer 21 is not completely covered in conductive posts 22, i.e. the first conductive pattern layer of part 21 is to expose.First leads
Electric column layer 22 can be formed in the first conductive pattern layer 21 using technologies such as plating, sputter, vapor deposition or collocation micro image etching procedures.
Step S03, as shown in Figure 6 C, in forming a conducting binding layer 23 in the first conductive pattern layer 21 of exposing.It is conductive
Binder course 23 is such as, but not limited to the material for conductive connection such as tin cream, tin ball or golden convex block.For example tin cream, such as with print
The modes such as brush, point tin cream or spray tin cream are formed in the first conductive pattern layer 21.
One electronic building brick 24 is connect by step S04 with conducting binding layer 23 as shown in Figure 6 D.It is using back welding process
So that the electric connection pad 241 of electronic building brick 24 and the first conductive pattern layer 21 are electrically connected by conducting binding layer 23.
Step S05 forms an overlay electronic component 24, the first conductive posts 22 and the first conductive pattern as illustrated in fig. 6e
First dielectric layer 25 of layer 21, and the polished surface 221 for exposing the first conductive posts 22.
Step S06, as fig 6 f illustrates, in one second conductive pattern of formation on the first dielectric layer 25 and the first conductive posts 22
Layer 26.Second conductive pattern layer 26 can be formed in first Jie using technologies such as plating, sputter, vapor deposition or collocation micro image etching procedures
In electric layer 25 and the first conductive posts 22.
Step S07, as shown in Figure 6 G, in one second conductive posts 27 of formation in the second conductive pattern layer 26.Second is conductive
Column layer 27 can be formed in the second conductive pattern layer 26 using technologies such as plating, sputter, vapor deposition or collocation micro image etching procedures.
It is conductive to form first dielectric layer 25 of covering, the second conductive pattern layer 26 and second as shown in figure 6h by step S08
Second dielectric layer 28 of column layer 27, and expose a surface 271 of the second conductive posts 27 after ground processing procedure.
Shown in step S09, collocation Fig. 6 H and Fig. 6 I, after removing support plate 20 and making 180 degree overturning, it is embedded into formula envelope to form one
Assembling structure 2.Wherein, support plate 20 can be such as, but not limited to using etch process (Etching process), removing processing procedure
(Debonding process) or grinding processing procedure remove it.
It please refers to shown in Fig. 7, is a process of the manufacturing method for being embedded into formula encapsulating structure 3 of second embodiment of the invention
Figure comprising step S11 to step S19.Fig. 8 A to Fig. 8 I arrange in pairs or groups below to illustrate the manufacturing method for being embedded into formula encapsulating structure 3.
Step S11, as shown in Figure 8 A, in one first conductive pattern layer 31 of formation on a support plate 30.Wherein, support plate 30 is one
Metal support plate, such as, but not limited to stainless steel copper facing.First conductive pattern layer 31 can be micro- using plating, sputter, vapor deposition or collocation
The technologies such as image etching procedure are formed on support plate 30.
Step S12 forms the fixing layer 33 of first conductive pattern layer of covering part 31 as shown in Figure 8 B.Fixing layer 33
Glue or combination film are such as, but not limited to combined, the first conductive pattern layer can be formed in using coating process or dispensing processing procedure
On 31.
One electronic building brick 34 is set on fixing layer 33 by step S13 as shown in Figure 8 C, and is exposed at least one and electrically connected
Connection pad 341.In this present embodiment, electronic building brick 34 is fixed on support plate 30 by the stickiness of fixing layer 33.
Step S14, as in fig. 8d, in forming one the in the first conductive pattern layer 31 and electric connection pad 341 of exposing
One conductive posts 32.Wherein, the first conductive posts 32 can be using technologies such as plating, sputter, vapor deposition or collocation micro image etching procedures
It is formed on the first conductive pattern layer 31 and electric connection pad 341.
Step S15 forms an overlay electronic component 34, the first conductive posts 32 and the first conductive pattern as illustrated in fig. 8e
First dielectric layer 35 of layer 31, and the polished surface 321 for exposing the first conductive posts 32.
Step S16, as shown in Figure 8 F, in one second conductive pattern of formation on the first dielectric layer 35 and the first conductive posts 32
Layer 36.Second conductive pattern layer 36 can be formed in first Jie using technologies such as plating, sputter, vapor deposition or collocation micro image etching procedures
In electric layer 35 and the first conductive posts 32.
Step S17, as shown in fig. 8g, in one second conductive posts 37 of formation in the second conductive pattern layer 36.Second is conductive
Column layer 37 can be formed in the second conductive pattern layer 36 using technologies such as plating, sputter, vapor deposition or collocation micro image etching procedures.
It is conductive to form first dielectric layer 35 of covering, the second conductive pattern layer 36 and second as illustrated in figure 8h by step S18
Second dielectric layer 38 of column layer 37, and the polished surface 371 for exposing the second conductive posts 37.
Step S19 removes support plate 30 and makees 180 degree overturning as shown in Fig. 8 H and Fig. 8 I, is embedded into formula encapsulation knot to form one
Structure 3.Wherein, support plate 30 such as, but not limited to can remove it using etch process, removing processing procedure or grinding processing procedure.
In conclusion one kind according to the present invention is embedded into formula encapsulating structure and its processing procedure, manufactured in the way of stacking,
Without using substrate, do not need to produce using time-consuming processes such as laser etchings be embedded into electronic building brick in substrate
It is embedded into formula encapsulating structure.Process due to having given up laser etching, the selection of electronic building brick will not be limited to ball down payment
Belong to the thickness of layer and more elastic.In addition, to be embedded into formula encapsulating structure by side sight be asymmetric due to of the invention, i.e., it is electric
The distance between sub-component and the first conductive pattern layer are shorter, and can shorten electronic transmission path, and then can increase it and electrically imitate
Energy.
The present invention meets the application condition of patent of invention, therefore proposes patent application in accordance with the law.But the foregoing is merely the present invention
Preferred embodiment, the scope of patent protection of the application cannot be limited with this.Those skilled in the art are according to the technology of the application
Equivalent modification or variation made by scheme should belong to scope of patent protection of the invention.
Claims (10)
1. a kind of manufacturing method for being embedded into formula encapsulating structure, it is characterised in that: comprising:
In forming one first conductive pattern layer by electroplating technology on a metal support plate；
In forming one first conductive posts by electroplating technology in first conductive pattern layer, and this is first conductive for exposed portion
Pattern layer；
In forming a conducting binding layer in first conductive pattern layer of exposing；
One electronic building brick is connect with the conducting binding layer；
It forms one and covers the first dielectric layer of the electronic building brick, first conductive posts and first conductive pattern layer, and expose
One surface of first conductive posts；
In forming one second conductive pattern layer by electroplating technology on first dielectric layer and first conductive posts；
In forming one second conductive posts by electroplating technology in second conductive pattern layer；
It forms one and covers the second dielectric layer of first dielectric layer, second conductive pattern layer and second conductive posts, and reveal
A surface of second conductive posts out；And
Remove the metal support plate.
2. being embedded into the manufacturing method of formula encapsulating structure as described in claim 1, it is characterised in that: first conductive pattern layer and
At least one of thickness of second conductive pattern layer is less than 7 microns.
3. a kind of manufacturing method for being embedded into formula encapsulating structure, it is characterised in that: include:
In forming one first conductive pattern layer by electroplating technology on a metal support plate；
Form the fixing layer of first conductive pattern layer of covering part；
One electronic building brick is set on the fixing layer, and exposes an at least electric connection pad；
In forming one first conductive posts by electroplating technology in first conductive pattern layer of exposing and the electric connection pad；
It forms one and covers the first dielectric layer of the electronic building brick, first conductive posts and first conductive pattern layer, and expose
One surface of first conductive posts；
In forming one second conductive pattern layer by electroplating technology on first dielectric layer and first conductive posts；
In forming one second conductive posts by electroplating technology in second conductive pattern layer；
It forms one and covers the second dielectric layer of first dielectric layer, second conductive pattern layer and second conductive posts, and reveal
A surface of second conductive posts out；And
Remove the metal support plate.
4. being embedded into the manufacturing method of formula encapsulating structure as claimed in claim 3, it is characterised in that: first conductive pattern layer and
At least one of thickness of second conductive pattern layer is less than 7 microns.
5. one kind is embedded into formula encapsulating structure, it is characterised in that: it is prepared by method comprising the following steps, comprising:
In forming one first conductive pattern layer by electroplating technology on a metal support plate；
In forming one first conductive posts by electroplating technology in first conductive pattern layer, and this is first conductive for exposed portion
Pattern layer；
In forming a conducting binding layer in first conductive pattern layer of exposing；
One electronic building brick is connect with the conducting binding layer；
First dielectric layer for covering the electronic building brick, first conductive posts and first conductive pattern layer is formed, this first
Dielectric layer have opposite a first surface and a second surface, and wherein a surface of first conductive posts from this first be situated between
The second surface of electric layer exposes；
In forming one second conductive pattern layer by electroplating technology on first dielectric layer and first conductive posts；
In forming one second conductive posts by electroplating technology in second conductive pattern layer；
Second dielectric layer for covering first dielectric layer, second conductive pattern layer and second conductive posts is formed, this
Two dielectric layers have opposite a third surface and one the 4th surface, and wherein a surface of second conductive posts from this second
Expose on 4th surface of dielectric layer；And
Remove the metal support plate.
6. being embedded into formula encapsulating structure as claimed in claim 5, it is characterised in that: the electronic building brick is electrically connected at least one
Pad, by the conducting binding layer, first conductive pattern layer is electrically connected the electric connection pad with part.
7. being embedded into formula encapsulating structure as claimed in claim 5, it is characterised in that: the electronic building brick is electrically connected at least one
Pad, the electric connection pad and part first conductive posts are electrically connected.
8. one kind is embedded into formula encapsulating structure, it is characterised in that: it is prepared by method comprising the following steps, comprising:
In forming one first conductive pattern layer by electroplating technology on a metal support plate；
Form the fixing layer of first conductive pattern layer of covering part；
One electronic building brick is set on the fixing layer, and exposes an at least electric connection pad；,
In forming one first conductive posts by electroplating technology in first conductive pattern layer of exposing and the electric connection pad；
First dielectric layer for covering the electronic building brick, first conductive posts and first conductive pattern layer is formed, this first
Dielectric layer have opposite a first surface and a second surface, and wherein a surface of first conductive posts from this first be situated between
The second surface of electric layer exposes；
In forming one second conductive pattern layer by electroplating technology on first dielectric layer and first conductive posts；
In forming one second conductive posts by electroplating technology in second conductive pattern layer；
Second dielectric layer for covering first dielectric layer, second conductive pattern layer and second conductive posts is formed, this
Two dielectric layers have opposite a third surface and one the 4th surface, and wherein a surface of second conductive posts from this second
Expose on 4th surface of dielectric layer；And
Remove the metal support plate.
9. being embedded into formula encapsulating structure as described in claim 5 or 8, it is characterised in that: first conductive pattern layer and this second
At least one of thickness of conductive pattern layer is less than 7 microns.
10. being embedded into formula encapsulating structure as described in claim 5 or 8, it is characterised in that: the electronic building brick and first dielectric layer
The first surface between have a first distance, between the electronic building brick and the 4th surface of second dielectric layer have one
Second distance, the first distance are different from the second distance.
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| TW200807661A (en) * | 2006-07-28 | 2008-02-01 | Phoenix Prec Technology Corp | Circuit board structure having passive component and stack structure thereof |
| CN102214626A (en) * | 2010-12-17 | 2011-10-12 | 日月光半导体制造股份有限公司 | Built-in type semiconductor package and manufacturing method thereof |
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