CN106449420A - Embedded type packaging structure and the manufacturing method thereof - Google Patents
Embedded type packaging structure and the manufacturing method thereof Download PDFInfo
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- CN106449420A CN106449420A CN201510472785.7A CN201510472785A CN106449420A CN 106449420 A CN106449420 A CN 106449420A CN 201510472785 A CN201510472785 A CN 201510472785A CN 106449420 A CN106449420 A CN 106449420A
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- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 238000004806 packaging method and process Methods 0.000 title abstract description 3
- 239000011469 building brick Substances 0.000 claims description 58
- 238000000034 method Methods 0.000 claims description 53
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 230000008020 evaporation Effects 0.000 claims description 19
- 238000001704 evaporation Methods 0.000 claims description 19
- 238000000206 photolithography Methods 0.000 claims description 5
- 239000010949 copper Substances 0.000 description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 17
- 229910052802 copper Inorganic materials 0.000 description 17
- 239000000463 material Substances 0.000 description 17
- 238000007747 plating Methods 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 15
- 239000000758 substrate Substances 0.000 description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 12
- 238000012545 processing Methods 0.000 description 12
- 239000011347 resin Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- 239000006071 cream Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000010329 laser etching Methods 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 4
- 229920001296 polysiloxane Polymers 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- CPFNXHQBAHTVKB-UHFFFAOYSA-N [Ti].[Cu].[W] Chemical compound [Ti].[Cu].[W] CPFNXHQBAHTVKB-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention provides an embedded type packaging structure, comprising a first dielectric layer, a first conductive pattern layer, a first conductive pole layer, an electronic assembly, a second dielectric layer, a second conductive pattern layer and a second conductive pole layer. The first conductive pattern layer, the first conductive pole layer and the electronic assembly are arranged in the first dielectric layer. One surface of the first conductive pattern layer exposes out of the first surface of the first dielectric layer. One surface of the first conductive pole layer exposes out of the second surface of the first dielectric layer. The second conductive pattern layer and the second conductive pole layer are arranged in the second dielectric layer. One surface of the second conductive pattern layer exposes out of the third surface of the second dielectric layer, and is electrically connected with the first conductive pole that exposes out of the second surface. One surface of the second conductive pole layer exposes out of the fourth surface of the second dielectric layer.
Description
Technical field
The present invention relates to a kind of encapsulating structure and its manufacture method, it is embedded into formula encapsulating structure and its manufacture method particularly to one kind.
Background technology
In today of social advanced IT application, multimedia application market constantly explosion, integrated antenna package technology is also therewith towards the digitized of electronic installation, networking, region connectionization and the trend development using hommization.For meeting above-mentioned requirement, electronic building brick must coordinate high speed processing, multifunction, productive set（Integrated）And many requirements such as miniaturization, integrated antenna package technology is also therefore and then towards miniaturization, densification development.Wherein, ball lattice array type construction（Ball Grid
Array, BGA）, chip size construction（Chip-Scale
Package, CSP）, flip construction（Flip
Chip Package, F/C）, multi-chip module（Multi-Chip
Module, MCM）Also arise at the historic moment Deng high density integrated circuit encapsulation technology.
Wherein, flip constructing technology is mainly external contact on being formed with the wafer of multiple chips（Typically wafer weld pad）Upper formation ball bottom metal layer（UBM, Under Bump
Metallurgy）, then in ball bottom metal layer upper formation projection or implantation soldered ball using as follow-up chip（Or wafer）With substrate（substrate）The connecting interface electrically conducting.Because flip constructing technology can be applicable to high pin number（High Pin Count）Chip-packaging structure, and have simultaneously and reduce package area and shorten the multiple advantages such as signal transmission path, so flip constructing technology has been widely used in chip package field.
And, in order to be able to create bigger space in limited substrate area to lift the function of electronic installation, electronic building brick is embedded in substrate prior art, it is embedded into formula encapsulating structure to form one.User can be according to its demand, from the baseplate material with suitable dielectric coefficient and resistance value, with adjustment circuit characteristic.It is shortened by circuit layout, reduces the non-usage quantity being embedded into formula electronic unit, and reduce signal transmission distance to lift the service behaviour being embedded into formula encapsulating structure.
Hereinafter, refer to Figure 1A to Fig. 1 I to briefly describe the manufacture method being typically embedded into formula encapsulating structure.First, as shown in Figure 1A, on a substrate 10 after boring, plating one the first metal layer 11 and consent, then with photolithography techniques, the first metal layer 11 of part is removed, with exposed portion substrate 10.Again as shown in Figure 1B, using laser etching or impact style, the substrate 10 exposing the first metal layer 11 is removed, to form multiple perforates 101.Again as shown in Figure 1 C, the above-mentioned substrate 10 through processing is placed and be fixed on the carrier 12 of a such as adhesive tape, and perforate 101 corresponding for electronic building brick 131 and 132 be aligned is fixed on carrier 12.Again as shown in figure ip, inserted with a dielectric material 14 and fix aforesaid substrate 10, the first metal layer 11 and electronic building brick 131,132, the first surface 141 then at dielectric material 14 forms a second metal layer 15.Again as referring to figure 1e, due to the fixing substrate 10 of above-mentioned dielectric material 14, the first metal layer 11 and electronic building brick 131,132, therefore removable carrier 12, and equally insert dielectric material 14 by the relative opposite side of second metal layer 15, and the second surface 142 in dielectric material 14 forms one the 3rd metal level 16.
Again as shown in fig. 1f, part second metal layer 15, part dielectric material 14 and part the 3rd metal level 16 are removed using laser etching, to form hole H1 ~ H13 respectively.Again as shown in Figure 1 G, in hole H1 ~ H13 plated metal to fill up so that corresponding the first metal layer 11, second metal layer 15 and the 3rd metal level 16 are electrically connected with.Again as shown in fig. 1h, then with photolithography techniques part second metal layer 15 and the 3rd metal level 16 are removed.As shown in Figure 1 I, in second metal layer 15 and the 3rd metal level 16, suitable position forms a welding resisting layer 17 respectively, so just completes one and is embedded into formula encapsulating structure 1 finally.
The above-mentioned formula encapsulating structure 1 that is embedded into has following several technological deficiencies：First, the center of electronic building brick 131,132 is identical to the distance of second metal layer 15 and the 3rd metal level 16, and in other words, being embedded into formula encapsulating structure 1 is a symmetrical structure it is necessary to as shown in Fig. 1 D and Fig. 1 E, execute dual side build-up layers operation, and qualification rate so will be made to reduce.
Second, as shown in fig. 1f, due to the ball bottom metal layer of electronic building brick（UBM）Have to pass through laser etch process, therefore its thickness generally need to reach 1 millimeter, just can bear the destruction that this processing procedure is met with.In addition, as shown in Figure 1 G, it is blind hole electroplating process, and because this processing procedure, the ball bottom metal layer of electronic building brick（UBM）It is necessarily limited to copper metal, and lead to design flexibility degree not enough.
Content of the invention
In view of this, a purpose of the present invention is to provide one kind to be embedded into formula encapsulating structure and its manufacture method so that having different ball bottom metal layer（UBM）Chip can be suitable for.
Another object of the present invention is to providing one kind to be embedded into formula encapsulating structure and its manufacture method, the thickness of ball bottom metal layer need not be limited, and design can be made to have more elasticity.
A further object of the present invention is to provide one kind to be embedded into formula encapsulating structure and its manufacture method, and it can shorten manufacturing time.
For reaching above-mentioned purpose, the present invention provides a kind of manufacture method being embedded into formula encapsulating structure, and it comprises the following steps：Step S01：One first conductive pattern layer is formed on a support plate；Step S02：Form one first conductive posts in this first conductive pattern layer, and this first conductive pattern layer of exposed portion；Step S03：Form a conducting binding layer in this first conductive pattern layer exposed；Step S04：One electronic building brick is connected with this conducting binding layer；Step S05：Form first dielectric layer covering this electronic building brick, this first conductive posts and this first conductive pattern layer, and expose a surface of this first conductive posts；Step S06：One second conductive pattern layer is formed on this first dielectric layer and this first conductive posts；Step S07：One second conductive posts are formed on this second conductive pattern layer；Step S08：Form second dielectric layer covering this first dielectric layer, this second conductive pattern layer and this second conductive posts, and expose a surface of this second conductive posts；Step S09：Remove this support plate, be embedded into formula encapsulating structure to form one.
In addition, for reaching above-mentioned purpose, the present invention provides another kind to be embedded into the manufacture method of formula encapsulating structure, and it comprises the following steps：Step S11：One first conductive pattern layer is formed on a support plate；Step S12：Form the fixed layer of covering part first conductive pattern layer；Step S13：One electronic building brick is arranged on this fixed layer, and exposes at least one electric connection pad；Step S14：One first conductive posts are formed on this first conductive pattern layer exposed and this electric connection pad；Step S15：Form first dielectric layer covering this electronic building brick, this first conductive posts and this first conductive pattern layer, and expose a surface of this first conductive posts；Step S16：One second conductive pattern layer is formed on this first dielectric layer and this first conductive posts；Step S17：One second conductive posts are formed on this second conductive pattern layer；Step S18：Form second dielectric layer covering this first dielectric layer, this second conductive pattern layer and this second conductive posts, and expose a surface of this second conductive posts；Step S19：Remove this support plate, be embedded into formula encapsulating structure to form one.
Wherein, this first conductive pattern layer, this first conductive posts, this second conductive pattern layer and this second conductive posts to electroplate, sputter, evaporation or photolithography techniques are formed.
Wherein, this first conductive pattern layer and this at least one of thickness of the second conductive pattern layer are less than 7 microns.
Wherein, this support plate is a metal support plate.
For reaching above-mentioned purpose, the present invention also provides one kind to be embedded into formula encapsulating structure, including one first dielectric layer, one first conductive pattern layer, one first conductive posts, an electronic building brick, one second dielectric layer, one second conductive pattern layer and one second conductive posts.First dielectric layer has a relative first surface and a second surface.First conductive pattern layer is arranged in this first dielectric layer, and this first surface of this first dielectric layer is exposed on a surface of this first conductive pattern layer.First conductive posts are arranged in this first dielectric layer, and are electrically connected with this first conductive pattern layer, and this second surface of this first dielectric layer is exposed on a surface of this first conductive posts.Electronic building brick is arranged in this first dielectric layer.Second dielectric layer has one the 3rd relative surface and one the 4th surface.Second conductive pattern layer is arranged in this second dielectric layer, and a surface of this second conductive pattern layer is exposed the 3rd surface of this second dielectric layer and is electrically connected with this first conductive posts exposing this second surface.Second conductive posts are arranged in this second dielectric layer, and are electrically connected with this second conductive pattern layer, and the 4th surface of this second dielectric layer is exposed on a surface of this second conductive posts.
According to one embodiment of the invention, wherein, the first conductive pattern layer and this second conductive pattern layer one thickness at least within is less than 7 microns.
According to one embodiment of the invention, wherein, there is between this first surface of electronic building brick and this first dielectric layer one first distance, between this electronic building brick and the 4th surface of this second dielectric layer, there is a second distance, this first distance is different from this second distance.
Wherein, this electronic building brick has at least one electric connection pad, and this electric connection pad is electrically connected with this first conductive pattern layer of part by a conducting binding layer.
Wherein, this electronic building brick has at least one electric connection pad, and this electric connection pad is electrically connected with this first conductive posts of part.
Wherein, this electronic building brick is linked with this first conductive pattern layer of part by a fixed layer.
From the above, it is embedded into formula encapsulating structure and its processing procedure using manufactured by the mode of stacking according to the present invention, it is without using substrate it is not necessary to make electronic building brick be embedded in substrate to produce and be embedded into formula encapsulating structure using relatively time consuming operations such as laser etchings.Due to having given up the operation of laser etching, the therefore selection of electronic building brick will not be limited to the thickness of ball bottom metal layer and more elastic.
Brief description
Figure 1A to Fig. 1 I：A kind of existing production process schematic diagram being embedded into formula encapsulating structure.
Fig. 2：The one of first embodiment of the invention is embedded into a schematic diagram of formula encapsulating structure.
Fig. 3：Another view of the electronic building brick of first embodiment.
Fig. 4：The one of second embodiment of the invention is embedded into a schematic diagram of formula encapsulating structure.
Fig. 5：One flow chart of the manufacture method being embedded into formula encapsulating structure of first embodiment of the invention.
Fig. 6 A to Fig. 6 I：First embodiment of the invention is embedded into the production process schematic diagram of formula encapsulating structure.
Fig. 7：One flow chart of the manufacture method being embedded into formula encapsulating structure of second embodiment of the invention.
Fig. 8 A to Fig. 8 I：Second embodiment of the invention is embedded into the production process schematic diagram of formula encapsulating structure.
Description of reference numerals
1、2、3
It is embedded into formula encapsulating structure
10
Substrate
101
Perforate
11
The first metal layer
12
Carrier
131、132
Electronic building brick
14
Dielectric material
141、251、351
First surface
142、252、352
Second surface
15
Second metal layer
16
3rd metal level
17
Welding resisting layer
20、30
Support plate
21、31
First conductive pattern layer
211st, 221,261,271,311,321,361,371 surface
22、32
First conductive posts
23
Conducting binding layer
24、24A、34
Electronic building brick
241、341
Electric connection pad
241A
Copper pillar bumps
25、35
First dielectric layer
26、36
Second conductive pattern layer
27、37
Second conductive posts
28、38
Second dielectric layer
281、381
3rd surface
282、382
4th surface
33
Fixed layer
D01、D11
First distance
D02、D12
Second distance
H1~H13
Hole.
Specific embodiment
Present disclosure below will be explained by embodiment, embodiments of the invention are simultaneously not used to limit the present invention and can must implement in any specific environment as described embodiments, application or particular form.Explanation accordingly, with respect to embodiment only explains the present invention, and is not used to limit the present invention.It should be noted that in following examples and accompanying drawing, related assembly non-immediate to the present invention has been omitted from and does not illustrate；And the size relationship of each inter-module is only readily understood by accompanying drawing, it is not used to limit actual ratio.In addition, in following examples, identical assembly will be illustrated with identical element numbers.
Refer to shown in Fig. 2, the one of first embodiment of the invention is embedded into a schematic diagram of formula encapsulating structure 2.It is embedded into formula encapsulating structure 2 and include one first conductive pattern layer 21, one first conductive posts 22, a conducting binding layer 23, an electronic building brick 24, one first dielectric layer 25, one second conductive pattern layer 26, one second conductive posts 27 and one second dielectric layer 28.
The material of the first dielectric layer 25 may include phenolic group resin（Novolac-Based
Resin）, epoxy（Epoxy-Based Resin）, silicone（Silicone-Based Resin）, it has a relative first surface 251 and a second surface 252.
First conductive pattern layer 21 is arranged in the first dielectric layer 25, and first a surface 211 of conductive pattern layer 21 be exposed to the first surface 251 of the first dielectric layer 25, and it is exposed to the first conductive pattern layer 21 of the first surface 251 of the first dielectric layer 25, it is same plane substantially with the first surface 251 of the first dielectric layer 25.Wherein, the material of the first conductive pattern layer 21 is metal, such as but not limited to copper, and it can be formed in modes such as plating, sputter or evaporations, therefore its thickness is smaller than 1 millimeter（mm）, preferably, the thickness of the first conductive pattern layer 21 is less than 7 microns（um）.In the present embodiment, the first conductive pattern layer 21 may include conducting wire and electric connection pad.
First conductive posts 22 are arranged in the first dielectric layer 25, and are electrically connected with the first conductive pattern layer 21.The second surface 252 of the first dielectric layer 25 is exposed on one surface 221 of the first conductive posts 22, and is exposed to the first conductive posts 22 of the second surface 252 of the first dielectric layer 25, is same plane substantially with the second surface 252 of the first dielectric layer 25.Wherein, the first conductive posts 22 can be formed in modes such as plating, sputter or evaporations, and its material is metal, such as but not limited to copper.
Electronic building brick 24 is arranged in the first dielectric layer 25, and has multiple electric connection pads 241, its first conductive pattern layer 21 towards part and arrange, and be electrically connected with corresponding first conductive pattern layer 21 by conducting binding layer 23.Wherein, the material of electric connection pad 241 is such as, but not limited to copper（Cu）, titanium tungsten copper（TiWCu）, aluminum（Al）Or other metal electric connection pads.In the present embodiment, electronic building brick 24 may include driving component and/or passive component, is not limited in this.So-called driving component, such as but not limited to chip（chip）, crystal grain（die）Or integrated circuit（integrated
circuit, IC）.And so-called passive component then such as but not limited to capacitor or resistor.In addition, conducting binding layer 23 is such as, but not limited to tin cream, stannum ball or golden projection etc. for the material being conductively connected.As for tin cream, it is for example to print, the mode such as point tin cream or spray tin cream is formed in the first conductive pattern layer 21.
The material of the second dielectric layer 28 may include phenolic group resin（Novolac-Based
Resin）, epoxy（Epoxy-Based Resin）, silicone（Silicone-Based Resin）, it has one the 3rd relative surface 281 and one the 4th surface 282.
Second conductive pattern layer 26 is arranged in the second dielectric layer 28, and the 3rd surface 281 of the second dielectric layer 28 is exposed on a surface 261 of the second conductive pattern layer 26.Second conductive pattern layer 26 is electrically connected with the first conductive posts 22 of the second surface 252 exposing the first dielectric layer 25.It is exposed to second conductive pattern layer 26 on the 3rd surface 281 of the second dielectric layer 28, be same plane substantially with the 3rd surface 281 of the second dielectric layer 28.Wherein, the material of the second conductive pattern layer 26 is metal, such as but not limited to copper, and it can be formed by modes such as plating, sputter or evaporations, therefore its thickness is smaller than 1 millimeter（mm）, preferably, the thickness of the second conductive pattern layer 26 is less than 7 microns（um）.
Second conductive posts 27 are arranged in the second dielectric layer 28, and are electrically connected with the second conductive pattern layer 26, and the 4th surface 282 of the second dielectric layer 28 is exposed on a surface 271 of the second conductive posts 27.It is exposed to second conductive posts 27 on the 4th surface 282 of the second dielectric layer 28, be same plane substantially with the 4th surface 282 of the second dielectric layer 28.Wherein, the second conductive posts 27 can be formed in modes such as plating, sputter or evaporations, and its material is metal, such as but not limited to copper.
In addition, it is noted that having one first apart from D01 between the first surface 251 of electronic building brick 24 and the first dielectric layer 25, and there is between the 4th surface 282 of electronic building brick 24 and the second dielectric layer 28 a second distance D02, in the present embodiment, first is different from second distance D02 apart from D01.In other words, it is embedded into formula encapsulating structure 2 by laterally seeing as an asymmetric construction, also therefore the distance between the electric connection pad 241 of electronic building brick 24 and first conductive pattern layer 21 are shorter, thus electronic transmission path can be shortened, and then can increase its electrical property efficiency.
Referring again to shown in Fig. 3, another kind of state of the electronic building brick of first embodiment.In the present embodiment, electronic building brick 24A can be a copper pillar bumps crystal grain（Cu post die / Cu-pillar die）, it has multiple copper pillar bumps 241A as electric connection pad, can effectively shorten the spacing between stannum ball or tin cream, thus can increase the pin number amount of electronic building brick 24A.
Hereinafter, refer to shown in Fig. 4, one be embedded into formula encapsulating structure 3 with what second embodiment of the invention was described.
It is embedded into formula encapsulating structure 3 and include one first conductive pattern layer 31, one first conductive posts 32, a fixed layer 33, an electronic building brick 34, one first dielectric layer 35, one second conductive pattern layer 36, one second conductive posts 37 and one second dielectric layer 38.
The material of the first dielectric layer 35 may include phenolic group resin, epoxy, silicone, and it has a relative first surface 351 and a second surface 352.
First conductive pattern layer 31 is arranged in the first dielectric layer 35, and first a surface 311 of conductive pattern layer 31 be exposed to the first surface 351 of the first dielectric layer 35, and it is exposed to the first conductive pattern layer 31 of the first surface 351 of the first dielectric layer 35, it is same plane substantially with the first surface 351 of the first dielectric layer 35.Wherein, the material of the first conductive pattern layer 31 is metal, such as but not limited to copper, and it can be formed in modes such as plating, sputter or evaporations, therefore its thickness is smaller than 1 millimeter（mm）, preferably, the thickness of the first conductive pattern layer 31 is less than 7 microns（um）.In the present embodiment, the first conductive pattern layer 31 may include conducting wire and electric connection pad.
First conductive posts 32 are arranged in the first dielectric layer 35, and are electrically connected with the first conductive pattern layer 31.The second surface 352 of the first dielectric layer 35 is exposed on one surface 321 of the first conductive posts 32, and is exposed to the first conductive posts 32 of the second surface 352 of the first dielectric layer 35, is same plane substantially with the second surface 352 of the first dielectric layer 35.Wherein, the first conductive posts 32 can be formed in modes such as plating, sputter or evaporations, and its material is metal, such as but not limited to copper.
Electronic building brick 34 is arranged in the first dielectric layer 35, and has multiple electric connection pads 341, and it is arranged towards opposite side of the first conductive pattern layer 31.Electronic building brick 34 is connected with corresponding first conductive pattern layer 31 by fixed layer 33.Fixed layer 33 such as but not limited to combines glue（glue）Or combination film（film）.It is noted that part the first conductive posts 32 and electric connection pad 341 are electrically connected with.
The material of the electric connection pad 341 of electronic building brick 34 is such as, but not limited to copper, titanium tungsten copper, aluminum or other metals.In the present embodiment, electronic building brick 34 may include driving component and/or passive component, is not limited in this.So-called driving component, such as but not limited to chip, crystal grain or integrated circuit.And so-called passive component then such as but not limited to capacitor or resistor.
The material of the second dielectric layer 38 may include phenolic group resin, epoxy, silicone, and it has one the 3rd relative surface 381 and one the 4th surface 382.
Second conductive pattern layer 36 is arranged in the second dielectric layer 38, and the 3rd surface 381 of the second dielectric layer 38 is exposed on a surface 361 of the second conductive pattern layer 36.Second conductive pattern layer 36 is electrically connected with the first conductive posts 32 of the second surface 352 exposing the first dielectric layer 35.It is exposed to second conductive pattern layer 36 on the 3rd surface 381 of the second dielectric layer 38, be same plane substantially with the 3rd surface 381 of the second dielectric layer 38.Wherein, the material of the second conductive pattern layer 36 is metal, such as but not limited to copper, and it can be formed in modes such as plating, sputter or evaporations, therefore its thickness is smaller than 1 millimeter（mm）, preferably, the thickness of the second conductive pattern layer 36 is less than 7 microns（μ m）.
Second conductive posts 37 are arranged in the second dielectric layer 38, and are electrically connected with the second conductive pattern layer 36, and the 4th surface 382 of the second dielectric layer 38 is exposed on a surface 371 of the second conductive posts 37.It is exposed to second conductive posts 37 on the 4th surface 382 of the second dielectric layer 38, be same plane substantially with the 4th surface 382 of the second dielectric layer 38.Wherein, the second conductive posts 37 can be formed in modes such as plating, sputter or evaporations, and its material is metal, such as but not limited to copper.
In addition, identical with first embodiment, have one first apart from D11 between the first surface 351 of electronic building brick 34 and the first dielectric layer 35, and there is between the 4th surface 382 of electronic building brick 34 and the second dielectric layer 38 a second distance D12, in the present embodiment, first is different from second distance D12 apart from D11.In other words, it is embedded into formula encapsulating structure 3 by laterally seeing as an asymmetric construction, also therefore the distance between the electric connection pad 341 of electronic building brick 34 and first conductive pattern layer 31 are shorter, and can shorten electronic transmission path, and then can increase its electrical property efficiency.
Refer to shown in Fig. 5, it is a flow chart of the manufacture method being embedded into formula encapsulating structure 2 of first embodiment of the invention, and it includes step S01 to step S09.Hereinafter collocation Fig. 6 A to Fig. 6 I is to illustrate to be embedded into the manufacture method of formula encapsulating structure 2.
Step S01, as shown in Figure 6A, forms one first conductive pattern layer 21 on a support plate 20.Wherein, support plate 20 is a metal support plate, such as but not limited to rustless steel copper facing.First conductive pattern layer 21 can apply the technology such as plating, sputter, evaporation or collocation micro image etching procedure to be formed on support plate 20.
Step S02, as shown in Figure 6B, forms one first conductive posts 22 in the first conductive pattern layer 21.Wherein, the first conductive posts 22 are not completely covered the first conductive pattern layer 21, and that is, part the first conductive pattern layer 21 is exposed.First conductive posts 22 can apply the technology such as plating, sputter, evaporation or collocation micro image etching procedure to be formed in the first conductive pattern layer 21.
Step S03, as shown in Figure 6 C, forms a conducting binding layer 23 in the first conductive pattern layer 21 exposed.Conducting binding layer 23 is such as, but not limited to tin cream, stannum ball or golden projection etc. for the material being conductively connected.As for tin cream, it is for example to print, the mode such as point tin cream or spray tin cream is formed in the first conductive pattern layer 21.
Step S04, as shown in Figure 6 D, an electronic building brick 24 is connected with conducting binding layer 23.Its available back welding process is so that the electric connection pad 241 of electronic building brick 24 is electrically connected with by conducting binding layer 23 with the first conductive pattern layer 21.
Step S05, as illustrated in fig. 6e, forms the first dielectric layer 25 of an overlay electronic assembly 24, the first conductive posts 22 and the first conductive pattern layer 21, and the polished surface 221 exposing the first conductive posts 22.
Step S06, as fig 6 f illustrates, forms one second conductive pattern layer 26 on the first dielectric layer 25 and the first conductive posts 22.Second conductive pattern layer 26 can apply the technology such as plating, sputter, evaporation or collocation micro image etching procedure to be formed on the first dielectric layer 25 and the first conductive posts 22.
Step S07, as shown in Figure 6 G, forms one second conductive posts 27 in the second conductive pattern layer 26.Second conductive posts 27 can apply the technology such as plating, sputter, evaporation or collocation micro image etching procedure to be formed in the second conductive pattern layer 26.
Step S08, as shown in figure 6h, forms second dielectric layer 28 covering the first dielectric layer 25, the second conductive pattern layer 26 and the second conductive posts 27, and exposes a surface 271 of the second conductive posts 27 after ground processing procedure.
Step S09, shown in collocation Fig. 6 H and Fig. 6 I, after removing support plate 20 and making 180 degree upset, is embedded into formula encapsulating structure 2 to form one.Wherein, support plate 20 can such as but not limited to apply etch process（Etching process）, peel off processing procedure（Debonding process）Or grinding processing procedure removes it.
Refer to shown in Fig. 7, it is a flow chart of the manufacture method being embedded into formula encapsulating structure 3 of second embodiment of the invention, and it includes step S11 to step S19.Hereinafter collocation Fig. 8 A to Fig. 8 I is to illustrate to be embedded into the manufacture method of formula encapsulating structure 3.
Step S11, as shown in Figure 8 A, forms one first conductive pattern layer 31 on a support plate 30.Wherein, support plate 30 is a metal support plate, such as but not limited to rustless steel copper facing.First conductive pattern layer 31 can apply the technology such as plating, sputter, evaporation or collocation micro image etching procedure to be formed on support plate 30.
Step S12, as shown in Figure 8 B, forms the fixed layer 33 of covering part first conductive pattern layer 31.Fixed layer 33 such as but not limited to combines glue or combination film, and it can apply coating process or dispensing processing procedure to be formed in the first conductive pattern layer 31.
Step S13, as shown in Figure 8 C, an electronic building brick 34 is arranged on fixed layer 33, and exposes at least one electric connection pad 341.In the present embodiment, electronic building brick 34 is fixed on support plate 30 by the stickiness of fixed layer 33.
Step S14, as in fig. 8d, forms one first conductive posts 32 in the first conductive pattern layer 31 exposed and electric connection pad 341.Wherein, the first conductive posts 32 can apply the technology such as plating, sputter, evaporation or collocation micro image etching procedure to be formed on the first conductive pattern layer 31 and electric connection pad 341.
Step S15, as illustrated in fig. 8e, forms the first dielectric layer 35 of an overlay electronic assembly 34, the first conductive posts 32 and the first conductive pattern layer 31, and the polished surface 321 exposing the first conductive posts 32.
Step S16, as shown in Figure 8 F, forms one second conductive pattern layer 36 on the first dielectric layer 35 and the first conductive posts 32.Second conductive pattern layer 36 can apply the technology such as plating, sputter, evaporation or collocation micro image etching procedure to be formed on the first dielectric layer 35 and the first conductive posts 32.
Step S17, as shown in fig. 8g, forms one second conductive posts 37 in the second conductive pattern layer 36.Second conductive posts 37 can apply the technology such as plating, sputter, evaporation or collocation micro image etching procedure to be formed in the second conductive pattern layer 36.
Step S18, as illustrated in figure 8h, forms second dielectric layer 38 covering the first dielectric layer 35, the second conductive pattern layer 36 and the second conductive posts 37, and the polished surface 371 exposing the second conductive posts 37.
Step S19, as shown in Fig. 8 H and Fig. 8 I, removes support plate 30 and makees 180 degree upset, be embedded into formula encapsulating structure 3 to form one.Wherein, support plate 30 can such as but not limited to apply etch process, stripping processing procedure or grinding processing procedure to remove it.
In sum, one kind according to the present invention is embedded into formula encapsulating structure and its processing procedure, mode using stacking manufactures, and it is without using substrate it is not necessary to make electronic building brick be embedded in substrate to produce and be embedded into formula encapsulating structure using time-consuming operations such as laser etchings.Due to having given up the operation of laser etching, the therefore selection of electronic building brick will not be limited to the thickness of ball bottom metal layer and more elastic.Further, since the present invention be embedded into that formula encapsulating structure seen by side is asymmetric, that is, the distance between electronic building brick and first conductive pattern layer are shorter, and can shorten electronic transmission path, and then can increase its electrical property efficiency.
The present invention meets the application condition of patent of invention, therefore proposes patent application in accordance with the law.But the foregoing is only presently preferred embodiments of the present invention it is impossible to the scope of patent protection of the application is limited with this.Equivalent modification or change that those skilled in the art are made according to the technical scheme of the application, all should belong to the scope of patent protection of the present invention.
Claims (14)
1. a kind of manufacture method being embedded into formula encapsulating structure it is characterised in that：It includes：
One first conductive pattern layer is formed on a support plate；
Form one first conductive posts in this first conductive pattern layer, and this first conductive pattern layer of exposed portion；
Form a conducting binding layer in this first conductive pattern layer exposed；
One electronic building brick is connected with this conducting binding layer；
Form first dielectric layer covering this electronic building brick, this first conductive posts and this first conductive pattern layer, and expose a surface of this first conductive posts；
One second conductive pattern layer is formed on this first dielectric layer and this first conductive posts；
One second conductive posts are formed on this second conductive pattern layer；
Form second dielectric layer covering this first dielectric layer, this second conductive pattern layer and this second conductive posts, and expose a surface of this second conductive posts；And
Remove this support plate.
2. be embedded into the manufacture method of formula encapsulating structure as claimed in claim 1 it is characterised in that：This first conductive pattern layer, this first conductive posts, this second conductive pattern layer and this second conductive posts are to electroplate, sputter, evaporation or photolithography techniques are formed.
3. be embedded into the manufacture method of formula encapsulating structure as claimed in claim 1 it is characterised in that：This first conductive pattern layer and this at least one of thickness of the second conductive pattern layer are less than 7 microns.
4. be embedded into the manufacture method of formula encapsulating structure as claimed in claim 1 it is characterised in that：This support plate is a metal support plate.
5. a kind of manufacture method being embedded into formula encapsulating structure it is characterised in that：Including：
One first conductive pattern layer is formed on a support plate；
Form the fixed layer of covering part first conductive pattern layer；
One electronic building brick is arranged on this fixed layer, and exposes at least one electric connection pad；
One first conductive posts are formed on this first conductive pattern layer exposed and this electric connection pad；
Form first dielectric layer covering this electronic building brick, this first conductive posts and this first conductive pattern layer, and expose a surface of this first conductive posts；
One second conductive pattern layer is formed on this first dielectric layer and this first conductive posts；
One second conductive posts are formed on this second conductive pattern layer；
Form second dielectric layer covering this first dielectric layer, this second conductive pattern layer and this second conductive posts, and expose a surface of this second conductive posts；And
Remove this support plate.
6. be embedded into the manufacture method of formula encapsulating structure as claimed in claim 5 it is characterised in that：This first conductive pattern layer, this first conductive posts, this second conductive pattern layer and this second conductive posts are to electroplate, sputter, evaporation or photolithography techniques are formed.
7. be embedded into the manufacture method of formula encapsulating structure as claimed in claim 5 it is characterised in that：This first conductive pattern layer and this at least one of thickness of the second conductive pattern layer are less than 7 microns.
8. be embedded into the manufacture method of formula encapsulating structure as claimed in claim 5 it is characterised in that：This support plate is a metal support plate.
9. one kind be embedded into formula encapsulating structure it is characterised in that：Including：
One first dielectric layer, has a relative first surface and a second surface；
One first conductive pattern layer, is arranged in this first dielectric layer, and this first surface of this first dielectric layer is exposed on a surface of this first conductive pattern layer；
One first conductive posts, are arranged in this first dielectric layer, and are electrically connected with this first conductive pattern layer, and this second surface of this first dielectric layer is exposed on a surface of this first conductive posts；
One electronic building brick, is arranged in this first dielectric layer；
One second dielectric layer, has one the 3rd relative surface and one the 4th surface；
One second conductive pattern layer, is arranged in this second dielectric layer, and a surface of this second conductive pattern layer is exposed the 3rd surface of this second dielectric layer and is electrically connected with this first conductive posts exposing this second surface；And
One second conductive posts, are arranged in this second dielectric layer, and are electrically connected with this second conductive pattern layer, and the 4th surface of this second dielectric layer is exposed on a surface of this second conductive posts.
10. be embedded into formula encapsulating structure as claimed in claim 9 it is characterised in that：This electronic building brick has at least one electric connection pad, and this electric connection pad is electrically connected with this first conductive pattern layer of part by a conducting binding layer.
11. be embedded into formula encapsulating structure as claimed in claim 9 it is characterised in that：This electronic building brick has at least one electric connection pad, and this electric connection pad is electrically connected with this first conductive posts of part.
12. be embedded into formula encapsulating structure as claimed in claim 9 it is characterised in that：This electronic building brick is linked with this first conductive pattern layer of part by a fixed layer.
13. be embedded into formula encapsulating structure as claimed in claim 9 it is characterised in that：This first conductive pattern layer and this at least one of thickness of the second conductive pattern layer are less than 7 microns.
14. be embedded into formula encapsulating structure as claimed in claim 9 it is characterised in that：There is between this first surface of this electronic building brick and this first dielectric layer one first distance, between this electronic building brick and the 4th surface of this second dielectric layer, there is a second distance, this first distance is different from this second distance.
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