CN107946285B - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

Info

Publication number
CN107946285B
CN107946285B CN201610938441.5A CN201610938441A CN107946285B CN 107946285 B CN107946285 B CN 107946285B CN 201610938441 A CN201610938441 A CN 201610938441A CN 107946285 B CN107946285 B CN 107946285B
Authority
CN
China
Prior art keywords
stopper
layer
electronic
electronic package
package according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610938441.5A
Other languages
Chinese (zh)
Other versions
CN107946285A (en
Inventor
赖昶存
江政嘉
王隆源
王愉博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN107946285A publication Critical patent/CN107946285A/en
Application granted granted Critical
Publication of CN107946285B publication Critical patent/CN107946285B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

An electronic package and its preparing process, wherein the preparing process comprises arranging electronic elements and stoppers on a carrying structure, forming a coating layer on the carrying structure to coat the electronic elements and stoppers, exposing the stoppers to the coating layer, removing the stoppers to form recesses on the coating layer, forming metal layers on the coating layer and in the recesses, and removing the stoppers to form the metal layers in the recesses to form electromagnetic shielding compartments.

Description

Electronic package and manufacturing method thereof
Technical Field
The present invention relates to a packaging technology, and more particularly, to an electronic package with electromagnetic shielding and a method for fabricating the same.
Background
With the development of semiconductor technology, semiconductor products have been developed into different package product types, and in order to improve electrical quality, various semiconductor products have a shielding function to prevent electromagnetic interference (EMI).
Fig. 1A to 1C are schematic cross-sectional views illustrating a manufacturing method of a semiconductor package 1 with a shielding function.
As shown in fig. 1A, a plurality of semiconductor devices 11 and a metal plate 12 are disposed on a carrier 10, the semiconductor devices 11 are electrically connected to the carrier 10, and the metal plate 12 is located between two adjacent semiconductor devices 11. Next, an encapsulant 14 is formed on the carrier 10 to encapsulate the semiconductor device 11 and the metal plate 12.
As shown in fig. 1B, an opening 140 is laser formed in the encapsulant 14 to expose the metal plate 12. In practice, however, when the laser process is performed to form the opening 140, no alignment member or mark is available for the laser alignment, so that the alignment can be performed only by the edge of the supporting member 10 or other auxiliary references.
As shown in fig. 1C, a metal layer 15 is formed on the encapsulant 14 and the side surface of the carrier 10, and the metal layer 15 extends into the opening 140, it is desirable to electrically connect the metal layer 15 to the metal plate 12, so that the metal layer 15 and the metal plate 12 form a shielding structure.
However, when the opening 140 is formed by a laser, the alignment accuracy of the laser is easily damaged by other processes, thereby reducing the accuracy. For example, during the process of forming the encapsulant 14, the metal plate 12 is easily deflected by the flow impact of the adhesive, or the edge of the carrier 10 is affected by the precision of the cutting tool to affect the position of the shape and size after cutting, and thus cause misalignment, as shown in fig. 1B, i.e., the position where the laser is to be fired, i.e., the position of the opening 140, cannot be aligned with the position of the metal plate 12, so that as shown in fig. 1C, the metal layer 15 cannot contact the metal plate 12, so that the two cannot be electrically conducted, thereby easily causing problems such as poor manufacturing or quality control, and leading to many problems of poor products, for example, the semiconductor device 11 is susceptible to external electromagnetic interference (EMI), which may cause the electrical operation of the semiconductor device 11 to malfunction, thereby affecting the electrical performance of the semiconductor package 1.
Therefore, how to overcome the above-mentioned problems of the prior art has become an issue to be solved.
Disclosure of Invention
In order to overcome the disadvantages of the conventional technologies, the present invention provides an electronic package and a method for fabricating the same, so as to avoid the problem of the conventional electromagnetic shielding structure that is not electrically connected.
The electronic package of the present invention includes: a load bearing structure; the electronic element is arranged on the bearing structure; a stopper formed on the bearing structure; and the coating layer is formed on the bearing structure so that the coating layer coats at least partial surfaces of the electronic element and the stopper.
The invention also provides a method for manufacturing the electronic packaging piece, which comprises the following steps: arranging the electronic element and the stopper on a bearing structure; forming a coating layer on the bearing structure to coat the electronic element and at least part of the surface of the stopper; removing the stopper to form a recess on the cladding layer; and forming a metal layer on the cladding layer and in the recess.
In the foregoing method, the covering layer covers the upper surface of the stopper. Also includes removing part of the covering layer to expose the upper surface of the stopper.
In the electronic package and the method for manufacturing the same, the supporting structure is provided with a plurality of electronic components, and the stopper is located between two adjacent electronic components.
In the electronic package and the method for fabricating the same, a portion of the surface of the stopper is exposed out of the covering layer, for example, the upper surface of the stopper is flush with the upper surface of the covering layer, or an opening is formed in the covering layer to expose out of the stopper. Alternatively, the stopper extends through the covering.
In the electronic package and the method for fabricating the same, the stopper is a heat dissipation material.
In view of the above, the electronic package and the method for manufacturing the same of the present invention mainly dispose the stopper at the position where the metal layer is to be formed subsequently, so that the metal layer can be formed on the coating layer and in the recess only by removing the stopper to form the corresponding recess in the coating layer, so that the metal layer effectively forms the electromagnetic shielding compartment, thereby avoiding the problem derived from the fact that the known electromagnetic shielding structure cannot be electrically conducted.
Drawings
Fig. 1A to 1C are schematic cross-sectional views illustrating a manufacturing method of a semiconductor package with a shielding function; and
fig. 2A to 2D are schematic cross-sectional views illustrating an electronic package and a method for fabricating the same according to the present invention; fig. 2B' is another embodiment of fig. 2B.
Description of the symbols
1 semiconductor package
10 bearing part
11 semiconductor element
12 metal plate
14 packaging adhesive
140 open pores
15,25,250 metal layer
2 electronic package
20 load bearing structure
20a first side
20b second side
20c side surface
200 insulating layer
201 line layer
202 ground part
21, 21' electronic component
21a action surface
21b non-active surface
210 conductive bump
210' bonding wire
22 stop
22a exposed surface
24 coating layer
24a first surface
24b,24 b' second surface
24c side surface
240 concave part
26 conductive element
260 under bump metal layer
L cut the path.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the present disclosure, and are not used for limiting the conditions of the present disclosure, which will not be technically significant, and any structural modifications, ratio changes or size adjustments should be made within the scope of the present disclosure without affecting the function and the achievable purpose of the present disclosure. In addition, the terms "upper", "a" and "lower" used in the present specification are for clarity of description only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship therebetween may be made without substantial changes in the technical content.
Fig. 2A to 2D are schematic cross-sectional views illustrating a method for manufacturing the electronic package 2 according to the present invention. In the present embodiment, the electronic package 2 can emit electromagnetic waves, such as a Radio Frequency (RF) module.
As shown in fig. 2A, a carrying structure 20 is provided, which has a first side 20a and a second side 20b opposite to each other, and a plurality of electronic components 21,21 ', 21 ″ and at least one stopper 22 are disposed on the first side 20a of the carrying structure 20, and the stopper 22 is disposed between the electronic components 21, 21'.
In the present embodiment, the carrier structure 20 is a circuit structure with a core layer or a circuit structure without a core layer (core), and includes at least an insulating layer 200 and a circuit layer 201 disposed on the insulating layer 200 and having a grounding portion 202, such as a fan-out (fan out) redistribution layer (RD L), the circuit layer 201 is made of copper, and the insulating layer 200 is made of a dielectric material, such as Polyoxadiazole (PBO), Polyimide (PI), Prepreg (PP), etc. it should be understood that the carrier structure 20 may also be a carrier of other carrier chips, such as a wafer (wafer), or other carrier boards with metal wires (routing), and is not limited thereto.
In addition, the electronic component 21, 21', 21 ″ is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, or an inductor, or a combination thereof. In particular, the electronic component 21, 21' is a radio frequency chip (e.g., a bluetooth chip or a Wi-Fi chip), but may also be other electronic components 21 ″ that do not affect electromagnetic wave interference. For example, the electronic component 21 has an active surface 21a and an inactive surface 21b opposite to each other, the active surface 21a has a plurality of electrode pads (not shown), which are disposed on the circuit layer 201 in a flip-chip manner by a plurality of conductive bumps 210 such as solder material and electrically connected to the circuit layer 201; alternatively, the electronic device 21 'can be electrically connected to the circuit layer 201 by a plurality of bonding wires 210' by wire bonding. However, the manner of electrically connecting the electronic component to the supporting structure is not limited to the above.
The stopper 22 is an insulating plate made of a polymer material, such as positive or negative photosensitive resist, a hot-melt polymer material, a heat loss material, or a corrosion-prone material, and is vertically disposed on the circuit layer 201 and around each of the electronic components 21, 21'; if the stopper 22 is a heat-dissipating material, it may be paraffin, polystyrene (polystyrene) or other heat-dissipating material. It should be understood that the shape of the stopper 22 is not limited, such as irregular or random geometric shape.
As shown in fig. 2B, a covering layer 24 is formed on the first side 20a of the supporting structure 20, so that the covering layer 24 covers the electronic components 21,21 ', 21 ″ and the stoppers 22 to form the electronic package 2 of the present invention, and a portion of the surface of the stopper 22 is exposed out of the covering layer 24, but each of the electronic components 21, 21', 21 ″ is not exposed out of the covering layer 24. Next, a plurality of conductive elements 26, such as solder balls, are formed on the circuit layer 201 on the second side 20b of the carrying structure 20 for subsequent connection of an electronic device (not shown), such as another package, a circuit board or a chip.
In the present embodiment, the cladding layer 24 is an insulating material, such as Polyimide (PI), dry film (dry film), epoxy resin (epoxy), or molding compound (molding compound), and may be formed on the first side 20a of the supporting structure 20 by pressing (laminating) or molding (molding). For example, if the stopper 22 is a heat-dissipating material, the coating 24 can be a molding encapsulant that cooperates with the heat-dissipating material and adjusts its operating temperature; alternatively, the cladding 24 may be a non-heat-affected material.
In addition, the cladding layer 24 has a first surface 24a and a second surface 24b opposite to each other, so that the first surface 24a of the cladding layer 24 is bonded to the first side 20a of the load-bearing structure 20.
Furthermore, an Under Bump Metal (UBM) 260 may be formed on the outermost circuit layer 201 on the second side 20b of the carrier structure 20 to facilitate bonding the conductive element 26.
In addition, the exposed surface 22a of the stopper 22 is flush with the second surface 24b of the covering layer 24, so that the end of the stopper 22 is exposed out of the second surface 24b of the covering layer 24. Specifically, when the covering layer 24 is formed, the upper surface (exposed surface 22a) of the stopper 22 can be directly flush with the upper surface (second surface 24b) of the covering layer 24; alternatively, as shown in fig. 2B ', the second surface 24B ' of the covering layer 24 may be covered with the stopper 22, and then a portion of the material of the second surface 24B ' of the covering layer 24 is removed (optionally, a portion of the material of the stopper 22 is removed) by, for example, grinding or laser, so that a portion of the surface of the stopper 22 is exposed out of the second surface 24B of the covering layer 24 in a flush manner or an opening manner.
As shown in fig. 2C, the stopper 22 is removed to form at least one plate-like recess 240 on the second surface 24b of the cladding layer 24, and the circuit layer 201 (or the grounding portion 202) is exposed to the recess 240.
In the present embodiment, the stopper 22 is removed by UV light irradiation, heating, clamping, stripping or chemical solvent, etc. to form the recess 240 penetrating the cladding layer 24.
In addition, if the cladding layer 24 and the concave portion 240 thereof are manufactured by using a thermal lost mold method, subsequent drilling is not required, so that the machining cost can be reduced, the mold extraction is convenient, the concave portion 240 of the cladding layer 24 is free from defects (for example, the wall surface of the concave portion 240 is free from burrs), the forming position and the shape of the concave portion 240 are not limited by the factors of molding, mold splitting, mold extraction and the like, and the concave portion 240 with any size can be completed according to the melting capability of the stopper 22.
As shown in fig. 2D, a metal layer 25 is formed on the second surface 24b and the side surface 24c of the cladding layer 24 and the side surface 20c of the supporting structure 20 by, for example, electroplating, and a metal layer 250 is also formed in the recess 240 (i.e., the metal layer 25,250 is integrally formed), so that the metal layer 250 contacts the circuit layer 201 (or the grounding portion 202), so that the metal layer 25,250 is electrically connected to the circuit layer 201 (or the grounding portion 202) to serve as an electromagnetic shielding compartment (EMI partition) to form another electronic package structure.
In the present embodiment, the metal layer 25,250 is made of gold, silver, copper (Cu), nickel (Ni), iron (Fe), aluminum (Al), stainless steel (Sus), or the like.
Alternatively, the metal layer 25,250 may be formed by coating (coating), sputtering (sputtering), electroless plating, or evaporation.
In other embodiments, the metal layer 25 is electrically connected to the circuit layer 201 (or the grounding portion 202) of the supporting structure 20 exposed from the side surface 20 c.
Therefore, the manufacturing method of the electronic package 2 of the present invention is to dispose the stopper 22 on the position of the metal layer 250, and the height of the stopper 22 is equal to the height of the covering layer 24, so that after the covering layer 24 is formed, the stopper 22 is exposed out of the covering layer 24, at this time, only the stopper 22 needs to be removed to form the recess 40 corresponding to the stopper 22 in the covering layer 24, and then the metal layer 25,250 can be formed on the covering layer 24 and in the recess 240, so that the metal layer 25,250 effectively forms an electromagnetic shielding compartment, thereby avoiding the problem derived from knowing that the metal layer 15 cannot be electrically connected to the metal plate 12.
In addition, since the metal layer 25,250 covers the periphery of the electronic components 21,21 ', 21 ″, when the electronic package 2 is in operation, the electronic components 21,21 ', 21 ″ will not be subjected to external electromagnetic interference (EMI), and the metal layer 250 also serves as an electromagnetic wave shield, so that the electronic components 21,21 ' will not be subjected to electromagnetic interference with each other (e.g., signals between a bluetooth chip and a Wi-Fi chip are prevented from interfering with each other), and thus the electrical operation function of the electronic package 2 is normal, and the electrical performance of the electronic package 2 is prevented from being affected.
The present invention also provides an electronic package 2 comprising: a carrying structure 20, at least one electronic component 21, 21', 21 ", a covering layer 24 and a stopper 22.
The electronic components 21, 21', 21 ″ are disposed on the supporting structure 20 and electrically connected to the supporting structure 20.
The flight 22 is formed on the load bearing structure 20.
The coating layer 24 is formed on the supporting structure 20, such that the coating layer 24 coats at least a portion of the surfaces of the electronic components 21, 21', 21 ″ and the stopper 22.
In one embodiment, the supporting structure 20 is provided with a plurality of electronic components 21,21 ', and the concave portion 240 is located between two adjacent electronic components 21, 21'.
In one embodiment, a portion of the surface of the stopper 22 is exposed out of the covering layer 24. For example, the upper surface of the stopper 22 is flush with the upper surface of the covering layer 24; alternatively, the covering layer 24 is formed with an opening that exposes a portion of the surface of the stopper. Alternatively, the stopper 22 extends through the covering 24.
In one embodiment, the stopper 22 is a heat-dissipating material.
In summary, the electronic package and the fabrication method thereof of the present invention effectively form the electromagnetic shielding compartment on the outer surface of the covering layer and in the covering layer by the sequential arrangement and removal of the stoppers, thereby avoiding the problem that the known electromagnetic shielding structure cannot be electrically conducted.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims (14)

1. An electronic package, characterized in that the electronic package comprises:
a load bearing structure;
the electronic element is arranged on the bearing structure;
a stopper which is a heat-dissipating material and is formed on the bearing structure; and
and the coating layer is formed on the bearing structure so that the coating layer coats at least partial surfaces of the electronic element and the stopper.
2. The electronic package according to claim 1, wherein the supporting structure is provided with a plurality of electronic components, and the stopper is located between two adjacent electronic components.
3. The electronic package according to claim 1, wherein a portion of the surface of the stopper is exposed out of the cover layer.
4. The electronic package according to claim 3, wherein the upper surface of the stopper is flush with the upper surface of the cover layer.
5. The electronic package according to claim 3, wherein the cover layer is formed with an opening that exposes a portion of the surface of the stopper.
6. The electronic package according to claim 3, wherein the stopper extends through the cover.
7. A method of fabricating an electronic package, the method comprising:
arranging the electronic element and the stopper on a bearing structure, wherein the stopper is made of a heat dissipation material;
forming a coating layer on the bearing structure to coat the electronic element and at least part of the surface of the stopper;
removing the stopper in a heating manner to form a recess in the cladding layer; and
forming a metal layer on the cladding layer and in the recess.
8. The method for manufacturing an electronic package according to claim 7, wherein a plurality of electronic components are disposed on the supporting structure, and the stopper is located between two adjacent electronic components.
9. The method for manufacturing an electronic package according to claim 7, wherein a portion of the surface of the stopper is exposed out of the covering layer.
10. The method of claim 9, wherein the stopper has an upper surface flush with an upper surface of the cover layer.
11. The method for manufacturing an electronic package according to claim 9, wherein the covering layer is formed with an opening exposing a portion of the surface of the stopper.
12. The method of claim 9, wherein the recess extends through the encapsulant.
13. The method for manufacturing an electronic package according to claim 7, wherein the covering layer covers the upper surface of the stopper.
14. The method of claim 13, further comprising removing a portion of the cover layer to expose the top surface of the stopper.
CN201610938441.5A 2016-10-13 2016-10-25 Electronic package and manufacturing method thereof Active CN107946285B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW105133009A TWI593079B (en) 2016-10-13 2016-10-13 Electronic package and method of manufacture
TW105133009 2016-10-13

Publications (2)

Publication Number Publication Date
CN107946285A CN107946285A (en) 2018-04-20
CN107946285B true CN107946285B (en) 2020-08-07

Family

ID=60048409

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610938441.5A Active CN107946285B (en) 2016-10-13 2016-10-25 Electronic package and manufacturing method thereof

Country Status (2)

Country Link
CN (1) CN107946285B (en)
TW (1) TWI593079B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109712964A (en) * 2018-10-16 2019-05-03 华为机器有限公司 A kind of packaging part and its manufacturing method and electronic equipment
TWI822226B (en) * 2022-08-04 2023-11-11 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5158910A (en) * 1990-08-13 1992-10-27 Motorola Inc. Process for forming a contact structure
TWI474462B (en) * 2011-12-16 2015-02-21 矽品精密工業股份有限公司 Semiconductor package and method of forming same
TWI594390B (en) * 2014-05-16 2017-08-01 矽品精密工業股份有限公司 Semiconductor package and method of manufacture
US9190367B1 (en) * 2014-10-22 2015-11-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process

Also Published As

Publication number Publication date
TW201814877A (en) 2018-04-16
CN107946285A (en) 2018-04-20
TWI593079B (en) 2017-07-21

Similar Documents

Publication Publication Date Title
US10381312B2 (en) Semiconductor package and method of manufacturing the same
US10163860B2 (en) Semiconductor package structure
US20180122789A1 (en) Semiconductor package and method of manufacturing the semiconductor package
US9345143B2 (en) Method of fabricating a wiring board
US8637963B2 (en) Radiation-shielded semiconductor device
US10916829B2 (en) Semiconductor package structure having antenna module
US20170245365A1 (en) Printed wiring board and method for manufacturing the same
US12033868B2 (en) Electronic package and method for fabricating the same
CN105990268B (en) Electronic package structure and method for fabricating the same
US8872329B1 (en) Extended landing pad substrate package structure and method
KR101383002B1 (en) Semiconductor package substrate, Package system using the same and method for manufacturing thereof
US11508673B2 (en) Semiconductor packaging substrate, fabrication method and packaging process thereof
CN107946285B (en) Electronic package and manufacturing method thereof
US20170231093A1 (en) Reduced-dimension via-land structure and method of making the same
CN107958894B (en) Electronic package and manufacturing method thereof
US9761570B1 (en) Electronic component package with multple electronic components
US20210267068A1 (en) Electronic assembly having circuit carrier and manufacturing method thereof
TW202221884A (en) Selective emi shielding using preformed mask
US20240096721A1 (en) Electronic package and manufacturing method thereof
US20210305148A1 (en) Electronic package, supporting structure and fabrication method thereof
US9466553B2 (en) Package structure and method for manufacturing package structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant