CN101924037B - Method for manufacturing coreless capsulation substrates - Google Patents
Method for manufacturing coreless capsulation substrates Download PDFInfo
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- CN101924037B CN101924037B CN 200910150829 CN200910150829A CN101924037B CN 101924037 B CN101924037 B CN 101924037B CN 200910150829 CN200910150829 CN 200910150829 CN 200910150829 A CN200910150829 A CN 200910150829A CN 101924037 B CN101924037 B CN 101924037B
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Abstract
The invention discloses a method for manufacturing coreless capsulation substrates, which comprises the following steps of: respectively stacking a first metal foil layer, a first dielectric layer and a second metal foil layer on both sides of a temporary core layer sequentially, wherein the first metal foil layer is provided with a smooth surface and a coarse surface, the smooth surface faces the temporary core layer, and the coarse surface faces the first dielectric layer; and patterning each second metal foil layer, and stacking at least one structure-spanning structure. The temporary core layer provides support temporarily during layer spanning. After the layer spanning is completed, the temporary core layer is removed to obtain two coreless capsulation substrates.
Description
[technical field]
The invention relates to a kind of manufacturing approach of coreless capsulation substrates, particularly relevant for a kind of manufacturing approach of utilizing the interim core layer of removable formula to increase the coreless capsulation substrates of layer program.
[background technology]
Now; The semiconductor packages industry develops the packaging structure that various different types gradually in order to satisfy the demand of various high-density packages, and wherein common packaging structure with substrate (substrate) comprises ball grid array packaging structure (ball grid array; BGA), pin array packaging structure (pin grid array; PGA), the crosspoint array packaging structure (land grid array, chip encapsulation construction LGA) or on the substrate (board onchip, BOC) etc.In above-mentioned packaging structure, a upper surface of said substrate carries at least one chip, and several connection pads of chip is electrically connected to several weld pads of the upper surface of said substrate through routing (wire bonding) or projection (bumping) program.Simultaneously, a lower surface of said substrate also must provide a large amount of weld pads, to weld several outputs.Usually, said substrate is a multilayer circuit board, and it is except providing the surface circuit layer forming the required weld pad on upper and lower surface, its inside also have at least one in circuit layer and several vias, with the annexation of the weld pad of rearranging upper and lower surface.Therefore, how to make base plate for packaging, also be an important key technology of encapsulation industry with multilayer circuit.
For example; Please with reference to shown in Figure 1; It discloses a kind of structure of existing base plate for packaging 10; Wherein said base plate for packaging 10 is to be the center with a core layer (core layer) 11, and outwards forms one first circuit layer 12, one first dielectric layer 13, a second circuit layer 14, one second dielectric layer 15, a surface circuit layer 16 and a welding resisting layer 17 respectively in regular turn in the both sides of said core layer 11 through Layer increasing method (build-up).Moreover during increasing layer, said core layer 11 possibly form several electroplating ventilating holes (plating throughhole) 111 in addition and run through therebetween, to electrically connect said first circuit layer 12 of both sides.Said first dielectric layer 13 possibly form several vias (conductive via) 131 to be run through therebetween, to electrically connect said first and second circuit layer 12,14.Said second dielectric layer 15 also can form several vias 151 to be run through therebetween, to electrically connect said second circuit layer 14 and surface circuit layer 16.At last, said welding resisting layer 16 forms several openings 161, with the said surface circuit layer 16 of an exposed part, so that several weld pads (being figure number 16 positions) to be provided, so that structure of electric connection (not illustrating) such as bond line, projection or tin balls.
Above-mentioned existing base plate for packaging 10 is widely applied in present manufacturing processes of semiconductor package.Yet,, therefore be necessary further to manage to reduce the integral thickness of said base plate for packaging 10 in order to meet the miniaturization demand of semiconductor packages.Yet; Said base plate for packaging 10 inevitably must use the said core layer 11 with adequate thickness during increasing layer; Guaranteeing that enough support strengths are provided, and prevent because of inhomogeneous (warpage) defectives such as warpage that take place of thermal stress (thermal stress).But, use said core layer 11 can take too much thickness space also, cause being unfavorable for reducing the integral thickness of said base plate for packaging 10.On the other hand, when integral thickness is constant, also be difficult to saved thickness space is used for increasing total number of plies of circuit layer, therefore use said core layer 11 also to be unfavorable for improving circuit level through reducing the thickness of said core layer 11.
Die, be necessary to provide a kind of manufacturing approach of base plate for packaging, to solve the existing in prior technology problem.
[summary of the invention]
Main purpose of the present invention is to provide a kind of manufacturing approach of coreless capsulation substrates; It is to utilize interim core layer that enough support strengths are provided during increasing layer; And can after increasing layer, remove interim core layer, and then help reducing substrate thickness and improve circuit level.
Secondary objective of the present invention is to provide a kind of manufacturing approach of coreless capsulation substrates; It is to utilize interim core layer to increase layer; Manufacturing simultaneously two groups of coreless capsulation substrates, and then improve speed of production, reduce manufacturing cost and guarantee to increase a layer yield in its both sides.
Another object of the present invention is to provide a kind of manufacturing approach of coreless capsulation substrates; It is to utilize interim core layer to increase layer; The surface of interim core layer has the metal foil layer that can remove; Can directly migrate as the surface circuit layer of coreless capsulation substrates, and then simplify and to increase a layer program, improve and increase layer efficient and the reduction cost of getting the raw materials ready.
For reaching above-mentioned purpose, the present invention provides a kind of manufacturing approach of coreless capsulation substrates, and it comprises: an interim core layer is provided; Two sides in said interim core layer are piled up one first metal foil layer, one first dielectric layer and second metal foil layer respectively in regular turn; Wherein said first metal foil layer has a flat surfaces and a rough surface; Said flat surfaces is towards said interim core layer, and said rough surface is towards said first dielectric layer; Each said second metal foil layer is carried out patterning, to form a second circuit layer respectively; Outside each said second circuit layer, pile up at least one layer reinforced structure, said layer reinforced structure comprises one and increases layer dielectric layer and and increase a layer metal foil layer; And, remove said interim core layer, to obtain two coreless capsulation substrates, each said coreless capsulation substrates comprises said first metal foil layer, first dielectric layer, second circuit layer and at least one layer reinforced structure at least.
In one embodiment of this invention, in the step of said interim core layer was provided, said interim core layer was the core layer that contains B stage thermosetting resin.
In one embodiment of this invention, in the step that said interim core layer and said first metal foil layer of pressing are provided, each side of said interim core layer has temporary adhesive surface, to be incorporated into the flat surfaces of said first metal foil layer.
In one embodiment of this invention, after the step of piling up said first metal foil layer, first dielectric layer and second metal foil layer, carry out heat treated, with the surperficial viscosity of the temporary adhesive of the said interim core layer of permanent removal.
In one embodiment of this invention; In the step that said interim core layer and said first metal foil layer of pressing are provided; Each side of said interim core layer has a metal supporting layer; Said metal supporting layer has a rough surface and a flat surfaces, and the rough surface of said metal supporting layer is incorporated into the surface of said interim core layer, and the flat surfaces of said metal supporting layer is incorporated into the flat surfaces of said first metal foil layer.
In one embodiment of this invention, the thickness of the metal supporting layer of said interim core layer is greater than the thickness of said first metal foil layer.
In one embodiment of this invention; After piling up the step of said layer reinforced structure and before removing the step of said interim core layer; In addition to said layer reinforced structure increase layer dielectric layer and increase that a layer metal foil layer holed, filling perforation and patterning, increase a layer circuit layer to form several vias and.
In one embodiment of this invention, after obtaining the step of said coreless capsulation substrates, in addition to first metal foil layer and first dielectric layer of said coreless capsulation substrates hole, filling perforation and patterning, to form one first circuit layer and several vias.
In one embodiment of this invention, after the step that forms said first circuit layer, on said first circuit layer, form a welding resisting layer (solder mask); And said welding resisting layer carried out patterning; To form several openings, said first circuit layer of an exposed part is to provide several weld pads.
In one embodiment of this invention, after obtaining the step of said coreless capsulation substrates, in addition to said layer reinforced structure increase layer dielectric layer and increase that a layer metal foil layer holed, filling perforation and patterning, increase a layer circuit layer to form several vias and.
In one embodiment of this invention, after forming the said step that increases layer circuit layer, form a welding resisting layer on layer circuit layer said increasing; And said welding resisting layer carried out patterning; To form several openings, the said layer circuit layer that increase of an exposed part is to provide several weld pads.
In one embodiment of this invention, after the step that forms said welding resisting layer and weld pad, form one on the surface of said weld pad and help layer.
In one embodiment of this invention; Said help layer be selected from electroless nickel layer, electrogilding layer, electroless nickel platingization gold layer (electroless Ni/Au), immersion silver (immersion silver), immersion tin (immersiontin) or organic protective film (organic solderability preservatives, OSP).
In one embodiment of this invention, said first metal foil layer, second metal foil layer and the thickness that increases layer metal foil layer respectively essence between 10 to 35 microns.
In one embodiment of this invention, said first dielectric layer and the thickness that increases layer dielectric layer respectively essence between 30 to 55 microns.
[description of drawings]
Fig. 1: the sketch map of existing base plate for packaging.
Fig. 2 A to 2H: the schematic flow sheet of the manufacturing approach of the coreless capsulation substrates of first embodiment of the invention.
Fig. 3: the sketch map of the manufacturing approach of the coreless capsulation substrates of second embodiment of the invention.
[embodiment]
For making above-mentioned purpose of the present invention, characteristic and advantage more obviously understandable, hereinafter is special lifts preferred embodiment of the present invention, and conjunction with figs., elaborates as follows:
Please with reference to shown in Fig. 2 A to 2H, the manufacturing approach of the coreless capsulation substrates of first embodiment of the invention mainly comprises the following step: an interim core layer 20 is provided; Pile up one first metal foil layer 21, one first dielectric layer 22 and second metal foil layer 23 respectively in regular turn in two sides of said interim core layer 20; Wherein said first metal foil layer 21 has a flat surfaces 211 and a rough surface 212; Said flat surfaces 211 is towards said interim core layer 20, and said rough surface 212 is towards said first dielectric layer 22; Each said second metal foil layer 23 is carried out patterning, to form a second circuit layer 230 respectively; Outside each said second circuit layer 230, pile up at least one layer reinforced structure 30, said layer reinforced structure 30 comprises one and increases layer dielectric layer 31 and and increase layer metal foil layer 32; And, remove said interim core layer 20, obtaining two coreless capsulation substrates 200, each said coreless capsulation substrates 200 comprises said first metal foil layer 21, first dielectric layer 22, second circuit layer 230 and at least one layer reinforced structure 30 at least.
Please with reference to shown in Fig. 2 A, the manufacturing approach first step of the coreless capsulation substrates of first embodiment of the invention is: an interim core layer 20 is provided.In this step; Said interim core layer 20 preferably is selected from the core layer that contains B stage thermosetting resin (B-stage thermosetting resin); The core layer that for example contains the B stage epoxy resin; (bismaleimide triazine BT) waits thermosetting resin also possibly to contain bismaleimide three nitrogen resins in addition.The core layer of the above-mentioned B of containing stage thermosetting resin is through packing material preimpregnation such as glass fiber (glass fiber) cloth is half-dried back and made through thermoplastic at the A stage thermosetting resin of raw lacquer (varnish) state.Therefore, each side of said interim core layer 20 all has temporary adhesive surface 201,202, so that the temporary adhesive of a predetermined extent to be provided.In the present embodiment, said interim core layer 20 can be selected from glass fiber fabric base material epoxy resin copper clad laminate, for example FR-4 or FR-5 etc., but be not limited to this.Said interim core layer 20 increases the required enough support strengths of layer program in order to provide, and therefore must possess adequate thickness, but possess under the preceding topic of enough support strengths, and the present invention does not limit the thickness range of said interim core layer 20.
Please refer again to shown in Fig. 2 A, manufacturing approach second step of the coreless capsulation substrates of first embodiment of the invention is: pile up one first metal foil layer 21, one first dielectric layer 22 and second metal foil layer 23 respectively in regular turn in two sides of said interim core layer 20.In this step; Said first metal foil layer 21 and second metal foil layer 23 are to process subsequent use through galvanoplastic (electroplating) or roll off method (rolling) in advance; Wherein said at least first metal foil layer 21 must have a flat surfaces 211 and a rough surface 212; Said flat surfaces 211 is towards said interim core layer 20, and said rough surface 212 is towards said first dielectric layer 22.The effect of above-mentioned stacked arrangement relation specifies other in hereinafter.Moreover said first metal foil layer 21 and second metal foil layer 23 can be drawn materials from metal or alloy such as copper, aluminium, nickel, gold, silver, but are not limited to this.The preferred essence of thickness of said first metal foil layer 21 and second metal foil layer 23 is between 10 to 35 microns.It should be noted that; When selecting glass fiber fabric base material epoxy resin copper clad laminates such as FR-4 or FR-5 for use when said interim core layer 20; The temporary adhesive surface 201,202 of said interim core layer 20 each side is stained with flat surfaces metal foil layer inwardly in advance; It can be directly in order to as said first metal foil layer 21, thereby help reducing the cost or simplify stacking procedure of getting the raw materials ready.Said first dielectric layer, 22 essence comprise the insulating material such as B stage thermosetting resin that possess temporary adhesive, and for example the epoxy resin in B stage or bismaleimide three nitrogen resins (BT) etc. in case of necessity, also can add packing materials such as glass fabric.The preferred essence of the thickness of said first dielectric layer 22 is between 30 to 55 microns.When carrying out the present invention's second step, can, completion carry out heat treated after piling up, make temporary adhesive surface 201,202 its stickiness of permanent removal of said interim core layer 20.At this moment; Said temporary adhesive surface 201,202 still can temporaryly be incorporated into the flat surfaces 211 of said first metal foil layer 21; And the rough surface 212 of said first metal foil layer 21 will permanent bond in said first dielectric layer 22, simultaneously said second metal foil layer 23 also can permanent bond in said first dielectric layer 22.
Please with reference to shown in Fig. 2 B, the manufacturing approach third step of the coreless capsulation substrates of first embodiment of the invention is: each said second metal foil layer 23 is carried out patterning, to form a second circuit layer 230 respectively.In this step, the present invention can carry out patterning to said second metal foil layer 23 through existing coating photoresist, mask exposure and developing liquid developing supervisor, to remove said second metal foil layer 23 of a part, thereby forms said second circuit layer 230.In case of necessity; The present invention also can be before patterning (or afterwards), selects to hole and the program of filling perforation, in said first dielectric layer 22, to form several vias (not illustrating); Said drilling program is optional from laser or machine drilling, and said filling perforation program is to accomplish through plating mode.Only, in the present embodiment, the present invention is after the 5th step, just in said first dielectric layer 22, forms several vias 221 (shown in Fig. 2 G).The formation of above-mentioned via is not in order to restriction the present invention opportunity.
Please with reference to shown in Fig. 2 C, 2D and the 2E, manufacturing approach the 4th step of the coreless capsulation substrates of first embodiment of the invention is: outside each said second circuit layer 230, pile up at least one layer reinforced structure 30,40.In the present embodiment, the present invention is provided with two groups of said layer reinforced structures 30,40, but its quantity is not limited to this, and it also can be provided with one group, more than three groups or three groups.Said layer reinforced structure 30 comprises one and increases layer dielectric layer 31 and and increase layer metal foil layer 32.Said layer dielectric layer 31 essence that increase are same as said first dielectric layer 22, and same essence comprises the insulating material such as B stage thermosetting resin that possess temporary adhesive, and the preferred essence of thickness is between 30 to 55 microns.Said layer metal foil layer 32 essence that increase are same as said second metal foil layer 23, can draw materials from metal or alloy such as copper, aluminium, nickel, gold, silver equally, and the preferred essence of thickness are between 10 to 35 microns.In the present embodiment; Shown in Fig. 2 C, the present invention piles up said layer reinforced structure 30 earlier outside each said second circuit layer 230, and suitable heat treated; So that the said layer dielectric layer 31 that increase is incorporated into said second circuit layer 230, and makes and saidly increase layer metal foil layer 32 toward the outer side.Then, shown in Fig. 2 D, to said layer reinforced structure 30 increase layer dielectric layer 31 and increase that layer metal foil layer 32 holed, processing such as filling perforation and patterning, increase layer circuit layer 320 to form several vias 311 and one.Moreover; Shown in Fig. 2 E; Way with similar Fig. 2 C; Further pile up another said layer reinforced structure 40 outside layer circuit layer 320 again each said increasing, said layer reinforced structure 40 comprises one and increases layer dielectric layer 41 and and increase layer metal foil layer 42, and its essence is same as and saidly increases layer dielectric layer 31 and increase layer metal foil layer 32.In case of necessity, the present invention also can to said increase layer dielectric layer 41 and increase that layer metal foil layer 42 selected to hole, the program of filling perforation and patterning, to form several vias (not illustrating) and another increases a layer circuit layer (not illustrating).Only; In the present embodiment; In order to make stacked structure have symmetry to prevent inhomogeneous warpage (warpage) defective that causes of thermal stress (thermal stress); The present invention is after the 5th step, just makes saidly to increase layer dielectric layer 41 and increase that layer metal foil layer 42 forms several vias 411 and another increases layer circuit layer 420 (shown in Fig. 2 G).
Please with reference to shown in Fig. 2 F, 2G and the 2H, manufacturing approach the 5th step of the coreless capsulation substrates of first embodiment of the invention is: remove said interim core layer 20, to obtain two coreless capsulation substrates 200.In the present embodiment, its viscosity of permanent removal in the heating process has been piled up at above-mentioned several in the temporary adhesive of said interim core layer 20 surface 201,202.At this moment, the final bond strength on said flat surfaces 211 and temporary adhesive surface 201,202 will be significantly less than the final bond strength of the said rough surface 212 and first dielectric layer 22.Therefore; Shown in Fig. 2 F; The present invention can remove said interim core layer 20 through artificial or simple and easy facility easily; And stay two groups of said coreless capsulation substrates 200, wherein each said coreless capsulation substrates 200 comprises said first metal foil layer 21, first dielectric layer 22, second circuit layer 230 and at least one layer reinforced structure 30,40 at least.In the present embodiment, each said coreless capsulation substrates 200 comprises two groups of said layer reinforced structures 30,40, but is not limited to this.Then; Shown in Fig. 2 G; After removing said interim core layer 20, can hole to first metal foil layer 21 and first dielectric layer 22 of each said coreless capsulation substrates 200, filling perforation and patterning, to form one first circuit layer 210 and several vias 221.Simultaneously, to said layer reinforced structure 40 increase layer dielectric layer 41 and increase that layer metal foil layer 42 holed, filling perforation and patterning, increase layer circuit layer 420 to form several vias 411 and one.Subsequently, shown in Fig. 2 H, then can on said first circuit layer 210, form a welding resisting layer (solder mask) 50; And said welding resisting layer 50 carried out patterning; To form several openings 51, said first circuit layer 210 of an exposed part is to provide several weld pads (not indicating).Simultaneously, form another welding resisting layer 50 on layer circuit layer 420 said increasing, and said welding resisting layer 50 is carried out patterning, to form several openings 51, the said layer circuit layer 420 that increase of an exposed part is to provide several weld pads (not indicating).At last; According to product demand; Optionally form one and help layer 60 on the surface of the weld pad of said first circuit layer 210 (or increasing layer circuit layer 420); Said help layer 60 be can be selected from electroless nickel layer, electrogilding layer, electroless nickel platingization gold layer (electroless Ni/Au), immersion silver (immersion silver), immersion tin (immersion tin) or organic protective film (organic solderability preservatives, OSP).
Through above-mentioned first to the 5th step; First embodiment of the invention is that said interim core layer 20 capable of using provides enough support strengths; So that increase a layer program smoothly; And can after increasing layer, remove said interim core layer 20, so the circuit level that helps reducing the integral thickness of said coreless capsulation substrates 200 and improve said coreless capsulation substrates 200.Owing to can manufacture two groups of coreless capsulation substrates 200 simultaneously in the both sides of said interim core layer 20; Therefore not only can improve speed of production relatively and reduce manufacturing cost; Also can increase layer through two side symmetries; Preventing the inhomogeneous warpage defective that is caused of thermal stress really, and then guarantee to increase a layer yield.
Please with reference to shown in Figure 3, the manufacturing approach of the coreless capsulation substrates of second embodiment of the invention is similar in appearance to first embodiment of the invention, but the interim core layer 70 that said second embodiment uses is different from the interim core layer 20 of said first embodiment.In a second embodiment, when preparing said interim core layer 70 in advance, each side of said interim core layer 70 has had a metal supporting layer 71 and one first metal foil layer 72.For example; Said interim core layer 70 can be selected glass fiber fabric base material epoxy resin copper clad laminates such as special FR-4 or FR-5 for use; That is the surface of said interim core layer 70 each side is stained with the said metal supporting layer 71 and first metal foil layer 72 in advance in regular turn, thereby helps reducing the cost or simplify stacking procedure of getting the raw materials ready.More in detail, said metal supporting layer 71 has a rough surface 711 and a flat surfaces 712, and said first metal foil layer 72 has a flat surfaces 721 and a rough surface 722 simultaneously.In the present invention, the rough surface 711 of said metal supporting layer 71 is incorporated into said interim core layer 70, and wherein said interim core layer 70 can have temporary adhesive surface (not indicating), but also can not have the temporary adhesive surface.Moreover the flat surfaces 712 of said metal supporting layer 71 is incorporated into the flat surfaces 721 of said first metal foil layer 72, and 722 of the rough surfaces of said first metal foil layer 72 combine one first interlayer electricity, 73 and 1 second metal foil layer 74 in order to pile up in regular turn.Therefore, said metal supporting layer 71 can be greater than the final bond strength of the said metal supporting layer 71 and first metal foil layer 72 with the final bond strength of interim core layer 70.When second embodiment accomplishes when increasing layer and desiring to remove said interim core layer 70; Said interim core layer 70 will be removed together with said metal supporting layer 71, only constitute two groups of coreless capsulation substrates (not illustrating) by said first metal foil layer 72, first interlayer electricity 73, second metal foil layer 74 and at least one layer reinforced structure (not illustrating).
It should be noted that since the metal supporting layer 71 of said interim core layer 70 only in order to the effect of providing support, so the present invention do not limit the thickness of said metal supporting layer 71, but its thickness is preferably greater than the thickness of said first metal foil layer 72.The preferred essence of the thickness of said first metal foil layer 72 is between 10 to 35 microns.Except the structure difference of said interim core layer 70, the manufacturing approach of the coreless capsulation substrates of said second embodiment is that essence is same as said first embodiment, so the present invention gives each step that specifies said second embodiment no longer in addition.
As stated; When increasing layer, use said core layer 11 compared to the existing base plate for packaging 10 of Fig. 1; Cause being unfavorable for reducing shortcomings such as integral thickness or raising circuit level; Fig. 2 A to 2H and the present invention of 3 utilize said interim core layer 20 that enough support strengths are provided during increasing layer, and can after increasing layer, remove said interim core layer 20, thereby the circuit level that helps reducing the integral thickness of said coreless capsulation substrates 200 and improve said coreless capsulation substrates 200.Moreover; Owing to can manufacture two groups of coreless capsulation substrates 200 simultaneously in the both sides of said interim core layer 20; Therefore not only can improve speed of production relatively and reduce manufacturing cost; Also can increase layer, preventing the inhomogeneous warpage defective that is caused of thermal stress really, and then guarantee to increase a layer yield through two side symmetries.In addition; As shown in Figure 3; Therefore when the surface of said interim core layer 70 had first metal foil layer 72 that can remove, said first metal foil layer 72 can directly be migrated as the surface circuit layer of follow-up coreless capsulation substrates, can simplify to increase a layer program, raising and increase layer efficient and the reduction cost of getting the raw materials ready.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is merely the example of embodiment of the present invention.Must be pointed out that disclosed embodiment does not limit scope of the present invention.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope includes in scope of the present invention.
Claims (12)
1. the manufacturing approach of a coreless capsulation substrates, it is characterized in that: said manufacturing approach comprises:
One interim core layer is provided; Each side of said interim core layer has a metal supporting layer and one first metal foil layer; Said metal supporting layer has a rough surface and a flat surfaces; The rough surface of said metal supporting layer is incorporated into the surface of said interim core layer, and the flat surfaces of said metal supporting layer is incorporated into a flat surfaces of said first metal foil layer;
Two sides in said interim core layer are piled up one first dielectric layer and second metal foil layer respectively in regular turn, and a rough surface of wherein said first metal foil layer is towards said first dielectric layer;
Each said second metal foil layer is carried out patterning, to form a second circuit layer respectively;
Outside each said second circuit layer, pile up at least one layer reinforced structure, said layer reinforced structure comprises one and increases layer dielectric layer and and increase a layer metal foil layer; And
Remove said interim core layer and metal supporting layer, to obtain two coreless capsulation substrates, each said coreless capsulation substrates comprises said first metal foil layer, first dielectric layer, second circuit layer and at least one layer reinforced structure at least.
2. the manufacturing approach of coreless capsulation substrates as claimed in claim 1, it is characterized in that: in the step of said interim core layer was provided, said interim core layer was the core layer that contains B stage thermosetting resin.
3. the manufacturing approach of coreless capsulation substrates as claimed in claim 1, it is characterized in that: the thickness of the metal supporting layer of said interim core layer is greater than the thickness of said first metal foil layer.
4. the manufacturing approach of coreless capsulation substrates as claimed in claim 1; It is characterized in that: after piling up the step of said layer reinforced structure and before removing the step of said interim core layer; In addition to said layer reinforced structure increase layer dielectric layer and increase that a layer metal foil layer holed, filling perforation and patterning, increase a layer circuit layer to form several vias and.
5. the manufacturing approach of coreless capsulation substrates as claimed in claim 1; It is characterized in that: after obtaining the step of said coreless capsulation substrates; In addition to first metal foil layer and first dielectric layer of said coreless capsulation substrates hole, filling perforation and patterning, to form one first circuit layer and several vias.
6. the manufacturing approach of coreless capsulation substrates as claimed in claim 5; It is characterized in that: after the step that forms said first circuit layer; On said first circuit layer, form a welding resisting layer, and said welding resisting layer is carried out patterning, to form several openings; Said first circuit layer of an exposed part is to provide several weld pads.
7. the manufacturing approach of coreless capsulation substrates as claimed in claim 1; It is characterized in that: after obtaining the step of said coreless capsulation substrates; In addition to said layer reinforced structure increase layer dielectric layer and increase that a layer metal foil layer holed, filling perforation and patterning, increase a layer circuit layer to form several vias and.
8. the manufacturing approach of coreless capsulation substrates as claimed in claim 7; It is characterized in that: after forming the said step that increases layer circuit layer; Form a welding resisting layer on layer circuit layer said increasing, and said welding resisting layer is carried out patterning, to form several openings; The said layer circuit layer that increase of an exposed part is to provide several weld pads.
9. like the manufacturing approach of claim 6 or 8 described coreless capsulation substrates, it is characterized in that: after the step that forms said welding resisting layer and weld pad, form one on the surface of said weld pad and help layer.
10. the manufacturing approach of coreless capsulation substrates as claimed in claim 9 is characterized in that: the said layer that helps is selected from electroless nickel layer, electrogilding layer, electroless nickel platingization gold layer, immersion silver, immersion tin or organic protective film.
11. the manufacturing approach of coreless capsulation substrates as claimed in claim 1 is characterized in that: said first metal foil layer, second metal foil layer and the thickness that increases layer metal foil layer are respectively between 10 to 35 microns.
12. the manufacturing approach of coreless capsulation substrates as claimed in claim 1 is characterized in that: said first dielectric layer and the thickness that increases layer dielectric layer are respectively between 30 to 55 microns.
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| TWI436464B (en) * | 2011-01-13 | 2014-05-01 | Advanced Semiconductor Eng | Semiconductor package, substrate, and manufacturing method of substrate |
| CN109637995B (en) * | 2013-09-03 | 2022-11-22 | 日月光半导体制造股份有限公司 | Substrate structure, packaging structure and manufacturing method thereof |
| CN104540339B (en) * | 2014-12-31 | 2017-11-17 | 广州兴森快捷电路科技有限公司 | Without core plate manufacture component, without core plate and centreless board manufacturing method |
| CN104540326A (en) * | 2014-12-31 | 2015-04-22 | 广州兴森快捷电路科技有限公司 | Core-less board manufacturing component and manufacturing method for core-less board |
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| CN1466517A (en) * | 2000-09-22 | 2004-01-07 | �źӵ�·ͭ����ʽ���� | Copper foil for high-density ultrafine wiring board |
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