CN203192781U - A packaging substrate strip structure - Google Patents
A packaging substrate strip structure Download PDFInfo
- Publication number
- CN203192781U CN203192781U CN 201220691033 CN201220691033U CN203192781U CN 203192781 U CN203192781 U CN 203192781U CN 201220691033 CN201220691033 CN 201220691033 CN 201220691033 U CN201220691033 U CN 201220691033U CN 203192781 U CN203192781 U CN 203192781U
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- dielectric layer
- base plate
- stress relief
- packaging bar
- relief hole
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Abstract
The utility model discloses a packaging substrate strip structure. The packaging substrate strip structure comprises a substrate body, multiple substrate units, a cutting area, and multiple stress releasing holes. The substrate body comprises at least one dielectric layer and at least one circuit layer which are arranged in an alternative and overlapped manner. The multiple substrate units are defined and arranged on the substrate body. The cutting area is arranged round the substrate units in order to be connected with any two adjacent substrate units. The multiple stress releasing holes are arranged within the range of the cutting area and pass through at least one dielectric layer.
Description
Technical field
The utility model relates to a kind of base plate for packaging bar structure, particularly relevant for a kind of base plate for packaging bar structure that prevents from encapsulating substrate strip warpage in the manufacturing process.
Background technology
Now, the semiconductor packages industry development goes out the packaging structure of various different types, to satisfy various demands, and encapsulation procedure mainly is the implementation step that comprises packing colloid, namely after arranging a plurality of chips of arrangement or electronic component on the substrate, with packing colloid it is coated again, with the destruction that provides chip or electronic component to avoid to be subjected to external force, water, moisture, chemicals and corrosion etc., and increase its mechanical strength.
Generally speaking, can use a large-sized substrate strip (substrate strip) that a plurality of chips setting area is provided in the processing procedure, can be called base board unit, chip or electronic component total arrange be arranged on the substrate strip after, packing colloid is set in the substrate strip surface again coats and seal up chip or electronic component, then carry out the step of cutting substrate bar again.Above-mentioned packing colloid is thermosets normally, and it can be injected by mould, chip or electronic component is sealed, at last by the sclerosis of baking (post molding cure) manufacturing process.
Yet, along with slim Development of Packaging Technology, thin base bar area increases and the thickness attenuation day by day, during making in substrate strip, carry out insulating barrier silicon dioxide, copper, gold, when metal level such as nickel and resin bed multilayer overlap, because thermal coefficient of expansion (coefficient of thermal expansion, CTE) and the different material of shape when making up mutually, tend to cause dielectric layer in pressing or baking-curing process, the stacking structure that makes substrate strip has in various degree swell increment or amount of contraction because of dielectric layer and circuit layer, very easily produce residual stress or thermal stress, and the phenomenon that during substrate strip is made, causes substrate strip warpage (warpage) and then peel off or be out of shape, the left and right sides of for example causing substrate strip is warpage downwards.The substrate strip warpage can influence the carrying out of follow-up packaging technology, and wherein the excessive chip that then can make of substrate strip warpage is difficult for smooth being fixed on the base board unit, or causes the profile after the sealing not to be inconsistent standard criterion, thereby influences the yields of packaging technology.
So, be necessary to provide a kind of packaging structure, to solve the existing in prior technology problem.
The utility model content
In view of this, the utility model provides a kind of base plate for packaging bar structure, to solve the substrate strip warpage issues in the existing in prior technology base plate for packaging bar manufacturing process.
Main purpose of the present utility model is to provide a kind of base plate for packaging bar structure, and it can lower base plate for packaging bar warpage degree, can alleviate the weight of base plate for packaging bar simultaneously.
For reaching aforementioned purpose of the present utility model, the utility model one embodiment provides a kind of base plate for packaging bar structure, and wherein said base plate for packaging bar structure comprises: a substrate body, a plurality of base board unit, a cutting area and a plurality of stress relief hole.Described substrate body comprises at least one dielectric layer and at least one circuit layer, and described dielectric layer and circuit layer alternately stack arrangement.Described a plurality of base board unit defines and is arranged on the described substrate body.Described cutting position is around described base board unit, to connect wantonly two adjacent described base board units.Described a plurality of stress relief hole is arranged in the scope of described cutting area, and runs through at least one described dielectric layer.
Compared with prior art, base plate for packaging bar structure of the present utility model, because in each described dielectric layer, having a plurality of stress relief holes, when thermal stress produces, can cause the phenomenon pullled by thermal stress behind the expanded by heating each other in order to cushion between the various materials because of thermal expansion coefficient difference, so not only can reduce the warpage degree of base plate for packaging bar, can also make that the base plate for packaging bar is more frivolous.
Description of drawings
Fig. 1 is the stereogram of the utility model one embodiment base plate for packaging bar structure.
Fig. 2 is the generalized section of the utility model one embodiment base plate for packaging bar structure.
Fig. 3 is the generalized section of another embodiment base plate for packaging bar structure of the utility model.
Fig. 4 is the generalized section of the another embodiment base plate for packaging of the utility model bar structure.
Fig. 5 A is the local amplification profile schematic diagram of the stress relief hole of the utility model one embodiment base plate for packaging bar structure.
Fig. 5 B is the local amplification profile schematic diagram of the stress relief hole of another embodiment base plate for packaging bar structure of the utility model.
Fig. 6 A-6I is the generalized section of the utility model one each step of embodiment base plate for packaging bar manufacture method.
Embodiment
For allowing the utility model above-mentioned purpose, feature and advantage become apparent, the utility model preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.Moreover, the direction term that the utility model is mentioned, for example " on ", D score, " top ", " end ", " preceding ", " back ", " left side ", " right side ", " interior ", " outward ", " side ", " on every side ", " central authorities ", " level ", " laterally ", " vertically ", " vertically ", " axially ", " radially ", " the superiors " or " orlop " etc., only be the direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the utility model, but not in order to limit the utility model.
Please refer to shown in Figure 1ly, the base plate for packaging bar of the utility model one embodiment structure 100 mainly comprises: a substrate body 110, a plurality of base board unit 120, a cutting area 130 and a plurality of stress relief hole 140.Described substrate body 110 comprises at least one dielectric layer 113 (being shown in Fig. 2) and at least one circuit layer 111 (being shown in Fig. 2), and described dielectric layer 113 and circuit layer 111 alternately stack arrangement.Described a plurality of base board unit 120 defines and is arranged on the described substrate body 110.130 of described cutting areas are around described base board unit 120, to connect wantonly two adjacent described base board units 120.Described a plurality of stress relief hole 140 is arranged in the scope of described cutting area 130, and runs through at least one described dielectric layer 113.
Please refer to shown in Figure 2, it discloses the generalized section of the utility model one embodiment, it for example is the base plate for packaging bar structure 100 of a double layer circuit structure, wherein said substrate body 110 comprises single dielectric layer 113, two circuit layers 111 and at least one conductive pole 114, described dielectric layer 113 and circuit layer 111 alternately stack arrangement, described two circuit layers 111 are positioned at the upper and lower surface of described dielectric layer 113, described conductive pole 114 is arranged in the described dielectric layer 113, in order to electrically connect described two circuit layers 111.Described cutting area 130 refers to connect the zone between the wantonly two adjacent described base board units 120, and to be illustrated between two dotted lines.Described a plurality of stress relief hole 140 is arranged in the scope of described cutting area 130, and runs through single described dielectric layer 113.In addition, also comprise upper surface and a lower surface and described two circuit layers 111 that two solder masks 112 are covered in described dielectric layer, described solder mask 112 only exposes described cutting area 130 and described stress relief hole 140.
Please refer to shown in Figure 3, it discloses the generalized section of another embodiment of the utility model, it for example is the base plate for packaging bar structure 100 of three layers of circuit structure, wherein said substrate body 110 comprises two layers of dielectric layer 113, three layers of circuit layer 111 and at least one conductive pole 114, described dielectric layer 113 and circuit layer 111 alternately stack arrangement, described three layers of circuit layer 111 are between wantonly two adjacent described dielectric layers 113, described conductive pole 114 is arranged in the described dielectric layer 113, in order to electrically connect wantonly two adjacent described circuit layers 111, one of them of described two layers of dielectric layer 113 (as the dielectric layer 113 of top) can be the dielectric layer structure of prefabricated shaping, and another 113 of described dielectric layer is to utilize to increase layer process formation.Described a plurality of stress relief hole 140 is arranged in the scope of described cutting area 130 equally, and runs through the described dielectric layer 113 that utilization increases layer process formation.In addition, also comprise two solder masks 112 and be covered in described dielectric layer 113 common a upper surface and a lower surface, described solder mask 112 exposes described cutting area 130 and described stress relief hole 140.
Please refer to shown in Figure 4, it discloses the generalized section of the another embodiment of the utility model, it for example is the base plate for packaging bar structure 100 of five layers of circuit structure, wherein said substrate body 110 comprises four layers of dielectric layer 113, five layers of circuit layer 111 and at least one conductive pole 114, described dielectric layer 113 and circuit layer 111 alternately stack arrangement, described five layers of circuit layer 111 are between wantonly two adjacent described dielectric layers 113, described conductive pole 114 is arranged in the described dielectric layer 113, in order to electrically connect wantonly two adjacent described circuit layers 111, one of them of described four layers of dielectric layer 113 (as the dielectric layer 113 of below) can be prefabricated dielectric layer structure, and three 113 of described dielectric layers can be to utilize to increase layer process and form in addition.Described a plurality of stress relief hole 140 is arranged at least one utilization and increases in the dielectric layer 113 (as the dielectric layer 113 of the below second layer and the dielectric layer 113 of the top) that layer process forms, and is positioned at the scope of described cutting area 130, and runs through above-mentioned dielectric layer 113.In addition, also comprise two solder masks 112 and be covered in described dielectric layer 113 common a upper surface and a lower surface, described solder mask 112 exposes described cutting area 130 and described stress relief hole 140.
In the above-described embodiment, described substrate body 110 comprises at least two layers described dielectric layer 113 and at least three layers described circuit layer 111, described stress relief hole 140 is arranged in the dielectric layer 113 of one of them layer, and when increasing layer process and form another adjacent described dielectric layer 113, the dielectric material of the described dielectric layer 113 that another is adjacent can be inserted in the described stress relief hole 140, but the openend of outermost described stress relief hole 140 is the outer surfaces (upper surface) that expose in described substrate body 110.All stress relief holes 140 are in the vertical all to being positioned at described cutting area 130.
In the above-described embodiment, described circuit layer 111 forms (or forming with patterning photoresist collocation electroplating technology) at least one pattern circuit with copper foil layer collocation patterning photoresist and etched technology, and described circuit layer 111 also electrically connects with described conductive pole 12.The material of described circuit layer 111 is copper, nickel, gold, silver or aluminium etc. for example, but is not limited to this.When described circuit layer 111 is an external circuit layer at this, then can further be coated with one deck solder mask 112 again to protect, only by described solder mask 112 exposed a part of described circuit layers 111, with as the weld pad purposes.
In addition, the material of described dielectric layer 113 can be dielectric resin material, for example glass layer is through containing the made B rank film (B-stage prepreg) of epoxy resin dipping (epoxy) and dry sclerosis back, it utilizes its run gum and gummosis characteristic in HTHP, be pressed together on described circuit layer 111, then be heating and curing again and can obtain described dielectric layer 113, the height of described dielectric layer 113 is approximately between 30 to 150 microns, but be not limited to this, described dielectric layer 113 makes the material of apparatus relatively low thermel expansion coefficient as far as possible.
Please refer to shown in the local amplification view of Fig. 5 A and 5B, and simultaneously again with reference to figure 1, described stress relief hole 140 is cylinder holes, and its cross section can be wherein one in circular, square or the polygon, wherein polygon may be triangle, quadrangle or other shapes.When the cross section of described stress relief hole 140 was circle, its diameter was between about 10 to 300 microns.Described stress relief hole 140 has one first opening (upper shed) 141, one second opening (under shed) 142, an and sidewall 143 described first opening 141 of connection and described second openings 142, the cross-sectional area of described second opening 142 can be equal to or greater than the cross-sectional area of described first opening 141, and described sidewall 143 has an intrados section or a straight inclined plane in the position near described second opening 142.Described intrados section or the length on described straight inclined plane are equal to or less than the total length of the sidewall 143 of described a plurality of stress relief hole 140.Described stress relief hole 140 is hollow form in described dielectric layer 113, the hole wall of described stress relief hole 140 itself has the physical property structural strength.Described stress relief hole 140 can be arranged in the interior arbitrary dielectric layer 113 of described cutting area 130 scopes, do not limit its number, the position in described cutting area 130 scopes or in what dielectric layer 113, for example described stress relief hole 140 can mainly be arranged on the position of the cross cutting area 130 between each four adjacent substrate unit 120, is not limited to this.Described stress relief hole 140 can cause the phenomenon pullled by thermal stress behind the expanded by heating each other in order to cushion in the described substrate body 110 between the various materials because of thermal expansion coefficient difference.
The utility model will be in hereinafter utilizing Fig. 6 A to 6I to describe in detail one by one, and the utility model one embodiment base plate for packaging bar is constructed 100 manufacture method, and it mainly comprises the following step:
At first, please refer to shown in Fig. 6 A, in a step (a), provide a support plate 200 earlier, described support plate 200 also can be the dielectric layer (as the dielectric layer 113 of Fig. 3 top or Fig. 4 dielectric layer 113 of below) of a prefabricated shaping, and described prefabricated dielectric layer also comprises the conductive pole of at least one prefabricated shaping;
Then, please continue with reference to shown in Fig. 6 A, in a step (b), utilize the first photoresist layer 300a of a patterning, described support plate 200 electroplate be formed up to the position that marks between a few conductive pole 114 and a plurality of interim conductive pole 131, two dotted lines for later on as cutter contraposition cut a cutting area 130 of a plurality of base board unit 120 required uses.Described support plate 200 can have a thin metal layer in the face of a side of described conductive pole 114 and interim conductive pole 131, and thin copper layer for example is with as the peel ply purposes;
Afterwards, shown in Fig. 6 B, in a step (c), remove the described first photoresist layer 300a, stay established described conductive pole 114 and described a plurality of interim conductive pole 131 at described support plate 200, the cross section of described interim conductive pole 131 can be wherein one in circular, square or the polygon, and wherein polygon may be triangle, quadrangle or other shapes.When the cross section of described interim conductive pole 131 was circle, its diameter was between about 10 to 300 microns.Described interim conductive pole 131 has a first surface (upper surface), a second surface (lower surface), and a sidewall connects described first surface and described second surface, the cross-sectional area of wherein said second surface is greater than the cross-sectional area of described first surface, and described sidewall has an intrados section or a straight inclined plane in the position near described second surface;
Then, please refer to shown in Fig. 6 C, in a step (d), upper surface, described conductive pole 114 and the described interim conductive pole 131 of pressing one dielectric layer 113 (for example B rank film) to cover described support plate 200, and expose an end of described conductive pole 114 and described interim conductive pole 131 to the open air;
Afterwards, shown in Fig. 6 D, in a step (e), utilize one second photoresist layer 300b to cover described dielectric layer 113, and the described second photoresist layer 300b of patterning, to expose an end of described interim conductive pole 131 to the open air;
Then, shown in Fig. 6 E, in a step (f), described interim conductive pole 114 is removed in etching, to form a plurality of stress relief holes 140 at described dielectric layer 113; Described stress relief hole 140 is cylinder holes, described stress relief hole 140 has one first opening 141, one second opening 142, an and sidewall 143 described first opening 141 of connection and described second openings 142, the cross-sectional area of described second opening 142 is greater than the cross-sectional area of described first opening 141, and described sidewall 143 has an intrados section or a straight inclined plane.Described intrados section or the length on described straight inclined plane are equal to or less than the total length of the sidewall 143 of described a plurality of stress relief hole 140.Described stress relief hole 140 is hollow form in described dielectric layer 113.Then, remove the described second photoresist layer 300b;
At last, shown in Fig. 6 F, in a step (g), form first circuit layer 111 of a patterning at the 3rd photoresist layer 300c of another patterning of upper surface recycling of described dielectric layer 113.
Please refer to shown in Fig. 6 G, in a step (h), after forming the step of first circuit layer 111, if during the prefabricated dielectric layer of described support plate 200 non-, just remove described support plate 200; When if described support plate 200 is a prefabricated dielectric layer, does not just need this step, and can directly finish the action that increases layer.If described support plate 200 has a thin metal layer, after then described support plate 200 being removed, described thin metal layer stays in a lower surface of described dielectric layer 113, and this moment, etching removed described thin metal layer in addition;
Please refer to shown in Fig. 6 H, in step (h) afterwards, then in a step (i), can continue to form at a lower surface of described dielectric layer 113 the second circuit layer 111 ' of a patterning, described second circuit layer 111 ' electrically connects by described conductive pole 114 and described first circuit layer 111.
In addition, if after above-mentioned steps, want to increase the circuit number of plies, just carry out a step (j), with continue the upper surface of described dielectric layer 113 or lower surface again pressing form another and increase a layer dielectric layer (as second dielectric layer 113 of Fig. 4 top), and the described dielectric material that increases layer dielectric layer can be inserted in the described stress relief hole 140, but the hole wall of described stress relief hole 140 itself still has the physical property structural strength, can pull phenomenon in order to the thermal stress that cushions between the various materials.
In addition, please refer to shown in Fig. 6 I, if the upper surface of described dielectric layer 113 does not have to increase layer, then can comprise a step (g1) in addition afterwards in step (g), in order to form the upper surface that a solder mask 112 is covered in described dielectric layer 113 again, one cutting area 130 of described solder mask 112 exposed described dielectric layers 113,140 of described stress relief holes are in the scope of described cutting area 130.
Described stress relief hole 140 not only causes the phenomenon pullled by thermal stress behind the expanded by heating each other in order to cushion to comprise in the described substrate body 110 between the various materials because of thermal expansion coefficient difference, the setting of described stress relief hole 140 does not influence and can keep described substrate body 110 integrally-built integralities, and guarantee to have enough structural strengths before described base plate for packaging bar structure 100 is cut separation relatively, and the described stress relief hole 140 in the outermost layer dielectric layer 113 can not inserted the material of dielectric layer, the cutter waste in the time of yet can reducing the cutter cutting relatively.
The utility model is described by above-mentioned related embodiment, yet above-described embodiment is only for implementing example of the present utility model.Must be pointed out that disclosed embodiment does not limit scope of the present utility model.On the contrary, being contained in the spirit of claims and modification and impartial setting of scope is included in the scope of the present utility model.
Claims (9)
1. a base plate for packaging bar is constructed, and it is characterized in that: described base plate for packaging bar structure bag contains ︰
One substrate body comprises at least one dielectric layer and at least one circuit layer, and described dielectric layer and circuit layer alternately stack arrangement;
A plurality of base board units define and are arranged on the described substrate body;
One cutting area, position are around described base board unit, to connect wantonly two adjacent described base board units;
And
A plurality of stress relief holes are arranged in the scope of described cutting area, and run through at least one described dielectric layer.
2. base plate for packaging bar as claimed in claim 1 is constructed, and it is characterized in that: described stress relief hole is cylinder hole.
3. base plate for packaging bar as claimed in claim 2 is constructed, and it is characterized in that: the cross section of described stress relief hole is circle or polygon.
4. base plate for packaging bar as claimed in claim 3 is constructed, and it is characterized in that: the cross section of described stress relief hole is circular, and diameter is between about 10 to 300 microns.
5. base plate for packaging bar as claimed in claim 2 is constructed, it is characterized in that: described stress relief hole has one first opening, one second opening, reach a sidewall and connect described first opening and described second opening, the cross-sectional area of described second opening is greater than the cross-sectional area of described first opening.
6. base plate for packaging bar as claimed in claim 5 is constructed, and it is characterized in that: described sidewall has an intrados section.
7. base plate for packaging bar as claimed in claim 1 is constructed, and it is characterized in that: described stress relief hole is hollow form in described dielectric layer.
8. base plate for packaging bar as claimed in claim 1 is constructed, it is characterized in that: described substrate body comprises at least two layers described dielectric layer and at least three layers described circuit layer, described stress relief hole is arranged in the dielectric layer of one of them layer, and the dielectric material of another adjacent described dielectric layer is inserted in the described stress relief hole.
9. base plate for packaging bar as claimed in claim 1 is constructed, and it is characterized in that: described base plate for packaging bar structure comprises a upper surface and a lower surface that two solder masks are covered in described dielectric layer in addition, and described solder mask exposes described cutting area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220691033 CN203192781U (en) | 2012-12-13 | 2012-12-13 | A packaging substrate strip structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220691033 CN203192781U (en) | 2012-12-13 | 2012-12-13 | A packaging substrate strip structure |
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| CN203192781U true CN203192781U (en) | 2013-09-11 |
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| CN 201220691033 Expired - Fee Related CN203192781U (en) | 2012-12-13 | 2012-12-13 | A packaging substrate strip structure |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066029A (en) * | 2012-12-13 | 2013-04-24 | 日月光半导体（上海）股份有限公司 | Packaging substrate strip structure and manufacturing method thereof |
| CN103824831A (en) * | 2014-02-20 | 2014-05-28 | 清华大学 | Package substrate and manufacturing method thereof |
| CN111696979A (en) * | 2019-03-14 | 2020-09-22 | 联发科技股份有限公司 | Semiconductor packaging structure |
| US11862578B2 (en) | 2017-03-14 | 2024-01-02 | Mediatek Inc. | Semiconductor package structure |
| US11942439B2 (en) | 2017-03-14 | 2024-03-26 | Mediatek Inc. | Semiconductor package structure |
| US11948895B2 (en) | 2017-03-14 | 2024-04-02 | Mediatek Inc. | Semiconductor package structure |
| CN111696979B (en) * | 2019-03-14 | 2024-04-23 | 联发科技股份有限公司 | Semiconductor packaging structure |
-
2012
- 2012-12-13 CN CN 201220691033 patent/CN203192781U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066029A (en) * | 2012-12-13 | 2013-04-24 | 日月光半导体（上海）股份有限公司 | Packaging substrate strip structure and manufacturing method thereof |
| CN103066029B (en) * | 2012-12-13 | 2015-07-15 | 日月光半导体(上海)有限公司 | Packaging substrate strip structure and manufacturing method thereof |
| CN103824831A (en) * | 2014-02-20 | 2014-05-28 | 清华大学 | Package substrate and manufacturing method thereof |
| US11862578B2 (en) | 2017-03-14 | 2024-01-02 | Mediatek Inc. | Semiconductor package structure |
| US11942439B2 (en) | 2017-03-14 | 2024-03-26 | Mediatek Inc. | Semiconductor package structure |
| US11948895B2 (en) | 2017-03-14 | 2024-04-02 | Mediatek Inc. | Semiconductor package structure |
| CN111696979A (en) * | 2019-03-14 | 2020-09-22 | 联发科技股份有限公司 | Semiconductor packaging structure |
| CN111696979B (en) * | 2019-03-14 | 2024-04-23 | 联发科技股份有限公司 | Semiconductor packaging structure |
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| CF01 | Termination of patent right due to non-payment of annual fee |
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