CN203055903U - Multilayer packaging substrate structure - Google Patents
Multilayer packaging substrate structure Download PDFInfo
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- CN203055903U CN203055903U CN 201220690506 CN201220690506U CN203055903U CN 203055903 U CN203055903 U CN 203055903U CN 201220690506 CN201220690506 CN 201220690506 CN 201220690506 U CN201220690506 U CN 201220690506U CN 203055903 U CN203055903 U CN 203055903U
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 title claims abstract description 47
- 229910000679 solder Inorganic materials 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920001187 thermosetting polymer Polymers 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 201
- 238000000034 method Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 238000000059 patterning Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 241000531908 Aramides Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 208000034189 Sclerosis Diseases 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229920006231 aramid fiber Polymers 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
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- 239000011521 glass Substances 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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Abstract
The utility model discloses a multilayer packaging substrate structure, comprising a core board, a first build-up structure and a second build-up structure. The core board comprises a core dielectric layer, two core circuit layers and at least one first laser conductive hole; the first build-up structure is positioned in one surface of the core dielectric layer, and comprises a first dielectric layer, a first circuit layer and at least one second laser conductive hole, wherein the thickness of the first build-up structure equals to that of the core board; and the second build-up structure is positioned in the other surface of the core dielectric layer, and comprises a second dielectric layer, at least one first conductive pole penetrating through the second dielectric layer and a second circuit layer. According to the utility model, a thin core board with dielectric layers and metal layers at two sides is used to carry out circuit build-up, thereby reducing the thickness of a substrate and improving integration of the circuit.
Description
Technical field
The utility model relates to a kind of layer multilayer packaging substrate structure, particularly relevant for a kind of layer multilayer packaging substrate structure with thin core board.
Background technology
Now, the semiconductor packages industry is in order to satisfy the package requirements of various high degree of integration (integration) and microminiaturized (miniaturization), connect for more active passive assemblies and circuit, conductor package substrate develops into multilayer circuit board by double-layer circuit board gradually, can be for the configuration area that utilizes on the conductor package substrate under limited space, to use interlayer interconnection technique (interlayer connection) to enlarge, except this, reduce the thickness of base plate for packaging, it is not only compact but also can improve the purpose of electrical functionality just to reach packaging part simultaneously.
The multilayer circuit board of prior art is by a core board and be symmetrically formed at the circuit layer reinforced structure of its both sides and formed.But because base plate for packaging needs to use the core board with adequate thickness to guarantee to provide enough support strengths during increasing layer, and prevent from pullling the warpage problems such as (warpage) that produces because of thermal stress (thermal stress), so the thickness of core board causes the integral thickness of base plate for packaging to increase; Moreover, if in base plate for packaging manufacturing process, remove core board, need on the one hand to increase to make formality, in the process that removes on the other hand, also cause the distortion of multilayer circuit easily.
So, be necessary to provide a kind of layer multilayer packaging substrate structure, to solve the existing in prior technology problem.
The utility model content
In view of this, the utility model provides a kind of layer multilayer packaging substrate structure, removes the problem that causes the base plate for packaging distortion to solve the blocked up or core board of the existing core board of prior art.
Main purpose of the present utility model is to provide a kind of layer multilayer packaging substrate structure, and it utilizes a thin core board with a dielectric layer and both sides metal level, increases the technology of layer circuit, can reduce substrate thickness and improve circuit level.
Secondary objective of the present utility model is to provide a kind of layer multilayer packaging substrate structure, it utilizes a thin core board with a dielectric layer and both sides metal level, increase the technology of layer circuit, can save the step that removes core board, and then improve speed of production, reduce manufacturing cost and avoid substrate in removing process, to be out of shape.
For reaching aforementioned purpose of the present utility model, the utility model one embodiment provides a kind of layer multilayer packaging substrate structure, and described base plate for packaging structure comprises: a core board, one first layer reinforced structure and one second layer reinforced structure.Described core board comprises: a core dielectric layer, two core circuit layers and at least one first laser conductive hole.Described core dielectric layer has a first surface and a second surface.Described two core circuit layers respectively are arranged on described first surface and the second surface.The described first laser conductive hole runs through described first surface and second surface, to electrically connect described two core circuit layers.Described first layer reinforced structure comprises: one first dielectric layer, one first circuit layer and at least one second laser conductive hole.Described first dielectric layer is covered on the first surface and described core circuit layer of described core dielectric layer.Described first circuit layer is arranged on the surface of described first dielectric layer away from described core circuit layer.The described second laser conductive hole runs through in described first dielectric layer, to electrically connect described core circuit layer and described first circuit layer.Described second layer reinforced structure comprises: one second dielectric layer, a second circuit layer and a plurality of first conductive pole.Described second dielectric layer is arranged on the second surface of described core dielectric layer.Described second circuit layer is arranged on the surface of described second dielectric layer away from described core circuit layer.Described a plurality of first conductive pole runs through described second dielectric layer, to electrically connect described core circuit layer and second circuit layer.2 microns of the roughness (Ra) of the wherein said first laser conductive hole and the second laser conductive hole, the roughness of described a plurality of first conductive poles (Ra) is less than 1 micron.
Moreover another embodiment of the utility model provides another kind of layer multilayer packaging substrate structure, and described base plate for packaging structure comprises: a core board, one first layer reinforced structure and two second layer reinforced structures.Described core board comprises: a core dielectric layer, two core circuit layers and at least one first laser conductive hole.Described core dielectric layer has a first surface and a second surface.Described two core circuit layers respectively are arranged on described first surface and the second surface.Described at least one first laser conductive hole runs through described first surface and second surface, to electrically connect described two core circuit layers.Described first layer reinforced structure comprises: one first dielectric layer, one first circuit layer and at least one second laser conductive hole.Described first dielectric layer is covered on the first surface and described core circuit layer of described core dielectric layer.Described first circuit layer is arranged on the surface of described first dielectric layer away from described core circuit layer.The described second laser conductive hole runs through in described first dielectric layer, to electrically connect described core circuit layer and described first circuit layer.Described two second layer reinforced structures comprise: two second dielectric layers, a plurality of first conductive pole and two second circuit layers.Described two second dielectric layers are arranged at respectively on the second surface of described core dielectric layer, and are arranged on the surface of described first dielectric layer away from described core circuit layer.Described a plurality of first conductive pole runs through described second dielectric layer, electrically connecting described core circuit layer respectively, and electrically connects described first circuit layer.Described two second circuit layers are arranged at respectively on the surface of described two second dielectric layers away from described core circuit layer, to electrically connect described first conductive pole.The roughness of the wherein said first laser conductive hole and the second laser conductive hole is less than 2 microns, and the roughness of described a plurality of first conductive poles is less than 1 micron.
Compared with prior art, layer multilayer packaging substrate structure of the present utility model so not only can be simplified processing step, can also make base plate for packaging frivolous and not yielding.
Description of drawings
Fig. 1 is the generalized section of the utility model one embodiment layer multilayer packaging substrate structure.
Fig. 2 is the generalized section of another embodiment layer multilayer packaging substrate structure of the utility model.
Fig. 3 is the generalized section of the another embodiment layer multilayer packaging substrate structure of the utility model.
Fig. 4 A-4I is the schematic diagram of the manufacture method of the utility model one embodiment layer multilayer packaging substrate structure.
Embodiment
For allowing the utility model above-mentioned purpose, feature and advantage become apparent, the utility model preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.Moreover, the direction term that the utility model is mentioned, for example " on ", D score, " top ", " end ", " preceding ", " back ", " left side ", " right side ", " interior ", " outward ", " side ", " on every side ", " central authorities ", " level ", " laterally ", " vertically ", " vertically ", " axially ", " radially ", " the superiors " or " orlop " etc., only be the direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the utility model, but not in order to limit the utility model.
Please refer to shown in Figure 1ly, the utility model one embodiment is that four layers layer multilayer packaging substrate structure mainly comprises: described base plate for packaging structure comprises: a core board 10, one first layer reinforced structure 20 and one second layer reinforced structure 30a.Described core board 10 comprises: a core dielectric layer 11, two core circuit layer 12a ', 12b ' and at least one first laser conductive hole 13.Described core dielectric layer 11 has a first surface and a second surface.Described two core circuit layer 12a ', 12b ' respectively are arranged on described first surface and the second surface.The described first laser conductive hole 13 runs through described first surface and second surface, to electrically connect described two core circuit layer 12a ', 12b '.
Moreover the thickness of described first layer reinforced structure 20 is substantially equal to the thickness 10 of described core board, and comprises: one first dielectric layer 21, one first circuit layer 22 and at least one second laser conductive hole 23.Described first dielectric layer 21 is covered on the first surface and described core circuit layer 12a ' of described core dielectric layer 11.Described first circuit layer 22 is arranged on the surface of described first dielectric layer 21 away from described core circuit layer 12a '.The described second laser conductive hole 23 runs through in described first dielectric layer 21, to electrically connect described core circuit layer 12a ' and described first circuit layer 22.
In addition, the described second layer reinforced structure 30a comprises: one second dielectric layer 31a, a plurality of first conductive pole 32a and a second circuit layer 33a.The described second dielectric layer 31a is arranged on the second surface of described core dielectric layer 11.Described second circuit layer 33a is arranged on the surface of the described second dielectric layer 31a away from described core circuit layer 12a '.Described a plurality of first conductive pole 32a runs through the described second dielectric layer 31a, to electrically connect described core circuit layer 12a ' and second circuit layer 33a.The described first conductive pole 32a is the copper post.The roughness of the wherein said first laser conductive hole 13 and the second laser conductive hole 23 is less than 2 microns, and the roughness of described a plurality of first conductive pole 32a is less than 1 micron.Moreover, described layer multilayer packaging substrate structure also comprises: two solder mask 40a, 40b, be separately positioned on outside described first circuit layer 22 and the described second circuit layer 33a, and described solder mask 40a, 40b have a plurality of solder mask perforates, some with exposed described first circuit layer 22 and described second circuit layer 33a forms a plurality of connection gaskets.
Please refer to shown in Figure 2, another embodiment of the utility model is the basic framework that five layers layer multilayer packaging substrate structure comprises among Fig. 1 four layers layer multilayer packaging substrate structure, wherein comprise described core board 10 and described first layer reinforced structure 20, but comprise two the second layer reinforced structure 30a, 30b.Described two the second layer reinforced structure 30a, 30b comprise: two the second dielectric layer 31a, 31b, a plurality of first conductive pole 32a, 32b and two second circuit layer 33a, 33b.Described two the second dielectric layer 31a, 31b are arranged at respectively on the second surface of described core dielectric layer 11, and are arranged on the surface of described first dielectric layer 21 away from described core circuit layer 12a '.Described a plurality of first conductive pole 32a, 32b run through the described second dielectric layer 31a, 31b, electrically connecting described core circuit layer 12a ', 12b ' respectively, and electrically connect described first circuit layer 22.Described two second circuit layer 33a, 33b are arranged at respectively on the surface of described two the second dielectric layer 31a, 31b away from described core circuit layer 12a ', 12b ', to electrically connect the described first conductive pole 32a, 32b.The described first conductive pole 32a, 32b are the copper post.Moreover, described layer multilayer packaging substrate structure also comprises: two solder mask 40a, 40b be separately positioned on outside described second circuit layer 33a, the 33b, and described solder mask 40a, 40b have a plurality of solder mask perforates, some with exposed described second circuit layer 33a, 33b forms a plurality of connection gaskets.
Please refer to shown in Figure 3, the another embodiment of the utility model is seven layers layer multilayer packaging substrate structure, its mainly on the basis of five layers layer multilayer packaging substrate structure (as Fig. 2, but do not contain described solder mask 40a, 40b among the figure, described solder mask 40a, 40b are separately positioned in this figure outside described second circuit layer 33a, the 33b), other comprises: two the 3rd layer reinforced structures, it comprises: two the 3rd dielectric layers are arranged at respectively on the surface of described second dielectric layer away from described core circuit layer; A plurality of second conductive poles run through described the 3rd dielectric layer, to electrically connect described second circuit layer; And two tertiary circuit layers, be arranged on the surface of described the 3rd dielectric layer away from described second dielectric layer, and electrically connect described second conductive pole.Except this, also comprise two solder mask 40a, 40b, be separately positioned on outside the described tertiary circuit layer, and described solder mask 40a, 40b have a plurality of solder mask perforates, the some with exposed described tertiary circuit layer forms a plurality of connection gaskets.Described core board 10 in above embodiment, described first layer reinforced structure 20 and the described second layer reinforced structure 30a, 30b are also or other thickness that increase layer are equal to each other basically.
The present invention will be in hereinafter utilizing Fig. 4 A to 4I to describe in detail one by one, the manufacture method of one embodiment of the invention base plate for packaging bar structure, and it mainly comprises the following step:
At first, please refer to shown in Fig. 4 A, one core board 10 is provided, described core board 10 comprises a core dielectric layer 11 and two core copper foil layer 12a, 12b, the core dielectric layer 11 of described core board 10 can be ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid CrystalPolymer), PI (Poly-imide), FR4, FR5, BT (Bismaleimide Triazine), aramid fiber (Aramide), one of epoxy resin and glass fibre institute cohort group person or other equivalent materials, as thermosetting resin material etc., and the thickness of described core board is between 50 to 80 microns;
Then, please refer to shown in Fig. 4 B, utilize a photomask to form at least one first laser conductive hole 13, run through described first surface and second surface, to electrically connect described two core circuit layer 12a, 12b, the described first laser conductive hole 13 is about a column emptying aperture wide at the top and narrow at the bottom, and generation type can be holed at described core dielectric layer 11 with laser drill, and the roughness of described column emptying aperture (Ra) is less than 2 microns;
Then, please refer to shown in Fig. 4 C, utilize the first photoresist layer 50a of a patterning, the first laser conductive hole 13 as described in plating fills up to form as materials such as copper, nickel, gold, aluminium with electric conducting material again on described core circuit layer 12b;
Afterwards, please refer to shown in Fig. 4 D, in the both sides up and down of described core board 10, respectively utilize second and third photoresist layer 50b, the 50c of a patterning to make described two core copper foil layer 12a, 12b be etched into core circuit layer 12a ', the 12b ' of two patternings;
Then, to form one first layer reinforced structure 20 at the lower surface of described core board 10, please refer to shown in Fig. 3 E, first surface and described core circuit layer 12a ' at described core dielectric layer 11 goes up pressing one first dielectric layer 21 earlier, the material of described first dielectric layer 21 can be dielectric resin material, for example glass layer is through containing the made B rank film (B-stage prepreg) of epoxy resin dipping (epoxy) and dry sclerosis back, it utilizes its run gum and gummosis characteristic in HTHP, be pressed together on described core circuit layer 12a ', then be heating and curing again and can obtain described first dielectric layer 21, its thickness is substantially equal to the thickness of described core board 10;
Afterwards, please refer to shown in Fig. 4 F, recycling one photomask forms at least one second laser conductive hole 23, runs through in described first dielectric layer 21, and using laser drill in described first layer reinforced structure 20 is to avoid if use the plated conductive post, thinner because of substrate when brushing technology, also the circuit brush is opened, caused breaking phenomena, so in first layer reinforced structure 20, to use the technology of laser drill, the roughness of the described second laser conductive hole 23 (Ra) is less than 2 microns;
Next, please refer to shown in Fig. 4 G, respectively utilize the 4th photoresist layer 50d of a patterning to form first circuit layer 22 of a patterning on the surface of described first dielectric layer 21 away from described core circuit layer 12a ', the material of described first circuit layer 22 for example is copper, nickel, gold, silver or aluminium etc., but be not limited to this, so finish described first layer reinforced structure 20, its thickness is substantially equal to the thickness of described core board;
Then, please refer to shown in Fig. 4 H, continue to form one second layer reinforced structure 30a, utilize the 5th photoresist layer 50e of a patterning to form a plurality of first conductive pole 32a, described a plurality of first conductive pole 32a are the copper post, and its roughness (Ra) is less than 1 micron;
Afterwards, shown in Fig. 4 I, remove described the 5th photoresist layer 50e, then pressing one second dielectric layer 31b is arranged on the second surface of described core dielectric layer 11, and envelopes described a plurality of first conductive pole 32a;
At last, as shown in Figure 1, form two solder mask 40a, 40b outside described first circuit layer 22 and described second circuit layer 33a, and described solder mask 40a, 40b have a plurality of solder mask perforates, some with exposed described first circuit layer 22 and described second circuit layer 33a, form a plurality of connection gaskets, described solder mask 40a, 40b can be the green lacquer of welding resistance and pitch-dark (solder mask) the photosensitive polymer material wherein one or the material of other equivalences.And the formation method of a solder mask perforate can be the method for exposure and development or other equivalences more than described solder mask 40a, the 40b.
The utility model provides a kind of layer multilayer packaging substrate structure, its utilization has the described core board 10 of described two core circuit layer 12a ', the 12b ' of described core dielectric layer 11 and both sides, increase the technology of layer circuit, can reduce substrate thickness and improve circuit level, also can remove the step of core board by saving, and improve speed of production, reduction manufacturing cost, and and then avoid substrate in removing process, to be out of shape.
The utility model is described by above-mentioned related embodiment, yet above-described embodiment is only for implementing example of the present utility model.Must be pointed out that disclosed embodiment does not limit scope of the present utility model.On the contrary, being contained in the spirit of claims and modification and impartial setting of scope is included in the scope of the present utility model.
Claims (10)
1. a layer multilayer packaging substrate is constructed, and it is characterized in that: described layer multilayer packaging substrate structure comprises:
One core board comprises:
One core dielectric layer has a first surface and a second surface;
Two core circuit layers respectively are arranged on described first surface and the second surface; And
At least one first laser conductive hole runs through described first surface and second surface, to electrically connect described two core circuit layers;
One first layer reinforced structure comprises:
One first dielectric layer is covered on the first surface and described core circuit layer of described core dielectric layer;
One first circuit layer is arranged on the surface of described first dielectric layer away from described core circuit layer; And
At least one second laser conductive hole runs through described first dielectric layer, to electrically connect described core circuit layer and described first circuit layer; And
One second layer reinforced structure comprises:
One second dielectric layer is arranged on the second surface of described core dielectric layer;
One second circuit layer is arranged on the surface of described second dielectric layer away from described core circuit layer; And
A plurality of first conductive poles run through described second dielectric layer, to electrically connect described core circuit layer and second circuit layer;
The roughness of the side surface of the wherein said first laser conductive hole and the second laser conductive hole is greater than 2 microns, and the roughness of the side surface of described a plurality of first conductive poles is less than 1 micron.
2. layer multilayer packaging substrate as claimed in claim 1 is constructed, and it is characterized in that: the thickness of described core board is between 50 to 80 microns.
3. layer multilayer packaging substrate as claimed in claim 1 is constructed, and it is characterized in that: described core board is the thermosetting resin core board.
4. layer multilayer packaging substrate as claimed in claim 1 or 2 is constructed, and it is characterized in that: the thickness of described core board, described first layer reinforced structure and described second layer reinforced structure is equal to each other.
5. layer multilayer packaging substrate as claimed in claim 1 is constructed, and it is characterized in that: described layer multilayer packaging substrate structure also comprises:
Two solder masks are separately positioned on outside described first circuit layer and the described second circuit layer, and described solder mask has a plurality of solder mask perforates, and the some of exposed described first circuit layer and described second circuit layer forms a plurality of connection gaskets respectively.
6. layer multilayer packaging substrate as claimed in claim 1 is constructed, and it is characterized in that: described first conductive pole is the copper post.
7. a layer multilayer packaging substrate is constructed, and it is characterized in that: described layer multilayer packaging substrate structure comprises:
One core board comprises:
One core dielectric layer has a first surface and a second surface;
Two core circuit layers respectively are arranged on described first surface and the second surface; And
At least one first laser conductive hole runs through described first surface and second surface, to electrically connect described two core circuit layers;
One first layer reinforced structure comprises:
One first dielectric layer is covered on the first surface and described core circuit layer of described core dielectric layer;
One first circuit layer is arranged on the surface of described first dielectric layer away from described core circuit layer; And
At least one second laser conductive hole runs through described first dielectric layer, to electrically connect described core circuit layer and described first circuit layer; And
Two second layer reinforced structures comprise:
Two second dielectric layers are arranged at respectively on the second surface of described core dielectric layer, and are arranged on the surface of described first dielectric layer away from described core circuit layer;
A plurality of first conductive poles run through described second dielectric layer, electrically connecting described core circuit layer respectively, and electrically connect described first circuit layer; And
Two second circuit layers are arranged at respectively on the surface of described two second dielectric layers away from described core circuit layer, to electrically connect described first conductive pole;
The roughness of the side surface of the wherein said first laser conductive hole and the second laser conductive hole is greater than 2 microns, and the roughness of the side surface of described a plurality of first conductive poles is less than 1 micron.
8. layer multilayer packaging substrate as claimed in claim 7 is constructed, and it is characterized in that: described layer multilayer packaging substrate structure also comprises:
Two the 3rd layer reinforced structures comprise:
Two the 3rd dielectric layers are arranged at respectively on the surface of described second dielectric layer away from described core circuit layer;
A plurality of second conductive poles run through described the 3rd dielectric layer, to electrically connect described second circuit layer; And
Two tertiary circuit layers are arranged on the surface of described the 3rd dielectric layer away from described second dielectric layer, and electrically connect described second conductive pole.
9. layer multilayer packaging substrate as claimed in claim 8 is constructed, and it is characterized in that: described layer multilayer packaging substrate structure also comprises:
Two solder masks are separately positioned on outside the described tertiary circuit layer, and described solder mask has a plurality of solder mask perforates, and the some with exposed described tertiary circuit layer forms a plurality of connection gaskets.
10. layer multilayer packaging substrate as claimed in claim 7 is constructed, and it is characterized in that: the thickness of described core board, described first layer reinforced structure and described second layer reinforced structure is equal to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220690506 CN203055903U (en) | 2012-12-13 | 2012-12-13 | Multilayer packaging substrate structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220690506 CN203055903U (en) | 2012-12-13 | 2012-12-13 | Multilayer packaging substrate structure |
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| Publication Number | Publication Date |
|---|---|
| CN203055903U true CN203055903U (en) | 2013-07-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220690506 Expired - Fee Related CN203055903U (en) | 2012-12-13 | 2012-12-13 | Multilayer packaging substrate structure |
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| CN (1) | CN203055903U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956342A (en) * | 2014-04-30 | 2014-07-30 | 惠州市力道电子材料有限公司 | High-thermal-conductivity ceramic substrate containing solid metal thermal-conductive filler and manufacturing technology thereof |
| CN106898594A (en) * | 2017-02-28 | 2017-06-27 | 美的智慧家居科技有限公司 | Substrate for wireless fidelity systems level encapsulation chip and forming method thereof |
| CN108735686A (en) * | 2017-04-24 | 2018-11-02 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation device and its manufacturing method |
-
2012
- 2012-12-13 CN CN 201220690506 patent/CN203055903U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956342A (en) * | 2014-04-30 | 2014-07-30 | 惠州市力道电子材料有限公司 | High-thermal-conductivity ceramic substrate containing solid metal thermal-conductive filler and manufacturing technology thereof |
| CN106898594A (en) * | 2017-02-28 | 2017-06-27 | 美的智慧家居科技有限公司 | Substrate for wireless fidelity systems level encapsulation chip and forming method thereof |
| CN108735686A (en) * | 2017-04-24 | 2018-11-02 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation device and its manufacturing method |
| CN108735686B (en) * | 2017-04-24 | 2022-04-29 | 日月光半导体制造股份有限公司 | Semiconductor package device and method of manufacturing the same |
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