TWI433269B - Semiconductor structure and manufacturing method and operating method for the same - Google Patents

Description

Semiconductor structure and its manufacturing method and operation method /

The present invention relates to a semiconductor structure, a method of fabricating the same, and a method of operating the same, and more particularly to a memory device, a method of fabricating the same, and a method of operating the same.

Memory devices are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. In response to this demand, it is required to manufacture a memory device having a high component density.

Since device critical dimensions have been reduced to the limits of technology, designers have developed a way to increase the density of memory devices by using a three-dimensional stacked memory device to achieve higher memory capacity while reducing the cost per bit. However, the complicated structure of such a memory device also complicates the manufacturing method. In addition, the operability is limited by design.

The present invention relates to a semiconductor structure, a method of fabricating the same, and a method of operation. The manufacturing method is simple and the semiconductor structure can be operated in a variable manner.
A method of operating a semiconductor structure is provided. The semiconductor structure includes a substrate, a first stacked structure, a dielectric member, a conductive line, a first conductive island, and a second conductive island. The first stack structure is formed on the substrate. The first stack structure includes first staggered stacked conductive stripes and first insulating stripes. The first conductive strips are separated by a first insulating stripe. A dielectric element is formed on the first stacked structure. A conductive line is formed on the dielectric element. The direction in which the conductive lines extend is perpendicular to the direction in which the first stacked structure extends. The first conductive island and the second conductive island are formed on the dielectric element. The first conductive islands on the opposite sides of the first stacked structure are separated from the second conductive islands. The method of operating the semiconductor structure includes applying a first voltage to the first conductive island, respectively, and applying a second voltage to the second conductive island.
A method of fabricating a semiconductor structure is provided. The method includes the following steps. A stacked structure is formed on the substrate. The stacked structure includes a plurality of conductive stripes and a plurality of insulating stripes. The conductive stripes are separated by insulating stripes. A dielectric element is formed on the stacked structure. A conductive line is formed on the dielectric element. The direction in which the conductive lines extend is perpendicular to the direction in which the stacked structures extend. An electrically conductive island is formed on the dielectric element. Conductive islands located on opposite sides of a single stacked structure are separated from one another.
A semiconductor structure is provided. The semiconductor structure includes a substrate, a stacked structure, dielectric elements, conductive lines, and conductive islands. A stacked structure is formed on the substrate. The stacked structure includes staggered stacked conductive stripes and insulating stripes. The conductive stripes are separated by insulating stripes. The dielectric elements are formed on the stacked structure. A conductive line is formed on the dielectric element. The direction in which the conductive lines extend is perpendicular to the direction in which the stacked structures extend. A conductive island is formed on the dielectric element. Conductive islands located on opposite sides of a single stacked structure are separated from one another.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.

1 to 9 illustrate a manufacturing embodiment of a semiconductor structure. Referring to FIG. 1, the conductive layer 4 and the insulating layer 6 are alternately stacked on the substrate 2. The conductive layers 4 are separated from each other by the insulating layer 6. The conductive layer 4 includes polysilicon. In an embodiment, the conductive layer 4 may be doped and then annealed. The conductive layer 4 may also include a metal. The insulating layer 6 includes an oxide. The substrate 2 has a buried oxide layer 8 thereon. The conductive layer 4 and the insulating layer 6 are patterned to form the stacked structures 10, 12 as shown in FIG. The method of patterning includes a lithography process. The stacked structures 10 and 12 each include staggered stacked conductive stripes 14 and insulating stripes 16.

Referring to FIG. 3, dielectric elements 18 are formed on stacked structures 10 and 12. For example, dielectric element 18 has a multilayer structure including, for example, dielectric layers 20, 22, 24. In one embodiment, the dielectric layer 20 is tantalum oxide, the dielectric layer 22 is tantalum nitride, and the dielectric layer 24 is tantalum oxide. In other embodiments, dielectric element 18 is a single layer of dielectric material (not shown), including tantalum nitride or tantalum oxide such as hafnium oxide or hafnium oxynitride.

Referring to FIG. 4, a conductive layer 26 is formed on the dielectric member 18. Conductive layer 26 includes polysilicon. Conductive layer 26 can also include a metal. A patterned mask layer 28 is formed over the conductive layer 26 and portions of the conductive layer 26 that are not masked by the patterned mask layer 28 are removed to form conductive lines 32, 34, 36 as shown in FIG. The method of patterning includes, for example, a lithography process. In an embodiment, the etch process has a suitable etch selectivity for the conductive layer 26 (eg, polysilicon) (FIG. 4) and the dielectric component 18 (eg, the ONO structure), thereby etching the conductive layer 26 without etching. Electrical component 18.

Referring to FIG. 5, the conductive lines 32, 34, 36 are disposed on the side surfaces 60, 62, 64, 66 of the stacked structures 10, 12 and the upper surfaces 50, 52. The extending direction of the conductive lines 32, 34, 36 (extending in the X direction) is perpendicular to the extending direction of the stacked structures 10, 12 (extending in the Z direction). The patterned mask layer 28 is removed.

Referring to FIG. 6, a dielectric layer 38 is formed on the dielectric member 18 and the conductive lines 32, 34, 36. For example, the dielectric layer 38 includes ruthenium oxide which can be formed by vapor phase deposition of methane and ozone or a mixed gas of tetraethoxy decane (TEOS) and ozone/oxygen. Dielectric layer 38 has a flat upper surface 40. In an embodiment, the upper surface 40 is aligned or higher than the upper surface 42 of the dielectric element 18 and the upper surfaces 44, 46, 48 of the conductive lines 32, 34, 36 on the upper surfaces 50, 52 of the stacked structures 10, 12. . The dielectric layer 38 having a flat upper surface 40 can aid in a subsequent lithography process such as an exposure step.

Referring to FIG. 7, a patterned mask layer 54 is formed on the dielectric layer 38. The method of patterning includes, for example, a lithography process. The patterned mask layer 54 has an opening 56 that exposes the dielectric layer 38 on the conductive line 32. The exposed dielectric layer 38 and the conductive lines 32 are removed from the opening 56 until the upper surface 42 of the dielectric element 18 is exposed, and the conductive lines 32 are disposed on opposite sides 60, 62, 64, 66 of the stacked structures 10, 12. Partially to form conductive islands 70, 72, 74 as shown in FIG. In an embodiment, the etch process has suitable etch selectivity for conductive lines 32 (eg, polysilicon) (FIG. 7), dielectric element 18 (eg, ONO structure), and dielectric layer 38 (eg, TEOS oxide), thus Dielectric layer 38 and conductive line 32 are etched without etching dielectric element 18. In other words, the conductive islands 70, 72, 74 are formed in a self-aligned manner. Therefore, the manufacturing method is simple. In other embodiments, the conductive lines 34, 36 are also suitably patterned to form other conductive islands (not shown), depending on the design requirements. The patterned mask layer 54 is removed (Fig. 7).

The dielectric layer 38 in Fig. 8 is not shown in Fig. 9. Referring to Figure 9, the conductive islands 70, 72 on the opposite sides 60, 62 of the stacked structure 10 are separated from one another. In addition, conductive islands 72, 74 on opposite sides 64, 66 of stack structure 12 are separated from one another. The conductive islands 70, 72, 74 are arranged in a direction (X direction) perpendicular to the extending direction of the stacked structures 10, 12 (extending in the Z direction).

Referring to FIG. 9, dielectric element 18 is between stack structures 10, 12 and conductive lines 34, 36 and between stack structures 10, 12 and conductive islands 70, 72, 74. In an embodiment, the conductive lines 34, 36 and the conductive islands 70, 72, 74 have a first conductivity type. The conductive stripes 14 have a second conductivity type. The first conductivity type is opposite to the second conductivity type. For example, the first conductivity type is an n-type conductivity type, and the second conductivity type is a p-type conductivity type. The conductive islands 70, 72, 74 may be constructed of a single material or a composite material.

The semiconductor structure fabricated according to the method of the embodiment may have a fine size. For example, in an embodiment, the half pitch of the word line (WL) is 37.5 nm. The etch critical dimension (ECD) of the word line (WL) is approximately 25 nm. The critical dimension of the bit line (BL) is about 30 nm. The channel length of the tandem select line (SSL) and the ground select line (GSL) is approximately equal to 0.25 um, which is sufficient to well avoid the occurrence of a punch through effect to satisfy program-inhibition. demand. In addition, the independently controlled dual gate (IDG) decoded three dimensional vertical gate device in the embodiment has an array layout similar to that of a general NAND type device. Since the independently controlled dual gate series selection lines are self-aligned and the pitch can be miniaturized, no additional area is required.

Figure 10 is a perspective view of a semiconductor structure of an embodiment. The semiconductor structure shown in Fig. 10 is different from the semiconductor structure shown in Fig. 9 in that the semiconductor structure shown in Fig. 10 has a BE-SONOS element (refer to US Pat. No. 7,529,137). Referring to FIG. 10, the dielectric member 218 has a multilayer structure including dielectric layers 217, 219, 221, 222, and 224. In an embodiment, the thickness of the dielectric layers 217, 219, 221 is less than the dielectric layers 222, 224. The dielectric layers 217, 221, 224 may be yttrium oxide. Dielectric layers 219, 222 can be tantalum nitride.

11 is a perspective view of a semiconductor structure in an embodiment. FIG. 11 does not show the dielectric layer in the semiconductor structure, such as the dielectric layer 38 shown in FIG. 8, nor the insulating stripe 116 is interposed between the conductive islands 110, 112 and the conductive lines 134, 135, and 136. The portion, in other words, the insulating strips 116 are such that the conductive strips 114 are continuous.

Referring to FIG. 11, in the embodiment, the semiconductor structure is a 3D vertical gate memory device, and includes, for example, a NAND type flash memory or an anti-fuse memory. Metal telluride layers 184, 185, 186 may be formed on conductive lines 134, 135, 136. The metal telluride layers 184, 185, 186 include, for example, tungsten telluride, cobalt telluride, and titanium telluride. Different levels of conductive strips 114 are respectively used as bit lines (BL) of different memory planes. For example, the lowermost conductive strips 114 are defined as first layer bit lines (1 ^st layer BL), and different rows of 1 ^st layer BL common lines electrically connected to the conductive layer 171, conductive layer 171 may be a layer of a first conductive layer (1 ^st layer cO). The lowermost conductive strips 114 are then sequentially defined as the second layer of bit lines (2 ^nd layer BL), the third layer of bit lines (3 ^rd layer BL), and the fourth layer of bit lines. (4 ^th layer BL). The different rows of 2 ^nd layer BL are electrically connected to the conductive layer 173 in common. Different rows of 3 ^rd layer BL lines are electrically connected to the conductive layer 175 in common. 4 ^th layer BL lines of the different rows together electrically connected to the conductive layer 177. The conductive layer 173, conductive layer 175, conductive layer 177 may be respectively a second level conductive layer (2 ^nd layer CO), a third conductive layers (3 ^rd layer CO), the fourth conductive layers (4 ^th layer CO). The conductive layer 171, the conductive layer 173, the conductive layer 175, and the conductive layer 177 are electrically connected to the different rows of the conductive plugs 192 and the conductive layer 193. The upper conductive stripes and conductive layers (not shown) are similar. The conductive layer 171, the conductive layer 173, the conductive layer 175, the conductive layer 177, the conductive plug 192 and the conductive layer 193 may have a double pitch to obtain a better process window.

The conductive strips 114 are coupled to a common source line 190. A common source line 190 can include polysilicon. Conductive line 135 acts as a ground select line (GSL). Conductive lines 134, 136 are used as word lines (WL). For example, the conductive line 136 closest to the conductive line 135 (GSL) among the plurality of conductive lines is defined as WL ₀ , and then the conductive line 134 away from the conductive line 135 (GSL) is defined as the word line WL ₁ . Conductive lines (not shown) further away from the conductive line 135 (GSL) are defined as word lines WL ₂ , WL ₃ ..., and so on.

Conductive islands 170, 172, and 174 are used as a serial selection line (SSL). Conductive islands 170, 172, 174 are each independently electrically coupled to a different set of conductive plugs 194, conductive layer 195, conductive plugs 196 and conductive layer 197, and to a decoding circuit (parallel to the word lines). For example, the conductive islands 170, 172, and 174 in Fig. 11 are defined as SSL ₀ , SSL ₁ , SSL ₂ , and so on.

The material of the conductive plug 192, the conductive layer 193, the conductive plug 194, the conductive layer 195, the conductive plug 196 and the conductive layer 197 may be metal. For example, the conductive layer 195 is a first metal line (ML1), the conductive layer 197 is a second metal line (ML2), the conductive layer 193 is a third metal line (ML3), and so on. Conductive plug 196 can also be represented by symbol V11.

Referring to FIG. 11, the conductive islands 170, 172 and 174 which are separated from each other can be operated independently, for example, different bias voltages can be respectively applied, so that the conductive stripes 114 (BL) in the different stacked structures 110 and 112 are separated. Selected or not selected. Therefore, the method of operation of the semiconductor structure has a high variability in denaturation. The semiconductor structure is a three-dimensional vertical gate (VG) device that independently controls an independently controlled double gate (IDG) decoding. In one embodiment, the memory device is a double-gate TFT BE-SONOS device.

In one embodiment, for example, when the conductive strip 114 (BL) between the conductive island 170 (SSL0) and the conductive island 172 (SSL1) is turned on, a positive voltage (V _SSL ) is applied. The conductive islands 170 and the conductive islands 172 are used to achieve the purpose of turning on the conductive stripes 114. When the conductive stripe 114 between the conductive island 172 (SSL1) and the conductive island 174 (SSL2) is not selected, a positive voltage is applied to the conductive island 172, and a negative voltage (V _inhibit ) is applied to the conductive _layer . Island 174 came to the end of the closure. The positive voltage described above can be approximately +2 V to +4 V, and the negative voltage can be approximately -2 V to -8 V. For example, in one embodiment, the positive voltage is about +3.3 V and the negative voltage is about -3.3 V. In another embodiment, the positive voltage is about +2.5 V and the negative voltage is about -7 V. In yet another embodiment, the positive voltage is about +2 V and the negative voltage is about -7 V. The remote SSL is turned off by applying 0V (or ground).

FIG. 12 is a top plan view showing a semiconductor structure having eight conductive stripes BL (bit lines) in an embodiment. Different levels of conductive strips BL are electrically connected to eight sets of stepped conductive structures, respectively. The stepped conductive structure may be composed of a conductive layer 171, a conductive plug 192 and a conductive layer 193 as shown in FIG. 11, or a conductive layer 173, a conductive plug 192 and a conductive layer 193, and so on. As shown in FIG. 12, the third metal wires ML3 of the different sets of stepped conductive structures are electrically connected to the contact pads 341, respectively. In this example, the semiconductor structure has sixty-four word lines WL1, WL2 ... WL63 and WL64.

Referring to FIG. 12, the semiconductor structure of this example has sixteen serial selection lines (conductive islands) SSL0, SSL1, SSL2, ..., SSL14 and SSL15, which are respectively electrically connected to different groups (sixteen groups). The metal line ML1, the conductive plug V11 and the second metal line ML2. The second metal line ML2 is electrically connected to the serial selection line decoding circuit. In an embodiment, another period of the semiconductor structure may be repeatedly extended in the X direction, and two adjacent periodic semiconductor structures may share one conductive island SSL0.

Figure 13 is a diagram showing the Id-V _SSL curve of a semiconductor structure having a BL of ECD of about 30 nm, wherein one gate is V _SSL and the remaining gates are V _inhibitor of about -1 V to about -7 V (the curve of the right side is represented) More negative). It is found from Fig. 13 that the higher the V _inhibitor is, the higher the threshold voltage (Vt) will be. In addition, when the V _inhibit used to turn off the SSL channel is about -1V to -7V, the V _SSL used to turn on the SSL channel is preferably greater than about +2V. For example, V _SSL is +2V and V _inhibit is -7V to provide the switch (ON/OFF) requirement for the selected/unselected BL channel.

Figure 14 shows the Vt-V _inhibition curve of the semiconductor structure. From Fig. 14, it is found that the smaller the size of the BL ECD, the larger the Vt, which is presumably due to the fact that the device having a small width is more likely to cause depletion. The TCAD simulation curve is in accordance with the experimental results.

The semiconductor structure of the examples not only provides read inhibition but also provides program inhibit. Figure 15 shows the stylized suppression characteristics of the semiconductor structure. Among them, _{SSL is} applied to SSL0 and SSL1 by +2V, and BL is selected between SSL0 and SSL1, and the selected BL is 0V. The other SSL applies a 4.7V V _inhibit to turn off the unselected BL, and the unselected BL is +3.3V. In the stylized stepping pulse (ISPP) process, one of the programming times is 50 microseconds (usec), and the channel-gate voltage (V _PASS ) is 10V. This result shows that the semiconductor structure has excellent stabilizing characteristics.

Fig. 16A shows that the semiconductor structure has a small program disturb even if the program time of the ISPP is increased to 100 usec each time. This presumes that when the channel potential is increased (about 8 V), the semiconductor structure has good punch-through immunity and can suppress the occurrence of leakage. FIG. 16B shows that when V _SSL is + 2V, V _inhibit greater than -5V to get good inhibitory effect. Figure 16C shows that when V _inhibit is -7V, V _SSL is less than 3V to obtain a good suppression effect.

Figure 17 shows the Id-Vg characteristics during the process of erasing a 3Xnm 3DVG TFT device. Among them, the single-level memory unit (SLC) operates a checkerboard (CKB) clock signal. The device is a NAND (64-WL NAND) with two levels of BL and sixty-four WLs. Idsat can be greater than 150nA. Vt can be defined from 20 nA to 40 nA. Fig. 17 shows that the semiconductor structure has excellent subcritical characteristics due to the good gate control capability of the narrow gate device having a narrow width. 64-WL NAND's Idsat provides proper memory sensing at 150nA or more.

Figure 18 shows that when the BL of a 3Xnm 3DVG TFT device has a narrow ECD, the system has a good subthreshold slope (SS) distribution, and the SS is mainly between 200 mV/decade and 500 mV/decade. And the distribution is narrow, which is due to the small polycrystalline carcass capturing volume.

Figure 19 shows the Vt distribution of the 3Xnm 3DVG TFT device in the stylized state after initial, erasing and stylization with SLC CKB. After stylizing the interference bias, the memory window is properly separated, which shows that the device of the embodiment has reasonably good performance.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

2‧‧‧Base

4‧‧‧ Conductive layer

6‧‧‧Insulation

8‧‧‧ buried oxide layer

10,12,110,112‧‧‧Stack structure

14, 114‧‧‧ conductive stripes

16, 116‧‧‧Insulation stripes

18, 218‧‧‧ dielectric components

20, 22, 24, 38, 217, 219, 221, 222, 224‧‧ dielectric layers

26‧‧‧ Conductive layer

28‧‧‧mask layer

32, 34, 36, 134, 135, 136‧‧‧ conductive lines

40‧‧‧ Upper surface of the dielectric layer

42‧‧‧ Upper surface of the dielectric component

44, 46, 48‧‧‧ upper surface of the conductive wire

50, 52‧‧‧ upper surface of the stacked structure

54‧‧‧ patterned mask layer

56‧‧‧ openings

60, 62, 64, 66‧‧‧ side of the stacking structure

70, 72, 74, 170, 172, 174‧‧ conductive islands

171, 173, 175, 177‧‧‧ conductive layers

184, 185, 186‧‧‧ metal telluride layers

190‧‧‧Common source line

192, 194, 196‧‧‧ conductive plugs

193, 195, 197‧‧‧ conductive layer

341‧‧‧Contact pads

GSL‧‧‧ Grounding selection line

WL1, WL2, WL63, WL64‧‧‧ character lines

V11‧‧‧ conductive plug

ML1‧‧‧first metal wire

ML2‧‧‧second metal wire

ML3‧‧‧ third metal wire

SSL0, SSL1, SSL2, SSL14, SSL15‧‧‧ string selection line

1 to 9 illustrate a manufacturing embodiment of a semiconductor structure.

Figure 10 is a perspective view of a semiconductor structure in an embodiment.

11 is a perspective view of a semiconductor structure of an embodiment.

Figure 12 is a top plan view showing a semiconductor structure in an embodiment.

Figure 13 shows the Id-V _SSL curve of the semiconductor structure.

Figure 14 shows the Vt-V _inhibition curve of the semiconductor structure.

Figure 15 shows the stylized suppression characteristics of the semiconductor structure.

Figure 16A shows the Vt - each stylized pulse curve of the semiconductor structure.

Figure 16B shows the Vt-V _inhibition curve of the semiconductor structure.

Figure 16C shows the Vt-V _SSL curve of the semiconductor structure.

Figure 17 shows the Id-Vg curve of the semiconductor structure.

Figure 18 shows the bit-count-S.S. curve of the semiconductor structure.

Figure 19 shows the number of bits of the semiconductor structure - Vt curve.

110, 112‧‧‧Stack structure

114‧‧‧ Conductive stripes

116‧‧‧Insulation stripe

134, 135, 136‧‧‧ conductive lines

170, 172, 174‧‧ ‧ conductive island

184, 185, 186‧‧‧ metal telluride layers

190‧‧‧Common source line

Claims (22)

A method of operating a semiconductor structure, wherein
The semiconductor structure includes:
a substrate;
a first stacked structure formed on the substrate, wherein the first stacked structure comprises a first conductive strip and a first insulating strip alternately stacked, the first conductive strip being separated by the first insulating strip;
a dielectric component formed on the first stacked structure;
a conductive line formed on the dielectric element, the conductive line extending in a direction perpendicular to the extending direction of the first stacked structure; and a first conductive island and a second conductive island formed on the dielectric element The first conductive island on the opposite side of the first stacked structure and the second conductive island are separated from each other,
The method of operation of the semiconductor structure includes:
A first voltage is applied to the first conductive island and a second voltage is applied to the second conductive island. The method of operating a semiconductor structure according to claim 1, wherein the first voltage and the second voltage are both positively biased. The method of operating a semiconductor structure according to claim 2, wherein the method of operation is such that the first conductive strip of the first stacked structure is selected. The method of operating a semiconductor structure of claim 3, wherein the selected first conductive strip is turned on. The method of operating a semiconductor structure of claim 1, wherein the first voltage is a positive bias and the second voltage is a negative bias. The method of operating a semiconductor structure according to claim 5, wherein the method of operation is such that the first conductive stripe of the first stacked structure is unselected. The method of operating a semiconductor structure of claim 6, wherein the unselected first conductive strip is closed. The method of operating a semiconductor structure according to claim 1, wherein the semiconductor structure further comprises:
a second stack structure formed on the substrate, wherein the second stack structure comprises a second conductive strip and a second insulating strip staggered, and the second conductive strip is separated by the second insulating strip, wherein a dielectric element is formed on the second stacked structure, the conductive line extends in a direction perpendicular to the extending direction of the second stacked structure; and a third conductive island is formed on the dielectric element, wherein the second The second conductive island on the opposite side of the stacked structure and the third conductive island are separated from each other,
The method of operating the semiconductor structure further includes applying a third voltage to the third conductive island. The method of operating a semiconductor structure according to claim 8, wherein the first voltage and the second voltage are both positively biased, and the third voltage is a negative bias. The method of operating a semiconductor structure according to claim 9 wherein the first conductive strip of the first stacked structure is selected such that the second conductive strip of the second stacked structure is not be chosen. A method of fabricating a semiconductor structure, comprising:
Forming a stacked structure on a substrate, wherein the stacked structure includes a plurality of conductive stripes and a plurality of insulating stripes, and the conductive stripes are separated by the insulating stripes;
Forming a dielectric component on the stacked structure;
Forming a plurality of conductive lines on the dielectric element, wherein the conductive lines extend in a direction perpendicular to an extending direction of the stacked structure; and forming a plurality of conductive islands on the dielectric element, wherein the stacked structure is located The conductive islands on opposite sides of each other are separated from each other. The method for fabricating a semiconductor structure according to claim 11, wherein the conductive lines are disposed on a side surface and an upper surface of the stacked structure, and the method for forming the conductive islands comprises:
A portion of the conductive line on the upper surface of the dielectric member on the upper surface of the stacked structure is removed, and a portion of the conductive line on opposite sides of the stacked structure is left to form the conductive islands. The method for fabricating a semiconductor structure according to claim 12, wherein the method for forming the conductive islands further comprises:
Forming a dielectric layer on the dielectric element on the stacked structure and the conductive line, wherein the dielectric layer has a flat upper surface;
Forming a patterned mask layer on the dielectric layer, wherein the patterned mask layer has an opening, and in the step of removing the conductive line, removing the conductive line exposed by the opening, Until the upper surface of the dielectric element on the upper surface of the stacked structure is exposed; and the patterned mask layer is removed. The method of fabricating a semiconductor structure according to claim 13, wherein the flat upper surface of the dielectric layer is aligned or higher than an upper surface of the dielectric member and an upper surface of the conductive line on the stacked structure. . The method of fabricating a semiconductor structure according to claim 11, wherein the conductive island between the two adjacent ones of the stacked structures has a single material. The method of fabricating a semiconductor structure according to claim 11, wherein the conductive island between the two adjacent ones of the stacked structures has a composite material. The method of manufacturing the semiconductor structure of claim 11, wherein the conductive line and the conductive island have a first conductivity type, the conductive strip has a second conductivity type, the first conductivity type and the second The conductivity type is reversed. A semiconductor structure comprising:
a substrate;
a stacked structure formed on the substrate, wherein the stacked structure comprises staggered stacked conductive stripes and insulating stripes, the conductive stripes being separated by the insulating stripes;
a dielectric component formed on the stacked structure;
a conductive line formed on the dielectric element, the conductive line extending in a direction perpendicular to an extending direction of the stacked structure; and a plurality of conductive islands formed on the dielectric element, wherein the single one of the stacked structures is The conductive islands on opposite sides are separated from one another. The semiconductor structure of claim 18, wherein the conductive islands are arranged in a direction perpendicular to an extending direction of the stacked structure. The semiconductor structure of claim 18, wherein the conductive island between two adjacent ones of the stacked structures has a single material. The semiconductor structure of claim 18, wherein the conductive island between the two adjacent ones of the stacked structures has a composite material. The semiconductor structure of claim 18, wherein the conductive line and the conductive island have a first conductivity type, the conductive strip has a second conductivity type, and the first conductivity type and the second conductivity type in contrast.