TWI555151B - Semiconductor structure - Google Patents

Description

Semiconductor structure

This invention relates to a semiconductor structure, and more particularly to a memory structure.

In recent years, the structure of semiconductor elements has been constantly changing, and the memory storage capacity of the elements has also been increasing. Memory devices are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. In response to this demand, it is required to manufacture a memory device having a high component density and a small size.

Therefore, designers are all committed to developing a three-dimensional memory device that not only has many stacked planes but also achieves higher memory storage capacity, has a smaller size, and has good characteristics and stability.

According to an embodiment, a semiconductor structure including a conductive strip, a conductive layer, a first dielectric layer, and a second dielectric layer is disclosed. The first dielectric layer is interposed between the staggered conductive stripes and the conductive layer. The second dielectric layer is different from the first dielectric layer and adjacent to the first dielectric layer at different positions on the same sidewall of the conductive stripe Set it up.

In accordance with another embodiment, a semiconductor structure is disclosed that includes a conductive layer, a first dielectric layer, and a conductive strip. The conductive stripes are separated from the conductive layer staggered with the conductive stripes by the first dielectric layer. The conductive stripe includes a first conductive portion, a second conductive portion, and a curved surface between the first conductive portion and the second conductive portion.

According to still another embodiment, a semiconductor structure including a conductive layer, a conductive strip, and a first dielectric layer is disclosed. The conductive layer has a first sidewall and a second sidewall, and a third sidewall between the first sidewall and the second sidewall. The first dielectric layer separates the staggered conductive strip conductive layers. The thickness of the first dielectric layer on the first sidewall and the second sidewall of the conductive layer is greater than the thickness on the third sidewall.

102‧‧‧Bottom insulation

104‧‧‧Electrical film

106‧‧‧Dielectric film

108‧‧‧Source contact plug

110‧‧‧First perforation

112‧‧‧Perforation

114‧‧‧Perforation

116‧‧‧ Conductive stripes

118‧‧‧Electrically connected

120‧‧‧conductive plate

122‧‧‧First dielectric layer

124‧‧‧ upper surface

126‧‧‧ surface

127‧‧‧ 曲 Surface

128‧‧‧ side wall

130‧‧‧ Conductive layer

132‧‧‧mask layer

134A, 134B‧‧‧ second perforation

136‧‧‧ tuning fork piercing

138‧‧‧ Conductive layer

140‧‧‧ striped section

142‧‧‧Second dielectric layer

144‧‧‧ first side wall

146‧‧‧ second side wall

148‧‧‧ side wall

149‧‧‧ surface

150‧‧‧ side wall

152‧‧‧First conductive part

154‧‧‧Second conductive part

156‧‧‧ third side wall

158‧‧‧mask layer

160‧‧‧ side wall

162‧‧‧ side wall

164‧‧‧ side wall

166‧‧‧ openings

168‧‧‧Electrical contact

T1, T2, T3‧‧‧ thickness

D1, D2, D3‧‧‧ size

S1‧‧‧first spacing

S2‧‧‧Second spacing

S3‧‧‧Second spacing

FIGS. 1A through 11A illustrate a manufacturing process of a semiconductor structure in accordance with an embodiment.

12 is a top view of a conductive structure, conductive stripes, and a first dielectric layer of a semiconductor structure in accordance with an embodiment.

FIGS. 1A through 11A illustrate a manufacturing process of a semiconductor structure in accordance with an embodiment.

Please refer to FIG. 1A and FIG. 1B, which respectively illustrate the stacked structure. The above diagram and section view. The stacked structure includes a conductive film 104 and a dielectric film 106 which are alternately formed on the bottom insulating layer 102. In the embodiment, the topmost layer of the stacked structure is the dielectric film 106, and for the sake of clarity of the disclosure, the figure shows the area of the stacked structure with the conductive film 104, which will not be described later.

The bottom insulating layer 102 may be formed on a semiconductor substrate (not shown). The semiconductor substrate can include a germanium substrate, an insulating layer overlying germanium (SOI), or other suitable substrate material. In one embodiment, the bottom insulating layer 102 and the dielectric film 106 are oxides such as hafnium oxide. However, the disclosure is not limited to this. In other embodiments, the bottom insulating layer 102 and the dielectric film 106 may respectively comprise a single layer structure or a multilayer structure of oxides, nitrides, or oxynitrides, such as hafnium oxide, tantalum nitride, hafnium oxynitride, or other suitable Dielectric material. Conductive film 104 can comprise polysilicon or other suitable electrically conductive material.

Referring to FIG. 1A, a source contact plug 108 is formed in the stacked structure, which is electrically connected to the conductive film 104 of different levels. The method of forming the source contact plug 108 may include, for example, an etching process in which a via is formed in the stacked structure and filled with a conductive material such as polysilicon or metal into the via.

Referring to FIGS. 2A and 2B, a first through hole 110, a through hole 112, and a through hole 114 are formed in the stacked structure to pattern the stacked structure. The patterned stacked structure has a plurality of stripe stacks (which include conductive strips 116) extending continuously in the Z direction and separated from each other, and a number extending in the X direction and adjoining between the stripe stacks (or conductive strips 116) Connection stacks (which include conductive connections 118). The stripe stack (conductive strips 116) may also abut the board stack (which includes the conductive strips 120). In one embodiment, for example, the size of the connection stack (or conductive connection 118) in the Z-axis direction D1 is 0.05 μm, and the size D2 of the board stack (or the conductive board 120) is 0.5 μm.

Referring to FIGS. 3A-3C, a first dielectric layer 122 may be formed on the stacked structure exposed by the first via 110 and on the upper surface 124 of the stacked structure. The first dielectric layer 122 may include an ONO structure, an ONONO structure, an ONONONO structure, or a material layer composed of a tunneling material/trapping material/blocking material, applied to the gate (NAND) storage material. For the sake of clarity, the first dielectric layer 122 only shows the portion located in the first through hole 110 in FIGS. 3A and 3C. Please refer to FIG. 3C, which shows an enlarged view of the area near the four first perforations 110. In an embodiment, the first vias 110 are formed by lithography using an etching process. The elongated first through hole 110, which is formed to extend in the Z direction, has a curved surface 127 at a corner between the short side wall 126 and the long side wall 128, which contour causes the subsequent deposition of the first dielectric layer 122 due to the deposition rate. The difference is that the thickness T1 on the curved surface 127 is greater than the thickness T2 and the thickness T3 which are substantially equal on the short side wall 126 and the long side wall 128 of the first through hole 110.

Referring to FIGS. 4A-4C, the conductive layer 130 is filled into the first via 110 and formed on the first dielectric layer 122 on the upper surface 124 of the stacked structure. Conductive layer 130 can comprise polysilicon, or other suitable material. For clarity of the disclosure, the conductive layer 130 depicts only portions of the first via 110 in Figures 4A and 4C, but does not show portions of the upper surface 124 of the stacked structure.

Referring to FIGS. 5A-5C, a patterned mask layer 132 is formed, for example, on the conductive layer 130.

Referring to FIGS. 6A and 6B, the second through holes 134A, 134B of the mask layer 132 and the tuning fork shaped through holes 136 are transferred downward to the conductive layer 130, the first dielectric layer 122, and the stacked structure. In one embodiment, the transfer process is performed using an etching process having a low etching selectivity ratio to the conductive layer 130, the first dielectric layer 122, and the stacked structure (including the material of the conductive film 104 and the dielectric film 106 shown in FIG. 1B). step.

Referring to FIGS. 7A-7C, after the mask layer 132 (FIG. 6A and FIG. 6B) is removed, the portion left by the conductive layer 130 includes a conductive layer 138 extending in the Z direction and separated from each other. And a stripe portion 140 that is adjacent between the conductive layers 138, wherein the stripe portion 140 overlaps the underlying stripe stack (conductive strips 116). For clarity of illustration, Figure 7C does not illustrate the portion of conductive layer 138 that is on top surface 124 of the stacked structure.

The second dielectric layer 142 is filled into the second vias 134A, 134B and the tuning fork shaped vias 136. In an embodiment, the first dielectric layer 122 is different from the second dielectric layer 142. For example, the first dielectric layer 122 is a multilayer dielectric structure, such as an oxide-nitride-oxide (ONO), oxide-nitride-oxide-nitride-oxide (ONONO) structure, or A layer of material consisting of a tunneling material/trapping material/blocking material is applied to the NAND storage material. The second dielectric layer 142 is a single layer dielectric structure, such as a single layer oxide. However, the disclosure is not limited thereto, and different dielectric layers may also refer to a single dielectric film having different materials, or a different number of multilayer dielectric structures. The dielectric layer can also include other suitable dielectric materials.

Please refer to FIG. 7C, which shows a conductive film step of the stacked structure. Layer, an enlarged view of the area adjacent to the four first perforations 110. The process of transferring the second vias 134A removes the conductive connections 118 (FIG. 5A) that are electrically connected to the conductive stripes 116. Therefore, the conductive stripes 116 left by this step are electrically isolated from each other. The second via 134B removes a portion of the conductive layer 138 in the first via 110, thereby dividing the conductive layer 138 into a plurality of discrete segments.

Referring to FIG. 7C, for example, the etching process of the second via 134B is desirably stopped at the inner portion of the first dielectric layer 122, such as an oxide-nitride-oxide-nitride-oxide (ONONO). The inner layer of ONO. In some cases, the etch process etches through the ONONO structure. Thus, in an embodiment, the dimension D3 (width in the X direction) of the second via 134B is substantially aligned, or exceeds the first sidewall 144 and the second sidewall 146 of the conductive layer 138 in the first via 110, or may exceed The long side wall 128 of the first perforation 110.

In some embodiments, the lithographic mask has the same contour as the pattern of the second perforation 134A and the second perforation 134B, so that the non-selective etching process can form the second perforation 134A and the second perforation having substantially the same contour. 134B.

Therefore, in one embodiment, the sidewalls 148, 150 of the second via 134A are substantially aligned with the first sidewall 144, the second sidewall 146 of the conductive layer 138, or the first sidewall 144 and the second sidewall 146, respectively. The extent to which the long side walls 128 of the first perforations 110 are aligned is reached. This causes the portion of the conductive strip 116 adjacent the location of the conductive connection 118 to form a second conductive portion 154 that is wider than the first conductive portion 152, that is, the first conductive portion 152 between the first vias 110 is a narrower conductive portion. The second conductive portion 154 between the second vias 134A is a wider conductive portion as shown in FIG. In this example, the remaining conductive strips 116 retain the curved surface 127, and the thicker corner portions of the first dielectric layer 122 on the curved surface 127 will remain on the surface 149 of the second via 134A. The first conductive portion 152 and the second conductive portion 154 are alternately arranged toward the extending direction of the conductive strips 116.

In another embodiment, the second perforations 134A are formed with their sidewalls 148, 150 substantially aligned with the long sidewalls 128 of the first perforations 110. This causes the conductive strips 116 to have substantially equal widths of the first conductive portion 152 and the second conductive portion 154 (not shown). In this example, the remaining conductive strips 116 have a curved surface 127, and the thicker corner portions of the first dielectric layer 122 on the curved surface 127 will remain on the surface 149 of the second via 134A.

In still another embodiment, the formed second perforations 134A have sidewalls 148, 150 that extend beyond the long sidewalls 128 of the first perforations 110. This causes the first conductive portion 152 of the conductive strip 116 to be narrower than the second conductive portion 154 (not shown), that is, the first conductive portion 152 is a narrower conductive portion and the second conductive portion 154 is a wider conductive portion. In this example, the remaining conductive strips 116 have a curved surface 127, and the thicker corner portions of the first dielectric layer 122 on the curved surface 127 will remain on the surface 149 of the second via 134A.

In one embodiment, the second via 134A corresponding to the location of the conductive connection 118 also exposes the first dielectric layer 122 of the conductive layer 138 adjacent the third sidewall 156 between the first sidewall 144 and the second sidewall 146. The second dielectric layer 142 filled therein can be adjacent to the exposed first dielectric layer 122 to form a continuous direction in the Z direction. The dielectric elements are extended and conductive strips 116 are defined. In other embodiments, the second via 134A process for forming the location of the corresponding conductive connection 118 removes a portion of the third sidewall 156 of the conductive layer 138 that is thinner than the first dielectric layer 122 and leaves the first portion. The dielectric layer 122 is located on a thicker corner portion of the curved surface 127, and the second dielectric layer 142 filled in the second via 134A can still form a conductive strip 116 with the first dielectric layer 122. Dielectric element. Removing some or all of the first dielectric layer 122 on the third sidewall 156 of the conductive layer 138 also causes the first dielectric layer 122 to be on the first sidewall 144 and the second sidewall 146 of the conductive layer 138. Greater than the thickness T2 located on the third sidewall 156. For example, when the first dielectric layer 122 is completely removed, the thickness T2 is zero.

There is no first dielectric layer 122 between the second conductive portion 154 and the second dielectric layer 142 in the second via 134A. The first dielectric layer 122 is located between the first conductive portion 152 and the second dielectric layer 142 of the second via 134B and between the first conductive portion 152 and the conductive layer 138.

In other embodiments, the pattern of the lithography mask corresponding to the positions of the second through holes 134A and the second through holes 134B may have different contours according to other designs, or may be combined with other characteristics (eg, isotropic, non-isotropic, etch selective, etc.). The etching process is performed to form a second via 134A and a second via 134B in a desired configuration.

Referring to FIG. 8A, a patterned mask layer 158 is formed, for example, on the structure shown in FIG.

Referring to FIGS. 9A to 9C, the portion of the conductive layer 130 exposed by the mask layer 158 is removed. In an embodiment, the etching step removes the conductive layer 138 The strip portions 140 (FIG. 7A) are electrically connected, thereby separating the conductive layers 138 and electrically isolating from each other. The mask layer 158 is then removed.

Referring to FIG. 9C, the first dielectric layer 122 is interposed or adjacent between the staggered conductive layer 138 and the first conductive portion 152 of the conductive strip 116. Alternatively, the first conductive portion 152 of the conductive strip 116 is adjacent between the first dielectric layer 122. The second dielectric layer 142 is interposed between two adjacent conductive layers 138 extending in the X direction and is adjacent to, or adjacent to, adjacent two adjacent second conductive portions 154 of the conductive stripes 116. Alternatively, the second conductive portion 154 of the conductive strip 116 is adjacent between the second dielectric layer 142. The first dielectric layers 122 at different positions in the Z direction are separated from each other by the second dielectric layer 142. The first dielectric layer 122 and the second dielectric layer 142 abut on the same sidewall of the conductive strip 116 (which may include sidewalls 160 and sidewalls 162 that are connected at different locations on the X-axis, and different locations of the curved sidewalls 164 therebetween) on.

Referring to FIGS. 10A and 10B, an etch process is performed with lithography to form openings 166 of different depths in the stack of plates, which respectively expose conductive films 104 (or conductive plates 120) of different levels to form a stepped structure. .

Referring to Figure 11A, a conductive contact 168 is formed.

In an embodiment, the semiconductor structure is a three-dimensional stacked vertical gate memory device, conductive stripes 116 are used as bit lines, and conductive layer 138 is used as word lines. The memory cell is determined by the intersection of the bit line and the word line, and the number may be determined according to actual needs and design, for example, changing the number of layers of the conductive stripe 116 (or bit line) in the stacked structure, or changing the same level. The number of conductive stripes 116 (or bit lines) extending in the Z direction and the number of conductive layers 138 (or word lines) extending in the X direction.

In the above embodiment, as shown in FIG. 9C, a second dielectric layer 142 formed in a first via 110 can divide (or define) two conductive layers 138 extending in the X direction. However, the disclosure is not limited to this. For example, five mutually separated second dielectric layers 142 (which are located in the second vias 134B) may be formed in one first via 110, thereby being at a second location corresponding to the conductive connections 118 (or connected stacks) Six conductive layers 138 are defined between the dielectric layer 142 (which is located in the second via 134A) as shown in FIG. The second conductive portion 154 of the conductive strip 116 has six conductive layers 138 adjacent to each other.

In the embodiment, the connection stack has a specific dimension D1 (width) in the Z-axis direction (refer to FIG. 2A, which may be limited by the process limit or determined by the support effect thereof). The second via 134A (FIG. 9C) needs to remove the connection stack (or conductive connection 118), or remove the portion of the first dielectric layer 122 adjacent to the connection stack (or conductive connection 118), or even move Except for the curved portion of the conductive layer 138 adjacent to the first dielectric layer 122. Therefore, the size of the second through hole 134A in the Z-axis direction may be larger than the second through hole 134B formed by mainly removing the conductive layer 138 in the first through hole 110. This causes the conductive layer 138 (or bit line) to be closest to the first pitch S1 (Fig. 12) between the two of the second conductive portions 154, which may be greater than the other second pitch, such as the second pitch S2 or the second Spacing S3 and so on.

In some comparative examples, the formation of the bit lines is defined by patterning the stacked structure of the conductive film and the dielectric film, and forming a strip-like opening at a time. In other words, the entire side wall is exposed to the opening during the formation of the bit line. However, a stripe stack including a high aspect ratio of the bit line, When both sides are open and are not supported by other components, they are susceptible to bending due to other stresses (such as the liquid in the immersion cleaning step, the liquid filled in the opening, or the stress caused by the immersion and pulling action). ), causing structural damage or even undesired short circuits, reducing product yield.

In an embodiment of the present disclosure, the stripe stack including the conductive strips 116 is formed by multiple patterning vias (including the first vias 110 and the second vias 134A, 134B), the material used to form the conductive strips 116 in the process. Some are supported. For example, after the first perforations 110 are formed, the stripe stack is supported by the stripe stack and the board stack. After forming the second vias 134A, 134B, the stripe stack is supported by the first dielectric layer 122, the second dielectric layer 142, and the conductive layer 138 within the first via 110. Therefore, compared with the comparative example, the embodiment has a relatively stable structural feature, is less prone to deformation, and has high product reliability.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

110‧‧‧First perforation

116‧‧‧ Conductive stripes

122‧‧‧First dielectric layer

134A, 134B‧‧‧ second perforation

138‧‧‧ Conductive layer

142‧‧‧Second dielectric layer

152‧‧‧First conductive part

154‧‧‧Second conductive part

160‧‧‧ side wall

162‧‧‧ side wall

164‧‧‧ side wall

Claims (10)

A semiconductor structure comprising: a conductive strip; a conductive layer; a first dielectric layer interposed between the conductive strips and the conductive layer; and a second dielectric layer different from the first dielectric layer And an electrical layer adjacent to the first dielectric layer at different locations on the same sidewall of the conductive strip. The semiconductor structure of claim 1, comprising a plurality of the conductive stripes and a plurality of conductive layers, wherein the second dielectric layer is between the adjacent two of the conductive stripes, and Between two adjacent ones of the conductive layers. The semiconductor structure of claim 1, wherein the conductive strip has a first conductive portion and a second conductive portion that are different in thickness and adjacent to each other. The first dielectric layer is adjacent to the first conductive layer. In part, the second dielectric layer is adjacent to the second conductive portion. The semiconductor structure of claim 1, wherein the first dielectric layer is a multilayer dielectric structure, and the second dielectric layer is a single layer dielectric structure. The semiconductor structure of claim 1, wherein the first dielectric layer is an oxide-nitride-oxide (ONO) or an oxide-nitride-oxide-nitride-oxide (ONONO) Structure, the second dielectric layer is an oxide. A semiconductor structure comprising: a conductive layer; a first dielectric layer; and a conductive strip separated from the conductive layer by a staggered arrangement of the conductive strips, the conductive stripe comprising a first conductive portion, a second conductive portion, and a curved surface between the first conductive portion and the second conductive portion. The semiconductor structure of claim 6, wherein the first dielectric layer is between the first conductive portion of the conductive strip and the conductive layer, the first conductive portion and the second conductive portion They are alternately arranged in the direction in which the conductive stripes extend. The semiconductor structure of claim 6, wherein the conductive layer is used as a word line, and the word lines have different first and second intervals. A semiconductor structure comprising: a conductive layer having a first sidewall and a second sidewall, and a third sidewall between the first sidewall and the second sidewall; a conductive strip; and a first dielectric layer And an electrically conductive layer, the electrically conductive layer is disposed in a staggered manner, and the first dielectric layer is located on the first sidewall and the second sidewall of the conductive layer to have a thickness greater than a thickness on the third sidewall. The semiconductor structure according to any one of claims 1 to 9, wherein the semiconductor structure is a memory device, the conductive stripe is used as a bit line, and the conductive layer is used as a word line, and the word lines are used. There is a different first spacing and a second spacing between.