TWI646667B - Method for manufacturing three dimensional stacked semiconductor structure and structure manufactured by the same - Google Patents

Abstract

A method of fabricating a three-dimensional stacked semiconductor structure and a structure thereof. In the manufacturing method of the embodiment, a plurality of layers are stacked on top of a substrate, and the multilayer stack includes a plurality of nitride layers and a plurality of polycrystalline germanium layers alternately stacked. A plurality of channel holes are formed perpendicular to the substrate. The multilayer stack is patterned to form a linear pitch between the via holes and perpendicular to the substrate, wherein the linear pitches extend downward to expose sidewalls of the nitride layer and the polysilicon layer. The polysilicon layer is replaced by a plurality of insulating layers having an air gap through a linear pitch, and the nitride layer is replaced by a plurality of conductive layers through a linear pitch.

Description

Method for manufacturing three-dimensional stacked semiconductor structure and structure thereof

The present invention relates to a method of fabricating a three-dimensional stacked semiconductor structure and a structure thereof, and more particularly to a three-dimensional stacked semiconductor structure having an air-gaps in an insulating layer and a method of fabricating the same.

A very important feature of non-volatile memory components is the ability to preserve the integrity of the data state when the memory component loses or removes power. Many different types of non-volatile memory components have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, some three-dimensional stacked NAND (NAND) type flash memory structures have been proposed. However, there are still some problems that need to be solved in the traditional three-dimensional stacked memory structure.

For example, in an array region of a three-dimensional stacked memory structure, the capacitance between the conductive layers of adjacent stacks is too high, and when the array area in the structure is larger or the number of stacks of the desired structure is more The capacitance will be higher. Furthermore, the traditional side The three-dimensional stacked memory structure produced by the method has a problem that the stack is prone to bending or even collapse when the number of layers of the required structure in the structure is large.

The present invention relates to a method of fabricating a three-dimensional stacked semiconductor structure and the resulting structure. According to an embodiment, a plurality of insulating layers and conductive layers having air-gaps are alternately stacked, so that the weight of the formed three-dimensional stacked memory structure can be reduced, and the capacitance between adjacent conductive layers can be reduced.

According to an embodiment, a method for fabricating a three-dimensional stacked semiconductor structure is provided, comprising: forming a multi-layer stack over a substrate, the multi-layer stack comprising a plurality of nitride layers and a plurality of polycrystalline germanium layers alternately stacked; forming a plurality of channels The holes are perpendicular to the substrate; the patterned multilayer stack is formed to be linearly spaced between the via holes and perpendicular to the substrate, wherein the linear pitches extend downward to expose sidewalls of the nitride layer and the polysilicon layer; and through the linear pitch to have an air gap The plurality of insulating layers replace the polysilicon layer; and the nitride layer is replaced by a plurality of conductive layers through a linear pitch.

According to an embodiment, a three-dimensional stacked semiconductor structure is provided, including a substrate having an array area and a peripheral area; a patterned multi-layered stack formed over the substrate and located in the array area Inside. The patterned multilayer stack includes: a plurality of insulating layers having an air gap; a plurality of conductive layers, wherein the insulating layer and the conductive layer are alternately stacked; and the plurality of via holes are perpendicular to the substrate and extend downward through the insulating layer and conductive Floor.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

10‧‧‧Substrate

11M‧‧‧Multilayer stacking

21M-1‧‧‧ patterned multi-layer stack

111‧‧‧ nitride layer

112‧‧‧Polysilicon layer

113‧‧‧ bottom oxide layer

114‧‧‧Top oxide layer

12‧‧‧ holes

13‧‧‧Channel hole

131‧‧‧ Charge trapping layer

132‧‧‧Polysilicon channel layer

133‧‧‧dielectric layer

14‧‧‧cap oxide layer

16‧‧‧Linear pattern

161, 162, 163‧‧‧ linear spacing

171‧‧‧ first cavity

172‧‧‧Second cavity

18‧‧‧Oxide layer

181‧‧‧First Oxidation Department

182‧‧‧Second Oxidation Department

19‧‧‧ Conductive layer

191‧‧‧Dielectric inner liner

192‧‧‧Titanium nitride layer

193‧‧‧Metal tungsten layer

G _air ‧‧‧ air gap

a _X ‧‧‧ short axis

a _L ‧‧‧ long axis

L _air ‧‧‧Maximum length of _air gap

L _i ‧‧‧Air gap to the distance of adjacent conductive layers

1 to 8B are views showing a method of manufacturing a three-dimensional stacked semiconductor structure according to an embodiment of the present invention.

In the embodiments disclosed herein, a method of fabricating a three-dimensional stacked semiconductor structure and a structure thereof are proposed. According to the manufacturing method proposed in the embodiment, in an array region in the three-dimensional stacked memory structure, a patterned multi-layered stack includes a plurality of insulating layers having air-gaps and conducting The layers are alternately stacked and formed over a substrate. According to the method of the embodiment, the weight of the three-dimensional stacked memory structure can be reduced, so that when manufacturing the three-dimensional stacked memory structure, a channel hole structure (for example, having an ONO layer and a polysilicon channel layer) can support more as a support pillar. The stack. Furthermore, due to the presence of air-gaps in the insulating layer, the capacitance between adjacent conductive layers (e.g., as word lines) of the stack can be reduced. Moreover, the embodiment methods do not cause damage to related components and layers in the structure. The embodiment method is particularly suitable for fabricating a three-dimensional stacked memory structure having a large area array area, and the resulting structure has a stable structure (a reduction in the weight of the insulating layer, resulting in less weight loading on the support cylinder), related components The layers and layers have a complete configuration and enhance the electronic properties of the three-dimensional stacked memory structure.

The disclosed embodiments are widely used and can be applied to the fabrication of many three-dimensional stacked semiconductor structures. For example, the embodiment can be applied to a three-dimensional vertical-channel type semiconductor device, but the disclosure does not Application is limited. The following embodiments are presented in conjunction with the drawings to explain in detail the manufacturing method of the three-dimensional stacked semiconductor structure proposed in the present disclosure and related structures. However, the disclosure is not limited to this. The description in the embodiments, such as the detailed structure, the process steps and the application of the materials, etc., are for illustrative purposes only, and the scope of the disclosure is not limited to the aspects described.

It should be noted that the disclosure does not show all possible embodiments, and the structure and process of the embodiments may be modified and modified to meet the needs of practical applications without departing from the spirit and scope of the disclosure. Therefore, other implementations not presented in the present disclosure may also be applicable. In addition, the drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn in proportion to actual products. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

Furthermore, the terms used in the specification and the claims, such as "first", "second", "third" and the like, are used to modify the elements of the claim, and are not intended to represent and represent the request element. Any previous ordinal number does not represent the order of a request element and another request element, or the order of the manufacturing method. The use of these ordinals is only used to enable one request element with a certain name and the other A request element of the same name can be clearly distinguished.

1-8B illustrate a method of fabricating a three-dimensional stacked semiconductor structure in accordance with an embodiment of the present invention. As shown in FIG. 1, a multi-layered stack 11M is formed on a substrate 10, and the multilayer stack 11M includes a plurality of first dummy layers such as nitride layers. 111 and A plurality of second dummy layers, such as polysilicon layers 112, are alternately stacked in a direction perpendicular to one of the substrates 10 (e.g., the Z direction). In one embodiment, the nitride layer 111 as the first temporary layer is, for example, silicon nitride, and the polysilicon layer 112 as the second temporary layer 112 is, for example, an N-type heavily doped polysilicon layer (N+). Polysilicon layers) or P-type polysilicon layers. In one embodiment, if the second temporary layer of the multilayer stack 11M is removed by immersion with tetra-methyl ammonium hydroxide (TMAH) in a subsequent step, the polycrystalline germanium layer is heavily doped with an N-type. The second temporary layer (i.e., in the TMAH etchant, the N-type heavily doped polysilicon can be removed more quickly than the P-type heavily doped polysilicon).

Moreover, in one embodiment, the three-dimensional stacked semiconductor structure further includes a bottom oxide layer 113 and a top oxide layer 114, wherein the bottom oxide layer 113 is formed on the substrate 10, and the multilayer stack 11M Formed on the bottom oxide layer 113, a top oxide layer 114 (as a hard mask) is formed on the multilayer stack 11M as shown in FIG.

Thereafter, a plurality of holes 12 are formed perpendicular to the substrate 10, for example, by etching. As shown in FIG. 2, the holes 12 pass through the top oxide layer 114, the multilayer stack 11M, and the bottom oxide layer 113. The downwardly extending holes 12 are stopped on the bottom oxide layer 113 and expose the sidewalls of the nitride layer 111 and the sidewalls of the polysilicon layer 112.

Thereafter, a plurality of channel holes perpendicular to the substrate 10 are formed. In one embodiment, each of the via holes 13 includes a charge trapping layer 131 (used as a memory layer) as the hole 12 A liner, a polysilicon channel layer (eg, undoped polysilicon) 132 is deposited along the charge trapping layer 131 (ie, the polysilicon channel layer 132 is structured as a polysilicon liner), and a dielectric layer A dielectric medium layer 133 fills the remaining space within the hole 12, as shown in FIG. The dielectric layer 133 is, for example, an oxide layer or air. Furthermore, in one embodiment, the charge trapping layer 131 as a memory layer is, for example, an ONO layer or an ONONO layer or an ONONONO layer. For example, the charge trapping layer 131 may include a blocking oxide layer (adjacent to the sidewalls of the nitride layer 111 and the polysilicon layer 112), a trapping nitride layer, and a tunneling oxide layer ( Tunneling oxide layer) (adjacent to the polysilicon channel layer 132). In the exemplary embodiment of the embodiment, although an amacaroni-type channel configuration is exemplified (that is, the polysilicon system is partially filled as a channel layer of the via hole 13), the present disclosure Not limited to this. The polysilicon can also be completely filled in the holes as a channel layer to meet the needs of the actual application. Therefore, the disclosure is not particularly limited to the application of a particular aspect. Furthermore, a cap oxide layer 14 may be formed on the top oxide layer and cover the via holes 13 to protect the polysilicon channels, as shown in FIG. In some embodiments, the etched holes 12 may be stopped on the substrate 10, and the polysilicon channel layer 132 may be etched to form spacers to short-circuit the polysilicon channel layer 132 and the substrate 10. These implementation aspects are also aspects of the application of the present disclosure.

Please refer to Figures 4A and 4B. Figure 4A is a cross-sectional view of the structure taken along section line 4A-4A of Figure 4B in accordance with an embodiment of the present disclosure. FIG. 4B is a top view of one of the application aspects of the via hole 13 and a line pattern 16 in accordance with an embodiment of the present disclosure. However, the disclosure is not limited to the application of the channel holes of the honeycomb arrangement as shown in FIG. 4B.

As shown in FIGS. 4A and 4B, after the via hole 13 and the cap oxide layer 14 are formed, the multilayer stack 11M is patterned to form a linear pattern 16 and a plurality of patterned multi-layered stacks. 21M-1. The linear pattern 16 can assist in subsequent material replacement steps. In one embodiment, the linear pattern 16 includes a plurality of linear spaces (eg, linear pitches 161, 162, 163 in FIG. 4B) between the via holes 13 and a linear pitch perpendicular to the substrate 10 (ie, Extending along the Z-direction, as shown in Figure 4A. In FIG. 4A, for example, the linear pitch 162 extends downwardly and exposes the sidewalls of the nitride layer 111 and the sidewalls of the polysilicon layer 112. Moreover, in one embodiment, the vertical extent of the linear pitch (such as the linear pitch 162 of FIG. 4A) (eg, along the Z-direction) is parallel to the vertical extension of the channel aperture 13 (eg, along the Z-direction). .

In one embodiment, a linear pattern 16 may define a plurality of patterned multilayer stacks 21M-1 (as shown in FIG. 4A), and each patterned multilayer stack 21M-1 may include a plurality of vias 13 adjacent to each other. Between linear spacings, such as between linear spacings 161 and 162 (as shown in Figure 4B). In one embodiment, each patterned multilayer stack 21M-1 may include four or eight via holes 13 between two adjacent linear pitches, depending on the actual application and needs.

Next, a material replacement step is performed through the linear pattern 16 to replace the temporary layer in the patterned multilayer stack. For example, the linearity between the linear patterns 16 The polysilicon layer 112 is replaced with an insulating layer (for example, an oxide layer) having an air gap; and the nitride layer 111 is replaced with a conductive layer by a linear pitch of the linear pattern 16.

As shown in FIG. 5, the polysilicon layer 112 is removed. The polysilicon layer 112 can be removed by dry etching or wet etching. In one embodiment, the polysilicon layers 112 are removed by immersion in tetra-methyl ammonium hydroxide (TMAH) (ie, using a TMAH solution as an etchant). TMAH has a high selectivity ratio for oxides and nitrides. During the immersion of TMAH, the TMAH solution etches only the polysilicon without damaging the upper oxide layer of the ONO layer or the ONONO layer or the ONONONO layer (ie, the charge trap layer 131), thereby maintaining the ONO layer or the ONONO layer or the ONONONO layer. The gate oxide integrity (GOI) of the gate oxide layer. After the polysilicon layer 112 is completely removed, a plurality of first cavities 171 are formed, whereby the tantalum nitride layer (e.g., SiN) 111 remains in the structure, as shown in FIG.

Next, as shown in FIG. 6A, a plurality of oxide layers 18 having an air gap G _{air are} deposited in the first cavity 171 as an insulating layer for replacing the polysilicon layer 112. The air gap G _air coated in each of the oxide layers 18 can be formed by two-stage deposition. Figure 6B is an enlarged schematic view of the oxide layer 18 in one of the first cavities in Figure 6A. In one embodiment, the deposition of the oxide layer 18 includes, for example: (1) conformally depositing a first oxidized portion 181 (FIG. 6B) on the first cavity 171 (ie, in a corresponding first space) Each of the first oxidized portions 181 in the cavity 171 is formed as an oxide liner; and (2) non-conformally depositing the second oxidized portion 182 in the first cavity 171 along the first oxidized portion 181 In order to generate an air gap G _{air, it is} coated in the oxide layer 18. In other words, the air gap G _air at the first cavity 171 is covered by the first oxidizing portion 181 and the second oxidizing portion 182.

Furthermore, an anisotropic etching step (for example, dry etching or wet etching) is performed to remove a portion of the oxide layer (to remove the oxide portion of the nitride layer 111 improperly), thereby exposing the nitride layer 111. As shown in Figure 6A.

In one embodiment, each air gap G _air is completely covered by the oxide layer 18, as shown in FIG. 6A. In Fig. 6A, the air gap G _air is spaced apart from the adjacent two nitride layers 111 by a distance and has a spindle-shaped cross-section. In one embodiment, the spindle-shaped profile of the air gap G _{air has} , for example, one of a short axis a _X (perpendicular to the substrate 10) and a long axis a _L (parallel to the substrate 10). Moreover, in an embodiment, the air gap G _air may be substantially located in the center of the oxide layer 18.

Thereafter, the nitride layer 111 is replaced by a conductive layer (for example, including a metal layer) through the linear pitch of the linear pattern 16. As shown in FIG. 7, the step of removing the nitride layer 111 is performed; for example, the nitride layer 111 is completely removed by immersion in a hot phosphoric acid solution (H ₃ PO ₄ ) to form a plurality of layers. Second cavities 172, thereby exposing the via holes 13 and the oxide layer 18.

Next, as shown in FIG. 8A, a conductive layer 19 is formed in the second cavities 172 to complete the replacement of the nitride layer 111. Similarly, the conductive layer 19 is patterned by chemical dry etching (CDE) or wet etching (non-isotropic etching) to pull back the sidewalls of the conductive layer 19, thereby avoiding adjacent conduction. There is an unnecessary connection between layers 19 (causing a short circuit). In the application of vertical channel (VC) semiconductor components, the conductive layer 19 can be used as a word line. Furthermore, in FIG. 8A, the air gap G _air having the spindle profile has a maximum length L _air perpendicular to the substrate 10 (ie, the maximum length L _air is parallel to the Z-direction), and the air gap G _air system The adjacent two conductive layers 19 are separated by a distance L _i . In one embodiment, the maximum length L _{air is} greater than the distance L _i ; for example, the ratio of the maximum length L _air to the distance L _i is equal to 2 or greater than 2. As shown in FIG. 8A, for the oxide layer 18, the length (L _i ) of the oxidized material and the length (L _air ) of the air gap G _air can be expressed, for example, as: L _i : L _air : L _i =, 1: 2:1.

Furthermore, each of the conductive layers 19 is, for example, a multi-layered configuration. Figure 8B is a partial enlarged view of the conductive layer 19 in a second cavity in Figure 8A, in accordance with an embodiment. In one embodiment, the conductive layer 19 in the second cavity 172 may include a high-k dielectric liner film 191 (eg, aluminum oxide (AlOx) or hafnium oxide (HfOx). )) in the second cavity 172; a titanium nitride (TiN) layer 192 is deposited in the second cavity 172 and deposited along the high dielectric constant dielectric liner 191; and a metal The tungsten (W) layer 193 fills the remaining space within the second cavity 172. The metal tungsten layer 193 of the conductive layer 19 can reduce the word line resistance.

According to the above embodiment, a method for fabricating a three-dimensional stacked semiconductor structure is provided. In an array region of a three-dimensional stacked memory structure, a patterned multilayer stack includes a plurality of insulating layers (eg, oxide layer 18) having an air gap and An alternating stack of conductive layers (eg, conductive layers 19) may be formed over a substrate. Since the array area of the three-dimensional stacked memory structure is a large area, the presence of the air gap can reduce the weight of the three-dimensional stacked memory structure, and the channel hole structure (for example, including the ONO layer and the polysilicon channel layer) as the support cylinder is stacked in three dimensions. More stacks can be supported in the process of memory structure. Furthermore, the presence of the air gap G _air reduces the capacitance between adjacent conductive layers 19 of the stack (the dielectric constant of the oxide is 3.9, and the dielectric constant of air is 1), thereby enhancing the three-dimensional stacking of the present application. The electronic properties of the memory structure. Moreover, the embodiment methods do not cause damage to related components and layers in the structure. The embodiment method is particularly suitable for fabricating a three-dimensional stacked memory structure having a high and thin support pillar (such as a via hole) or a large number of laminates, and the resulting structure has a stable structure (due to a reduction in the weight of the insulating layer) The weight loading of the support cylinders, the associated components and layers have a complete configuration and provide stable three-dimensional stacked memory structure electronic properties. Furthermore, the three-dimensional stacked memory structure of the embodiment is fabricated in a time-consuming and non-expensive process, and is very suitable for mass production.

The structures and steps of the above-described embodiments are used to describe some embodiments or application examples of the disclosure, and the disclosure is not limited to the scope and application of the above structures and steps. Embodiments of other different structural aspects, such as known components of different internal components, may be applied, and the structures and steps of the examples may be adjusted according to the needs of the actual application. Therefore, the structures shown in the drawings are for illustrative purposes only and are not limiting. It is generally known to those skilled in the art to apply the related structures and steps of the present disclosure, such as the arrangement of elements and layers in the array region in a three-dimensional stacked semiconductor structure, or the shape and relative position of the air gap, or step details, etc. There may be corresponding adjustments and changes depending on the actual application.

In summary, although the invention has been disclosed above by way of example, It is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (10)

A method of fabricating a three-dimensional stacked semiconductor structure includes: forming a multi-layered stack over a substrate, the multilayer stack including a plurality of nitride layers and a plurality of polysilicon layers Alternatingly stacked; forming a plurality of channel holes perpendicular to the substrate; patterning the multilayer stack to form linear spaces between the via holes and perpendicular to the substrate, wherein the linear pitches Extending downwardly to expose sidewalls of the nitride layer and the polysilicon layer; disposing the polysilicon layers through a plurality of insulating layers having air-gaps through the linear spacing; and transmitting the linear spacing The nitride layers are replaced by a plurality of conductive layers. The method of fabricating a three-dimensional stacked semiconductor structure according to claim 1, wherein a bottom oxide layer is formed on the substrate, the multilayer stack is formed on the bottom oxide layer, and a top oxide layer is formed on the multilayer stack. And wherein the channel holes extend downward to stop on the bottom oxide layer. The method for fabricating a three-dimensional stacked semiconductor structure according to claim 2, further comprising forming a cap oxide layer on the top oxide layer, wherein the cap oxide layer covers the via holes, And the step of patterning the multilayer stack to form the linear pitches is performed after forming the cap oxide layer, wherein the linear pitches extend downward to expose the bottom oxide layer. The method for manufacturing a three-dimensional stacked semiconductor structure according to claim 1, wherein the step of replacing the polysilicon layers with the insulating layers comprises: completely removing the polysilicon layers to form a plurality of first cavities And depositing a plurality of oxide layers in the first cavities as the insulating layers, wherein depositing the oxide layers comprises: conformally depositing the first oxidized portions on the first a cavity; and non-conformally depositing a second oxidized portion in the first cavities to form the air gaps; wherein each of the air gaps is completely covered by each of the oxide layers in. A three-dimensional stacked semiconductor structure includes: a substrate having an array area and a peripheral area; a patterned multi-layered stack formed over the substrate and located in the array area The patterned multilayer stack includes: a plurality of insulating layers having air-gaps; a plurality of conductive layers, wherein the insulating layers and the conductive layers are alternately stacked; a plurality of channel holes ) perpendicular to the substrate and extending downwardly through the insulating layer and the conductive layers; and a bottom oxide layer formed on the substrate; The channel holes extending downwardly are stopped in the bottom oxide layer, and the bottoms of the channel holes are in direct contact with the bottom oxide layer. The three-dimensional stacked semiconductor structure of claim 5, wherein the patterned multilayer stack is formed on the bottom oxide layer, and a top oxide layer is formed on the patterned multilayer stack. The three-dimensionally-stacked semiconductor structure of claim 6, wherein a cap oxide layer is formed on the top oxide layer and covers the via holes, wherein one of the via holes comprises: A charge trapping layer is a liner corresponding to the via hole; a polysilicon channel layer is deposited along the charge trap layer; and a dielectric medium layer is filled Corresponding to the remaining space in the hole of the channel. The three-dimensionally-stacked semiconductor structure of claim 5, wherein the insulating layers having the air gaps are a plurality of oxide layers having the air gaps, wherein the oxide layers each comprise: a first An oxidizing portion is conformally deposited; and a second oxidizing portion is non-conformally deposited along the first oxidizing portion to generate one of the air gaps, wherein one of the air gaps is the first oxidizing portion and the first portion The dioxide unit is completely coated. The three-dimensional stacked semiconductor structure of claim 5, wherein one of the air gaps of the insulating layers has a spindle-shaped cross-section, wherein one of the air gaps The spindle profile has a maximum length L _air perpendicular to the substrate, the air gap being spaced apart from the adjacent two conductive layers by a distance L _i , wherein the maximum length L _{air is} greater than the distance L _i . The three-dimensional stacked semiconductor structure of claim 9, wherein the ratio of the maximum length L _air to the distance L _i is equal to or greater than two.