TWI646667B - Method for manufacturing three dimensional stacked semiconductor structure and structure manufactured by the same - Google Patents
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Abstract
一種三維堆疊半導體結構之製造方法及其製得之結構。實施例之製造方法中,形成一多層堆疊於一基板上方,多層堆疊包括複數個氮化層和複數個多晶矽層交替堆疊而成。形成複數個通道孔垂直於基板。圖案化多層堆疊而形成線性間距於通道孔之間且垂直於基板,其中該些線性間距向下延伸而暴露出氮化層和多晶矽層之側壁。透過線性間距以具有氣隙之複數層絕緣層置換多晶矽層,和透過線性間距以複數層導電層置換氮化層。 A method of fabricating a three-dimensional stacked semiconductor structure and a structure thereof. In the manufacturing method of the embodiment, a plurality of layers are stacked on top of a substrate, and the multilayer stack includes a plurality of nitride layers and a plurality of polycrystalline germanium layers alternately stacked. A plurality of channel holes are formed perpendicular to the substrate. The multilayer stack is patterned to form a linear pitch between the via holes and perpendicular to the substrate, wherein the linear pitches extend downward to expose sidewalls of the nitride layer and the polysilicon layer. The polysilicon layer is replaced by a plurality of insulating layers having an air gap through a linear pitch, and the nitride layer is replaced by a plurality of conductive layers through a linear pitch.
Description
本發明是有關於一種三維堆疊半導體結構之製造方法及其製得之結構,且特別是有關於一種具有氣隙(air-gaps)於絕緣層內之三維堆疊半導體結構及其製造方法。 The present invention relates to a method of fabricating a three-dimensional stacked semiconductor structure and a structure thereof, and more particularly to a three-dimensional stacked semiconductor structure having an air-gaps in an insulating layer and a method of fabricating the same.
非揮發性記憶體元件在設計上有一個很大的特性是,當記憶體元件失去或移除電源後仍能保存資料狀態的完整性。目前業界已有許多不同型態的非揮發性記憶體元件被提出。不過相關業者仍不斷研發新的設計或是結合現有技術,進行記憶胞平面的堆疊以達到具有更高儲存容量的記憶體結構。例如已有一些三維堆疊反及閘(NAND)型快閃記憶體結構被提出。然而,傳統的三維堆疊記憶體結構仍有一些問題需要被解決。 A very important feature of non-volatile memory components is the ability to preserve the integrity of the data state when the memory component loses or removes power. Many different types of non-volatile memory components have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, some three-dimensional stacked NAND (NAND) type flash memory structures have been proposed. However, there are still some problems that need to be solved in the traditional three-dimensional stacked memory structure.
例如,於三維堆疊記憶體結構中的一陣列區域中,相鄰疊層之導電層之間的電容過高,而當結構中的陣列區域更大或是所需架構的疊層數目更多時,電容會更高。再者,以傳統方 法製作的三維堆疊記憶體結構,當結構中所需架構的疊層數目很多時,其堆疊容易出現彎曲甚至倒塌的問題。 For example, in an array region of a three-dimensional stacked memory structure, the capacitance between the conductive layers of adjacent stacks is too high, and when the array area in the structure is larger or the number of stacks of the desired structure is more The capacitance will be higher. Furthermore, the traditional side The three-dimensional stacked memory structure produced by the method has a problem that the stack is prone to bending or even collapse when the number of layers of the required structure in the structure is large.
本發明係有關於一種三維堆疊半導體結構之製造方法及其製得之結構。根據實施例,多個具有氣隙(air-gaps)的絕緣層和導電層交替堆疊,使形成的三維堆疊記憶體結構之重量可減少,且可降低相鄰導電層之間的電容。 The present invention relates to a method of fabricating a three-dimensional stacked semiconductor structure and the resulting structure. According to an embodiment, a plurality of insulating layers and conductive layers having air-gaps are alternately stacked, so that the weight of the formed three-dimensional stacked memory structure can be reduced, and the capacitance between adjacent conductive layers can be reduced.
根據一實施例,係提出一種三維堆疊半導體結構之製造方法,包括:形成一多層堆疊於一基板上方,多層堆疊包括複數個氮化層和複數個多晶矽層交替堆疊而成;形成複數個通道孔垂直於基板;圖案化多層堆疊而形成線性間距於通道孔之間且垂直於基板,其中該些線性間距向下延伸而暴露出氮化層和多晶矽層之側壁;透過線性間距以具有氣隙之複數層絕緣層置換多晶矽層;和透過線性間距以複數層導電層置換氮化層。 According to an embodiment, a method for fabricating a three-dimensional stacked semiconductor structure is provided, comprising: forming a multi-layer stack over a substrate, the multi-layer stack comprising a plurality of nitride layers and a plurality of polycrystalline germanium layers alternately stacked; forming a plurality of channels The holes are perpendicular to the substrate; the patterned multilayer stack is formed to be linearly spaced between the via holes and perpendicular to the substrate, wherein the linear pitches extend downward to expose sidewalls of the nitride layer and the polysilicon layer; and through the linear pitch to have an air gap The plurality of insulating layers replace the polysilicon layer; and the nitride layer is replaced by a plurality of conductive layers through a linear pitch.
根據一實施例,係提出一種三維堆疊半導體結構,包括一基板,具有一陣列區域(array area)和一周邊區域;一圖案化多層堆疊(patterned multi-layered stack)形成於基板上方且位於陣列區域內。圖案化多層堆疊包括:具有氣隙之複數層絕緣層;複數層導電層,其中絕緣層和導電層係交替地堆疊;和複數個通道孔垂直於基板並向下延伸而穿過絕緣層和導電層。 According to an embodiment, a three-dimensional stacked semiconductor structure is provided, including a substrate having an array area and a peripheral area; a patterned multi-layered stack formed over the substrate and located in the array area Inside. The patterned multilayer stack includes: a plurality of insulating layers having an air gap; a plurality of conductive layers, wherein the insulating layer and the conductive layer are alternately stacked; and the plurality of via holes are perpendicular to the substrate and extend downward through the insulating layer and conductive Floor.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下: In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings
10‧‧‧基板 10‧‧‧Substrate
11M‧‧‧多層堆疊 11M‧‧‧Multilayer stacking
21M-1‧‧‧圖案化多層堆疊 21M-1‧‧‧ patterned multi-layer stack
111‧‧‧氮化層 111‧‧‧ nitride layer
112‧‧‧多晶矽層 112‧‧‧Polysilicon layer
113‧‧‧底氧化層 113‧‧‧ bottom oxide layer
114‧‧‧頂氧化層 114‧‧‧Top oxide layer
12‧‧‧孔洞 12‧‧‧ holes
13‧‧‧通道孔 13‧‧‧Channel hole
131‧‧‧電荷捕捉層 131‧‧‧ Charge trapping layer
132‧‧‧多晶矽通道層 132‧‧‧Polysilicon channel layer
133‧‧‧介電介質層 133‧‧‧dielectric layer
14‧‧‧帽蓋氧化層 14‧‧‧cap oxide layer
16‧‧‧線性圖案 16‧‧‧Linear pattern
161、162、163‧‧‧線性間距 161, 162, 163‧‧‧ linear spacing
171‧‧‧第一空腔 171‧‧‧ first cavity
172‧‧‧第二空腔 172‧‧‧Second cavity
18‧‧‧氧化層 18‧‧‧Oxide layer
181‧‧‧第一氧化部 181‧‧‧First Oxidation Department
182‧‧‧第二氧化部 182‧‧‧Second Oxidation Department
19‧‧‧導電層 19‧‧‧ Conductive layer
191‧‧‧介電內襯層 191‧‧‧Dielectric inner liner
192‧‧‧氮化鈦層 192‧‧‧Titanium nitride layer
193‧‧‧金屬鎢層 193‧‧‧Metal tungsten layer
Gair‧‧‧氣隙 G air ‧‧‧ air gap
aX‧‧‧短軸 a X ‧‧‧ short axis
aL‧‧‧長軸 a L ‧‧‧ long axis
Lair‧‧‧氣隙的最大長度 L air ‧‧‧Maximum length of air gap
Li‧‧‧氣隙至相鄰導電層之距離 L i ‧‧‧Air gap to the distance of adjacent conductive layers
第1~8B圖係繪示本發明一實施例之三維堆疊半導體結構之製造方法。 1 to 8B are views showing a method of manufacturing a three-dimensional stacked semiconductor structure according to an embodiment of the present invention.
在此揭露內容之實施例中,係提出三維堆疊半導體結構之製造方法及其製得之結構。根據實施例提出之製造方法,於三維堆疊記憶體結構中的一陣列區域中,一圖案化多層堆疊(a patterned multi-layered stack)包括多個具有氣隙(air-gaps)的絕緣層和導電層交替堆疊形成於一基板上方。根據實施例之方法可以減少三維堆疊記憶體結構的重量,因此於製造三維堆疊記憶體結構時,通道孔(channel hole)結構(例如具有ONO層和多晶矽通道層)作為支撐柱體可以支撐更多的疊層。再者,由於絕緣層內氣隙(air-gaps)的存在,可降低疊層之相鄰導電層(例如做為字元線)之間的電容。再者,實施例方法不會對結構中的相關元件和層造成損傷。實施例方法特別適合用於製造具有大面積陣列區域的三維堆疊記憶體結構,且製得的結構具有穩固的架構(因絕緣層重量減少,造成對支撐柱體較少的重量負載)、相關元件和層具有完整構型、以及可增進三維堆疊記憶體結構的電子特性。 In the embodiments disclosed herein, a method of fabricating a three-dimensional stacked semiconductor structure and a structure thereof are proposed. According to the manufacturing method proposed in the embodiment, in an array region in the three-dimensional stacked memory structure, a patterned multi-layered stack includes a plurality of insulating layers having air-gaps and conducting The layers are alternately stacked and formed over a substrate. According to the method of the embodiment, the weight of the three-dimensional stacked memory structure can be reduced, so that when manufacturing the three-dimensional stacked memory structure, a channel hole structure (for example, having an ONO layer and a polysilicon channel layer) can support more as a support pillar. The stack. Furthermore, due to the presence of air-gaps in the insulating layer, the capacitance between adjacent conductive layers (e.g., as word lines) of the stack can be reduced. Moreover, the embodiment methods do not cause damage to related components and layers in the structure. The embodiment method is particularly suitable for fabricating a three-dimensional stacked memory structure having a large area array area, and the resulting structure has a stable structure (a reduction in the weight of the insulating layer, resulting in less weight loading on the support cylinder), related components The layers and layers have a complete configuration and enhance the electronic properties of the three-dimensional stacked memory structure.
此揭露內容之實施例其應用十分廣泛,可應用在許多三維堆疊半導體結構之製程。舉例來說,實施例可應用在三維垂直通道(vertical-channel)式之半導體元件,但本揭露並不以此 應用為限。以下係提出相關實施例,配合圖示以詳細說明本揭露所提出之三維堆疊半導體結構之製造方法及其相關結構。然而本揭露並不僅限於此。實施例中之敘述,如細部結構、製程步驟和材料應用等等,僅為舉例說明之用,本揭露欲保護之範圍並非僅限於所述之態樣。 The disclosed embodiments are widely used and can be applied to the fabrication of many three-dimensional stacked semiconductor structures. For example, the embodiment can be applied to a three-dimensional vertical-channel type semiconductor device, but the disclosure does not Application is limited. The following embodiments are presented in conjunction with the drawings to explain in detail the manufacturing method of the three-dimensional stacked semiconductor structure proposed in the present disclosure and related structures. However, the disclosure is not limited to this. The description in the embodiments, such as the detailed structure, the process steps and the application of the materials, etc., are for illustrative purposes only, and the scope of the disclosure is not limited to the aspects described.
需注意的是,本揭露並非顯示出所有可能的實施例,相關領域者可在不脫離本揭露之精神和範圍內對實施例之結構和製程加以變化與修飾,以符合實際應用所需。因此,未於本揭露提出的其他實施態樣也可能可以應用。再者,圖式係已簡化以利清楚說明實施例之內容,圖式上的尺寸比例並非按照實際產品等比例繪製。因此,說明書和圖示內容僅作敘述實施例之用,而非作為限縮本揭露保護範圍之用。 It should be noted that the disclosure does not show all possible embodiments, and the structure and process of the embodiments may be modified and modified to meet the needs of practical applications without departing from the spirit and scope of the disclosure. Therefore, other implementations not presented in the present disclosure may also be applicable. In addition, the drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn in proportion to actual products. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.
再者,說明書與請求項中所使用的序數例如”第一”、”第二”、”第三”等之用詞,是為了修飾請求項之元件,其本身並不意含及代表該請求元件有任何之前的序數,也不代表某一請求元件與另一請求元件的順序、或是製造方法上的順序,該些序數的使用僅用來使具有某命名的一請求元件得以和另一具有相同命名的請求元件能作出清楚區分。 Furthermore, the terms used in the specification and the claims, such as "first", "second", "third" and the like, are used to modify the elements of the claim, and are not intended to represent and represent the request element. Any previous ordinal number does not represent the order of a request element and another request element, or the order of the manufacturing method. The use of these ordinals is only used to enable one request element with a certain name and the other A request element of the same name can be clearly distinguished.
第1~8B圖繪示本發明一實施例之三維堆疊半導體結構之製造方法。如第1圖所示,一多層堆疊(a multi-layered stack)11M形成於一基板10上,多層堆疊11M包括複數個第一暫置層(first dummy layers)例如氮化層(nitride layers)111和 複數個第二暫置層(second dummy layers)例如多晶矽層(polysilicon layers)112沿著垂直於基板10之一方向(例如Z方向)交替堆疊。一實施例中,做為第一暫置層之氮化層111例如是氮化矽(silicon nitride),做為第二暫置層112之多晶矽層112例如是N型重摻雜多晶矽層(N+ polysilicon layers)或P型重摻雜多晶矽層(P+ polysilicon layers)。一實施例中,如後續步驟中欲以氫氧化四甲基銨(tetra-methyl ammonium hydroxide,TMAH)浸置而移除多層堆疊11M的第二暫置層,則以N型重摻雜多晶矽層為第二暫置層(亦即,在TMAH蝕刻液中,N型重摻雜多晶矽比起P型重摻雜多晶矽可以更快速地被去除)。 1-8B illustrate a method of fabricating a three-dimensional stacked semiconductor structure in accordance with an embodiment of the present invention. As shown in FIG. 1, a multi-layered stack 11M is formed on a substrate 10, and the multilayer stack 11M includes a plurality of first dummy layers such as nitride layers. 111 and A plurality of second dummy layers, such as polysilicon layers 112, are alternately stacked in a direction perpendicular to one of the substrates 10 (e.g., the Z direction). In one embodiment, the nitride layer 111 as the first temporary layer is, for example, silicon nitride, and the polysilicon layer 112 as the second temporary layer 112 is, for example, an N-type heavily doped polysilicon layer (N+). Polysilicon layers) or P-type polysilicon layers. In one embodiment, if the second temporary layer of the multilayer stack 11M is removed by immersion with tetra-methyl ammonium hydroxide (TMAH) in a subsequent step, the polycrystalline germanium layer is heavily doped with an N-type. The second temporary layer (i.e., in the TMAH etchant, the N-type heavily doped polysilicon can be removed more quickly than the P-type heavily doped polysilicon).
再者,一實施例中,三維堆疊半導體結構更包括一底氧化層(bottom oxide layer)113和一頂氧化層(top oxide layer)114,其中底氧化層113形成於基板10上,多層堆疊11M形成於底氧化層113上,一頂氧化層114(做為一硬質遮罩)形成於多層堆疊11M上,如第1圖所示。 Moreover, in one embodiment, the three-dimensional stacked semiconductor structure further includes a bottom oxide layer 113 and a top oxide layer 114, wherein the bottom oxide layer 113 is formed on the substrate 10, and the multilayer stack 11M Formed on the bottom oxide layer 113, a top oxide layer 114 (as a hard mask) is formed on the multilayer stack 11M as shown in FIG.
之後,例如以蝕刻形成複數個孔洞(holes)12垂直於基板10。如第2圖所示,孔洞12穿過頂氧化層114、多層堆疊11M和底氧化層113。向下延伸的孔洞12係停在底氧化層113上,並暴露出氮化層111之側壁和多晶矽層112之側壁。 Thereafter, a plurality of holes 12 are formed perpendicular to the substrate 10, for example, by etching. As shown in FIG. 2, the holes 12 pass through the top oxide layer 114, the multilayer stack 11M, and the bottom oxide layer 113. The downwardly extending holes 12 are stopped on the bottom oxide layer 113 and expose the sidewalls of the nitride layer 111 and the sidewalls of the polysilicon layer 112.
之後,形成垂直於基板10的複數個通道孔(channel holes)。一實施例中,各個通道孔13包括一電荷捕捉層(charge trapping layer)131(做為一記憶層之用)為孔洞12之 一襯裡(a liner)、一多晶矽通道層(polysilicon channel layer)(例如未摻雜之多晶矽)132沿著電荷捕捉層131沉積(亦即多晶矽通道層132係如一多晶矽襯裡之構型)、以及一介電介質層(dielectric medium layer)133填滿孔洞12內之剩餘空間,如第3圖所示。而介電介質層133例如是氧化層或空氣。再者,一實施例中,做為一記憶層之電荷捕捉層131例如是一ONO層或一ONONO層或一ONONONO層。例如,電荷捕捉層131可能包括一阻擋氧化層(blocking oxide layer)(相鄰於氮化層111和多晶矽層112之側壁)、一氮化物捕捉層(trapping nitride layer)和一穿隧氧化層(tunneling oxide layer)(相鄰於多晶矽通道層132)。於實施例之示例圖式中,雖然是以通心粉式的通道結構(amacaroni-type channel configuration)做示例(亦即,多晶矽係部分填充以做為通道孔13之一通道層),但本揭露並不以此為限。多晶矽亦可完全填充於孔洞以做為通道層,以符合實際應用時之需求。因此,本揭露並不特別僅限制於某一特定態樣之應用。再者,一帽蓋氧化層(cap oxide layer)14可形成於頂氧化層上並覆蓋通道孔13以保護多晶矽通道,如第3圖所示。在一些實施例中,蝕刻後的孔洞12可以是停在基板10上,且可蝕刻多晶矽通道層132以形成間隙壁,使多晶矽通道層132和基板10之間短路。該些實施態樣亦屬本揭露之應用態樣。 Thereafter, a plurality of channel holes perpendicular to the substrate 10 are formed. In one embodiment, each of the via holes 13 includes a charge trapping layer 131 (used as a memory layer) as the hole 12 A liner, a polysilicon channel layer (eg, undoped polysilicon) 132 is deposited along the charge trapping layer 131 (ie, the polysilicon channel layer 132 is structured as a polysilicon liner), and a dielectric layer A dielectric medium layer 133 fills the remaining space within the hole 12, as shown in FIG. The dielectric layer 133 is, for example, an oxide layer or air. Furthermore, in one embodiment, the charge trapping layer 131 as a memory layer is, for example, an ONO layer or an ONONO layer or an ONONONO layer. For example, the charge trapping layer 131 may include a blocking oxide layer (adjacent to the sidewalls of the nitride layer 111 and the polysilicon layer 112), a trapping nitride layer, and a tunneling oxide layer ( Tunneling oxide layer) (adjacent to the polysilicon channel layer 132). In the exemplary embodiment of the embodiment, although an amacaroni-type channel configuration is exemplified (that is, the polysilicon system is partially filled as a channel layer of the via hole 13), the present disclosure Not limited to this. The polysilicon can also be completely filled in the holes as a channel layer to meet the needs of the actual application. Therefore, the disclosure is not particularly limited to the application of a particular aspect. Furthermore, a cap oxide layer 14 may be formed on the top oxide layer and cover the via holes 13 to protect the polysilicon channels, as shown in FIG. In some embodiments, the etched holes 12 may be stopped on the substrate 10, and the polysilicon channel layer 132 may be etched to form spacers to short-circuit the polysilicon channel layer 132 and the substrate 10. These implementation aspects are also aspects of the application of the present disclosure.
請參照第4A圖和第4B圖。第4A圖為根據本揭露之一實施例沿著第4B圖中之剖面線4A-4A繪製之結構剖面圖。 第4B圖為根據本揭露之一實施例中通道孔13和一線性圖案(line pattern)16的其中一種應用態樣之上視圖。然本揭露並不僅限於如第4B圖所示之蜂巢狀排列之通道孔的應用態樣。 Please refer to Figures 4A and 4B. Figure 4A is a cross-sectional view of the structure taken along section line 4A-4A of Figure 4B in accordance with an embodiment of the present disclosure. FIG. 4B is a top view of one of the application aspects of the via hole 13 and a line pattern 16 in accordance with an embodiment of the present disclosure. However, the disclosure is not limited to the application of the channel holes of the honeycomb arrangement as shown in FIG. 4B.
如第4A圖和第4B圖所示,在形成通道孔13和帽蓋氧化層14之後,多層堆疊11M被圖案化而形成一線性圖案16和多個圖案化多層堆疊(patterned multi-layered stack)21M-1。線性圖案16可協助後續進行的材料置換步驟。一實施例中,線性圖案16包括多個線性間距(linear spaces)(例如第4B圖中之線性間距161、162、163)於通道孔13之間,且線性間距垂直於基板10(亦即,沿著Z-方向延伸),如第4A圖所示。第4A圖中,例如線性間距162係向下延伸並暴露出氮化層111之側壁和多晶矽層112之側壁。再者,一實施例中,線性間距(如第4A圖之線性間距162)的垂直延伸方向(例如沿著Z-方向)係平行於通道孔13的垂直延伸方向(例如沿著Z-方向)。 As shown in FIGS. 4A and 4B, after the via hole 13 and the cap oxide layer 14 are formed, the multilayer stack 11M is patterned to form a linear pattern 16 and a plurality of patterned multi-layered stacks. 21M-1. The linear pattern 16 can assist in subsequent material replacement steps. In one embodiment, the linear pattern 16 includes a plurality of linear spaces (eg, linear pitches 161, 162, 163 in FIG. 4B) between the via holes 13 and a linear pitch perpendicular to the substrate 10 (ie, Extending along the Z-direction, as shown in Figure 4A. In FIG. 4A, for example, the linear pitch 162 extends downwardly and exposes the sidewalls of the nitride layer 111 and the sidewalls of the polysilicon layer 112. Moreover, in one embodiment, the vertical extent of the linear pitch (such as the linear pitch 162 of FIG. 4A) (eg, along the Z-direction) is parallel to the vertical extension of the channel aperture 13 (eg, along the Z-direction). .
一實施例中,一線性圖案16可定義出數個圖案化多層堆疊21M-1(如第4A圖所示),且各個圖案化多層堆疊21M-1可包括數個通道孔13於兩相鄰線性間距之間,例如線性間距161和162之間(如第4B圖所示)。一實施例中,各圖案化多層堆疊21M-1可包括4個或8個通道孔13於兩相鄰線性間距之間,可視實際應用情況與需求而定。 In one embodiment, a linear pattern 16 may define a plurality of patterned multilayer stacks 21M-1 (as shown in FIG. 4A), and each patterned multilayer stack 21M-1 may include a plurality of vias 13 adjacent to each other. Between linear spacings, such as between linear spacings 161 and 162 (as shown in Figure 4B). In one embodiment, each patterned multilayer stack 21M-1 may include four or eight via holes 13 between two adjacent linear pitches, depending on the actual application and needs.
接著,透過線性圖案16進行材料置換步驟,以置換圖案化多層堆疊中的暫置層。例如,透過線性圖案16的線性間 距,將多晶矽層112置換為具有氣隙之絕緣層(例如氧化層);以及透過線性圖案16的線性間距,將氮化層111置換為導電層。 Next, a material replacement step is performed through the linear pattern 16 to replace the temporary layer in the patterned multilayer stack. For example, the linearity between the linear patterns 16 The polysilicon layer 112 is replaced with an insulating layer (for example, an oxide layer) having an air gap; and the nitride layer 111 is replaced with a conductive layer by a linear pitch of the linear pattern 16.
如第5圖所示,移除多晶矽層112。其中多晶矽層112可利用乾式蝕刻或濕式蝕刻而移除。一實施例中,該些多晶矽層112係以浸置氫氧化四甲基銨(tetra-methyl ammonium hydroxide,TMAH)的方式而移除(亦即,使用TMAH溶液做為一蝕刻液)。TMAH對於氧化物和氮化物有很高的選擇比。在浸置TMAH期間,TMAH溶液僅對於多晶矽進行蝕刻而不會損傷ONO層或ONONO層或ONONONO層(亦即,電荷捕捉層131)的上氧化層,因而可保持ONO層或ONONO層或ONONONO層之閘極氧化層的良好完整性(gate oxide integrity,GOI)。在完全移除多晶矽層112後,會形成多個第一空腔(first cavities)171,至此氮化矽層(例如,SiN)111仍留在結構中,如第5圖所示。 As shown in FIG. 5, the polysilicon layer 112 is removed. The polysilicon layer 112 can be removed by dry etching or wet etching. In one embodiment, the polysilicon layers 112 are removed by immersion in tetra-methyl ammonium hydroxide (TMAH) (ie, using a TMAH solution as an etchant). TMAH has a high selectivity ratio for oxides and nitrides. During the immersion of TMAH, the TMAH solution etches only the polysilicon without damaging the upper oxide layer of the ONO layer or the ONONO layer or the ONONONO layer (ie, the charge trap layer 131), thereby maintaining the ONO layer or the ONONO layer or the ONONONO layer. The gate oxide integrity (GOI) of the gate oxide layer. After the polysilicon layer 112 is completely removed, a plurality of first cavities 171 are formed, whereby the tantalum nitride layer (e.g., SiN) 111 remains in the structure, as shown in FIG.
接著,如第6A圖所示,沉積具氣隙Gair之多層氧化層(oxide layers)18於第一空腔171,以做為置換多晶矽層112的絕緣層。其中,包覆於各氧化層18之中的氣隙Gair可透過兩階段沈積而形成。第6B圖係為第6A圖中位於第一空腔其中一者之氧化層18的放大示意圖。一實施例中,氧化層18的沈積例如是包括:(1)保形地(conformally)沉積第一氧化部181(第6B圖)於第一空腔171(亦即,在對應的第一空腔171中的各第一氧化部181係形成為氧化物襯裡);以及(2)沿著第一氧化部181非保形 地(non-conformally)沉積第二氧化部182於第一空腔171,以產生氣隙Gair包覆於氧化層18之中。換句話說,在第一空腔171處的氣隙Gair被第一氧化部181和第二氧化部182所包覆。 Next, as shown in FIG. 6A, a plurality of oxide layers 18 having an air gap G air are deposited in the first cavity 171 as an insulating layer for replacing the polysilicon layer 112. The air gap G air coated in each of the oxide layers 18 can be formed by two-stage deposition. Figure 6B is an enlarged schematic view of the oxide layer 18 in one of the first cavities in Figure 6A. In one embodiment, the deposition of the oxide layer 18 includes, for example: (1) conformally depositing a first oxidized portion 181 (FIG. 6B) on the first cavity 171 (ie, in a corresponding first space) Each of the first oxidized portions 181 in the cavity 171 is formed as an oxide liner; and (2) non-conformally depositing the second oxidized portion 182 in the first cavity 171 along the first oxidized portion 181 In order to generate an air gap G air, it is coated in the oxide layer 18. In other words, the air gap G air at the first cavity 171 is covered by the first oxidizing portion 181 and the second oxidizing portion 182.
再者,進行一非等向性蝕刻步驟(例如,乾蝕刻或濕蝕刻)以移除部分的氧化層(以移除不當覆蓋氮化層111的氧化物部分),因而暴露出氮化層111,如第6A圖所示。 Furthermore, an anisotropic etching step (for example, dry etching or wet etching) is performed to remove a portion of the oxide layer (to remove the oxide portion of the nitride layer 111 improperly), thereby exposing the nitride layer 111. As shown in Figure 6A.
一實施例中,各氣隙Gair係被氧化層18完全地包覆,如第6A圖所示。第6A圖中,氣隙Gair係與相鄰兩該些氮化層111相隔開一距離,且具有一紡錘型剖面(spindle-shaped cross-section)。一實施例中,氣隙Gair的紡錘型剖面例如是具有相交之一短軸aX(垂直於基板10)和一長軸aL(平行於基板10)。再者,一實施例中,氣隙Gair可實質上位於氧化層18的中央。 In one embodiment, each air gap G air is completely covered by the oxide layer 18, as shown in FIG. 6A. In Fig. 6A, the air gap G air is spaced apart from the adjacent two nitride layers 111 by a distance and has a spindle-shaped cross-section. In one embodiment, the spindle-shaped profile of the air gap G air has , for example, one of a short axis a X (perpendicular to the substrate 10) and a long axis a L (parallel to the substrate 10). Moreover, in an embodiment, the air gap G air may be substantially located in the center of the oxide layer 18.
之後,透過線性圖案16的線性間距將氮化層111置換為導電層(例如包括金屬層)。如第7圖所示,進行氮化層111之移除步驟;例如,利用浸置在熱磷酸溶液(H3PO4)中的方式,將氮化層111完全地移除,而形成多個第二空腔(second cavities)172,因而暴露出通道孔13和氧化層18。 Thereafter, the nitride layer 111 is replaced by a conductive layer (for example, including a metal layer) through the linear pitch of the linear pattern 16. As shown in FIG. 7, the step of removing the nitride layer 111 is performed; for example, the nitride layer 111 is completely removed by immersion in a hot phosphoric acid solution (H 3 PO 4 ) to form a plurality of layers. Second cavities 172, thereby exposing the via holes 13 and the oxide layer 18.
接著,如第8A圖所示,形成導電層19於該些第二空腔172以完成氮化層111的置換。類似地,導電層19係以化學乾式蝕刻(chemical dry etching,CDE)或濕蝕刻(非等向性蝕刻)進行圖案化,以回拉(pull back)導電層19之側壁,因而避免相鄰導電層19之間有不必要的連結(造成短路)。於垂直通道式 (VC)半導體元件之應用中,導電層19可做為字元線。再者,於第8A圖中,具紡錘型剖面之氣隙Gair具有一最大長度Lair垂直於基板10(亦即,最大長度Lair係平行於Z-方向),且氣隙Gair係與相鄰兩導電層19相隔開一距離Li。於一實施例中,最大長度Lair大於距離Li;例如,最大長度Lair相對於距離Li之一比值係等於2或大於2。如第8A圖所示,對於一氧化層18而言,氧化材料的長度(Li)和氣隙Gair的長度(Lair)例如可表示為:Li:Lair:Li=,1:2:1。 Next, as shown in FIG. 8A, a conductive layer 19 is formed in the second cavities 172 to complete the replacement of the nitride layer 111. Similarly, the conductive layer 19 is patterned by chemical dry etching (CDE) or wet etching (non-isotropic etching) to pull back the sidewalls of the conductive layer 19, thereby avoiding adjacent conduction. There is an unnecessary connection between layers 19 (causing a short circuit). In the application of vertical channel (VC) semiconductor components, the conductive layer 19 can be used as a word line. Furthermore, in FIG. 8A, the air gap G air having the spindle profile has a maximum length L air perpendicular to the substrate 10 (ie, the maximum length L air is parallel to the Z-direction), and the air gap G air system The adjacent two conductive layers 19 are separated by a distance L i . In one embodiment, the maximum length L air is greater than the distance L i ; for example, the ratio of the maximum length L air to the distance L i is equal to 2 or greater than 2. As shown in FIG. 8A, for the oxide layer 18, the length (L i ) of the oxidized material and the length (L air ) of the air gap G air can be expressed, for example, as: L i : L air : L i =, 1: 2:1.
再者,各導電層19例如是一多層構型(multi-layered configuration)。第8B圖係為根據一實施例之第8A圖中一第二空腔內之導電層19的一局部放大圖。一實施例中,第二空腔172內之導電層19可包括一高介電常數之介電內襯層(high-k dielectric liner film)191(例如:氧化鋁(AlOx)或氧化鉿(HfOx))於第二空腔172內;一氮化鈦(titanium nitride,TiN)層192沉積於第二空腔172內並沿著高介電常數之介電內襯層191而沉積;以及一金屬鎢(W)層193填滿第二空腔172內之剩餘空間。導電層19之金屬鎢層193可降低字元線電阻。 Furthermore, each of the conductive layers 19 is, for example, a multi-layered configuration. Figure 8B is a partial enlarged view of the conductive layer 19 in a second cavity in Figure 8A, in accordance with an embodiment. In one embodiment, the conductive layer 19 in the second cavity 172 may include a high-k dielectric liner film 191 (eg, aluminum oxide (AlOx) or hafnium oxide (HfOx). )) in the second cavity 172; a titanium nitride (TiN) layer 192 is deposited in the second cavity 172 and deposited along the high dielectric constant dielectric liner 191; and a metal The tungsten (W) layer 193 fills the remaining space within the second cavity 172. The metal tungsten layer 193 of the conductive layer 19 can reduce the word line resistance.
根據上述實施例提出三維堆疊半導體結構之製造方法,所製得之一三維堆疊記憶體結構的一陣列區域中,一圖案化多層堆疊包括多個具有氣隙的絕緣層(例如氧化層18)和導電層(例如導電層19)交替堆疊可形成於一基板上方。由於三維堆疊記憶體結構的陣列區域是大面積區域,氣隙的存在可以減少三維堆 疊記憶體結構的重量,使作為支撐柱體的通道孔結構(例如包括ONO層和多晶矽通道層)在三維堆疊記憶體結構的製程中可以支撐更多的疊層。再者,氣隙Gair的存在可降低疊層之相鄰導電層19之間的電容(氧化物之介電常數為3.9,空氣之介電常數為1),因而增進應用本揭露之三維堆疊記憶體結構的電子特性。再者,實施例方法不會對結構中的相關元件和層造成損傷。實施例方法特別適合用於製造具有高和細的支撐柱體(例如通道孔)或疊層數目很多的三維堆疊記憶體結構,且製得的結構具有穩固的架構(因絕緣層重量減少,造成對支撐柱體較少的重量負載)、相關元件和層具有完整構型以及可提供三維堆疊記憶體結構穩定的電子特性。再者,實施例之三維堆疊記憶體結構係採用不費時和非昂貴之製程進行製作,十分適合量產。 According to the above embodiment, a method for fabricating a three-dimensional stacked semiconductor structure is provided. In an array region of a three-dimensional stacked memory structure, a patterned multilayer stack includes a plurality of insulating layers (eg, oxide layer 18) having an air gap and An alternating stack of conductive layers (eg, conductive layers 19) may be formed over a substrate. Since the array area of the three-dimensional stacked memory structure is a large area, the presence of the air gap can reduce the weight of the three-dimensional stacked memory structure, and the channel hole structure (for example, including the ONO layer and the polysilicon channel layer) as the support cylinder is stacked in three dimensions. More stacks can be supported in the process of memory structure. Furthermore, the presence of the air gap G air reduces the capacitance between adjacent conductive layers 19 of the stack (the dielectric constant of the oxide is 3.9, and the dielectric constant of air is 1), thereby enhancing the three-dimensional stacking of the present application. The electronic properties of the memory structure. Moreover, the embodiment methods do not cause damage to related components and layers in the structure. The embodiment method is particularly suitable for fabricating a three-dimensional stacked memory structure having a high and thin support pillar (such as a via hole) or a large number of laminates, and the resulting structure has a stable structure (due to a reduction in the weight of the insulating layer) The weight loading of the support cylinders, the associated components and layers have a complete configuration and provide stable three-dimensional stacked memory structure electronic properties. Furthermore, the three-dimensional stacked memory structure of the embodiment is fabricated in a time-consuming and non-expensive process, and is very suitable for mass production.
如上述圖示之結構和步驟,是用以敘述本揭露之部分實施例或應用例,本揭露並不限制於上述結構和步驟之範圍與應用態樣。其他不同結構態樣之實施例,例如不同內部組件的已知構件都可應用,其示例之結構和步驟可根據實際應用之需求而調整。因此圖示之結構僅為舉例說明之用,而非限制之用。通常知識者當知,應用本揭露之相關結構和步驟過程,例如三維堆疊半導體結構中於陣列區域的相關元件和層的排列方式,或氣隙的形狀與相對位置,或步驟細節等,都可能以依實際應用樣態所需而可能有相應的調整和變化。 The structures and steps of the above-described embodiments are used to describe some embodiments or application examples of the disclosure, and the disclosure is not limited to the scope and application of the above structures and steps. Embodiments of other different structural aspects, such as known components of different internal components, may be applied, and the structures and steps of the examples may be adjusted according to the needs of the actual application. Therefore, the structures shown in the drawings are for illustrative purposes only and are not limiting. It is generally known to those skilled in the art to apply the related structures and steps of the present disclosure, such as the arrangement of elements and layers in the array region in a three-dimensional stacked semiconductor structure, or the shape and relative position of the air gap, or step details, etc. There may be corresponding adjustments and changes depending on the actual application.
綜上所述,雖然本發明已以實施例揭露如上,然其 並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In summary, although the invention has been disclosed above by way of example, It is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
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US20160086972A1 (en) * | 2014-08-26 | 2016-03-24 | SanDisk Technologies, Inc. | Monolithic three-dimensional nand strings and methods of fabrication thereof |
US20170077117A1 (en) * | 2015-09-14 | 2017-03-16 | Sri Sai Sivakumar Vegunta | Three dimensional memory device having isolated periphery contacts through an active layer exhume process |
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US20130062681A1 (en) * | 2011-09-12 | 2013-03-14 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing the same |
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US20140264525A1 (en) * | 2013-03-12 | 2014-09-18 | SanDisk Technologies, Inc. | Vertical nand and method of making thereof using sequential stack etching and landing pad |
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