TWI692038B - Three-dimensional stacked semiconductor device and method of manufacturing the same - Google Patents

Abstract

A three-dimensional stacked semiconductor device includes a patterned multi-layered stacks formed in an array area of a substrate, wherein one of the patterned multi-layered stacks includes insulating layers and conductive layers arranged alternately, and a top gate layer is disposed above the conductive layers; a vertical channel structure disposed between the patterned multi-layered stacks and comprising a tunneling layer on the patterned multi-layered stacks and a channeling layer on the tunneling layer, wherein lateral sides of the top gate layer of one patterned multi-layered stack directly contact the tunneling layer; and discrete confined structures formed in recess regions adjacent to sidewalls of the conductive layers of the patterned multi-layered stacks, wherein one discrete confined structure includes a blocking layer formed as a liner in the recess region and a charge chapping element in contact with the blocking layer and the tunneling layer.

Description

Three-dimensional stacked semiconductor device and manufacturing method thereof

The present invention relates to a three-dimensional stacked semiconductor device and a method for manufacturing the same, and in particular to a uniform storage surface of a three-dimensional stacked semiconductor device and a method for manufacturing the same.

A great feature of the design of non-volatile memory devices is that when the memory device loses or removes power, it can still preserve the integrity of the data state. Many different types of non-volatile memory devices have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cell planes to achieve memory devices with higher storage capacity. For example, some three-dimensional stacked NAND flash memory devices have been proposed. However, the conventional three-dimensional stacked memory device still has some problems to be solved.

For example, for a three-dimensional stacked anti-gate memory device, especially for a structure in which a charge trapping layer extends in a direction in which multiple conductive layers and multiple insulating layers are alternately stacked, an unbroken charge trapping layer (such as nitrogen Layer) is an important issue for the storage time (Retention) of the memory device. According to the traditional manufacturing method of manufacturing three-dimensional stacked memory devices, poly pull-back It is a common step to make confined structures. However, its disadvantage is that the recessed area used to form the confined structure has an uneven amount of recession, thus causing the side walls of the confined structure and the surface of the charge trapping layer to appear wavy, which further affects the electrical performance of the three-dimensional stacked memory device.

The invention relates to a three-dimensional stacked semiconductor device and a manufacturing method thereof. According to the manufacturing method of the embodiment, a semiconductor device is provided that includes elements or layers with uniform surfaces, thereby improving the reliability of electrical performance of a three-dimensional stacked memory device.

According to an embodiment, a three-dimensional stacked semiconductor device is proposed, including: a substrate having an array area and a staircase area; a plurality of patterned multi-layered stacks are formed on Above the substrate and in the array area, and the patterned multilayer stacks are spaced apart from each other, wherein one of the patterned multilayer stacks includes a plurality of insulating layers and a plurality of conductive layers alternately arranged, and a top A top gate layer is formed above the conductive layer; a vertical channel structure is located between the patterned multilayer stacks, and the vertical channel structure includes a tunneling layer formed on the patterned A multi-layer stack and a channeling layer are formed on the tunneling layer, wherein the lateral sides of the top gate layer of one of the aforementioned patterned multi-layer stacks directly contact the tunneling layer; and the separated confinement structure (discrete confined structures), formed in the conductive layer adjacent to the patterned multilayer stack The recessed regions of the sidewalls, and the separate confinement structures each include a blocking layer lined in the recessed region and a charge chapping element and blocking layer Contact with the tunneling layer.

According to an embodiment, a method for manufacturing a three-dimensional stacked semiconductor device is proposed, including: forming a plurality of patterned multilayer stacks above a substrate and within an array region of the substrate, wherein the patterned multilayer stacks are spaced apart from each other, and Channel holes are formed between adjacently arranged patterned multilayer stacks. One of the patterned multilayer stacks includes a plurality of insulating layers and a plurality of conductive layers alternately arranged; the aforementioned one of the patterned multilayer stacks A top gate layer is formed above the conductive layer, and a plurality of separate confinement structures are formed in the recessed regions adjacent to the sidewalls of the conductive layers of the patterned multilayer stack, wherein each separate confinement structure includes a barrier Layer lining is formed in the recessed area and a charge trapping element is in contact with the barrier layer; and forming a vertical channel structure on the patterned multilayer stack, wherein the vertical channel structure includes a tunneling layer disposed on the patterned multilayer stack and a The channel layer is formed on the tunneling layer; wherein the side of the top gate layer of one of the patterned multilayer stacks directly contacts the tunneling layer.

In order to have a better understanding of the above and other aspects of the present invention, the following examples are specifically described in conjunction with the accompanying drawings as follows:

10: substrate

11M: Multi-layer stack

11M’: stacked cylinders

11MP: patterned multilayer stack

111: Insulation

111 _L : the lowest insulating layer

111 _U : uppermost insulating layer

111 _Ua : upper surface of the uppermost insulating layer

112: conductive layer

112 _B : the first conductive layer

112 _WL : second conductive layer

112S1: First side wall

111S2: second side wall

12: Hole

H _C : channel hole

13: sunken area

A _A : Array area

A _S : stepped area

140: barrier film

150: charge trapping membrane

1120: Top conductive film

112T: top gate layer

112T-S: the side of the top gate layer

S _C : Separated limited structure

14: barrier

15: charge trapping element

151S: The side of the charge trapping element

16: Tunneling layer

17: channel layer

18: Dielectric layer

t1: first thickness

t2: second thickness

t3: third thickness

W _R : width of the recessed area

W1: first width

W2: second width

D1: First direction

D2: Second direction

FIGS. 1A-1I illustrate a method of manufacturing a three-dimensional stacked semiconductor device according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a three-dimensional stacked semiconductor device according to an embodiment of the invention.

In the embodiment disclosed herein, a three-dimensional stacked semiconductor device and a manufacturing method thereof are proposed. According to the manufacturing method of the embodiment, data storage structures of a three-dimensional stacked semiconductor device, for example, including the blocking layers, charge chapping elements, and tunneling layer, which It has uniform surfaces, and can solve the problem of generating a wavy surface in the data storage structure in the conventional three-dimensional stacked semiconductor device. In one embodiment, before forming a top conductive film (the top conductive layer is made into a top selection gate in a later step), a charge trapping film is deposited to fill the pattern Patterned multi-layered stacks, and then perform a removal process (such as an etching step) to isolate the charge trapping elements, and the recessed areas adjacent to the sidewalls of the conductive layers of the patterned multi-layer stack Recessed regions form confined structures. Therefore, no confinement structure is formed adjacent to the side of the top conductive layer of the embodiment. The manufacturing method of the embodiment can make a device with a uniform and uniform surface of the device, thereby improving the reliability of the electrical performance of the three-dimensional stacked memory device. Furthermore, the embodiment method does not cause damage to the relevant layers and components in the device, and the embodiment method also The three-dimensional stacked memory device suitable for manufacturing a large number of stacked layers does not affect the configuration of the device of the embodiment.

The disclosed embodiments are widely used, and can be used in many three-dimensional stacked semiconductor devices. For example, the embodiment can be applied to a three-dimensional vertical-channel (VC) type semiconductor device, but the disclosure is not limited to this application. The following are related embodiments, which are illustrated in detail to illustrate the three-dimensional stacked semiconductor device and the manufacturing method thereof provided in the present disclosure. However, this disclosure is not limited to this. The descriptions in the embodiments, such as detailed structure, process steps, material application, etc., are for illustrative purposes only, and the scope of protection to be disclosed in the present disclosure is not limited to the described state.

It should be noted that this disclosure does not show all possible embodiments, and those skilled in the relevant arts can change and modify the structure and process of the embodiments without departing from the spirit and scope of this disclosure to meet the needs of practical applications. Therefore, other implementations not mentioned in this disclosure may also be applicable. Furthermore, the drawings have been simplified to clearly explain the contents of the embodiments, and the size ratios on the drawings are not drawn according to the actual products. Therefore, the description and illustrations are only used to describe the embodiments, not to limit the scope of disclosure of the present disclosure.

In addition, the ordinal numbers used in the specification and the request items, such as "first", "second", "third", etc., are used to modify the element of the request item, which does not mean and represent the request element itself. The presence of any previous ordinal numbers does not mean the order of a request element and another request element, or the order of manufacturing method. The use of these ordinal numbers is only to enable a request element with a certain name to phase Request elements with the same name can be clearly distinguished.

FIGS. 1A-1I illustrate a method of manufacturing a three-dimensional stacked semiconductor device according to an embodiment of the invention. As shown in FIG. 1A, a multi-layered stack 11M is formed on a substrate 10, and the substrate 10 has an array area A _A and a staircase area A _S , The multi-layer stack 11M includes a plurality of insulating layers 111 and a plurality of conductive layers 112 alternately stacked along a second direction D2 (eg, Z direction) perpendicular to one of the substrates 10. In one embodiment, the insulating layer 111 is, for example, an oxide layer, and the conductive layer 112 is, for example, a polysilicon layer (for example, an N-type heavily doped polysilicon layer or a P-type heavily doped polysilicon layer).

In an example (but not limited to), the conductive layer 112 of one of the multilayer stacks 11M in the array area A _A of the substrate 10 includes a plurality of first conductive layers 112 _B and a plurality of second conductive layers Layer 112 _WL . In one example, the first conductive layer 112 _{B is} formed on the substrate 10 and serves as a bottom gate layer, and the second conductive layer 112 _{WL is} formed on the first conductive layer 112 _B as a device For the character line.

After that, the multilayer stack 11M is patterned, for example, by etching to form a plurality of holes 12, as shown in FIG. 1B. In an example, the hole 12 extends downward and passes through the second conductive layer 112 _WL and the first conductive layer 112 _B , and exposes a bottommost insulating layer 111 _L (for example, a buried oxide layer is formed on the substrate 10) .

As shown in FIG. 1C, the conductive layer 112, including the first conductive layer 112 _B and the second conductive layer 112 _WL , is recessed inward relative to the insulating layer 111 to form a plurality of stacked pillars 11M′ It extends vertically on the substrate 10. Therefore, the side walls of the conductive layer 112 adjacent to the stacked pillars 11M′ form the recessed area 13. In one embodiment, the conductive layer 112 has first sidewalls 112S1, and the insulating layer 111 has second sidewalls 111S2, wherein the first sidewalls 112S1 are relatively recessed in the second sidewalls 111S2 to define the concave regions 13.

In addition, the degree of depression of the depression region 13 can be determined and modified according to actual application requirements. In an example, the recessed region 13 has a width W _R parallel to a first direction D1 (the X direction shown in FIG. 1C), where the width W _R may be less than or approximately equal to the remaining conductive layer after the recess step The width of 112 (for example, the second width W2 shown in FIG. 1I). However, this disclosure is not limited to this. Furthermore, one of the first conductive layers 112 _B has a first thickness t1 (along the second direction D2; for example, Z-direction), and one of the second conductive layers 112 _WL has a second thickness t2; In an example, the first thickness t1 is substantially equal to the second thickness t2, but the disclosure is not limited thereto.

Afterwards, a blocking film 140 is deposited to form blocking liners in the recessed regions 13; and a charge chapping film 150 is deposited on the blocking film 140, wherein the charge trapping film 150 Completely fill the space between the stacked pillars 11M′, for example, completely fill the space between the opposing two liner portions of the barrier film 140 at the stacked pillars 11M′, as in the 1D The picture shows. Furthermore, the barrier film 140 and the charge trapping film 150 formed thereon cover the uppermost insulating layer 111 _U.

The barrier film 140 may be a combination including multiple layers to optimize erase saturation. For example, the multilayer film layer may include material layers such as high dielectric constant (higher dielectric constant than silicon dioxide), capped SiN, and double-trapped BE-SONOS (Energy gap engineering silicon-oxide-nitride-oxide-silicon) ONO (oxide-nitride-oxide). In an example, the material of the charge trapping film 150 generally includes silicon nitride (SiN). In other examples, the charge trapping film 150 may include SiON, HfO ₂ , Al ₂ O ₃ and so on. In the example illustration of the embodiment, an integration layer is shown to represent the charge trapping film 150 to simplify the illustration and facilitate clear explanation.

Then, the charge trapping film 150 is etched back to expose the upper surface 111 _{Ua of} the uppermost insulating layer 111 _U , as shown in FIG. 1E. As shown in FIG. 1F, a top conductive film 1120 is formed on the charge trapping film 150, the barrier film 140, and the stacked pillars 11M'. And, another insulating layer 111 is deposited over the top conductive film 1120 to cover the top conductive film 1120.

Then, as shown in FIG. 1G, a portion of the top conductive film 1120 is removed, a portion of the charge trapping film 150 between the stacked pillars, and the portion of the barrier film 140 are removed to form a plurality of channels Holes H _{C. The} channel holes H _C expose the sidewalls of the insulating layer 111 (that is, the second sidewall 111S2 ). The channel holes H _C extend along the second direction D2 (eg, Z-direction) and are perpendicular to the substrate One of 10 extends the direction of the plane. Therefore, a plurality of patterned multilayer stacks 11MP are thus formed on the substrate 10.

Referring to FIGS. 1F and 1G, according to an embodiment, in the array area A _A of the substrate 10, some portions of the top conductive film 1120, the portion of the charge trapping film 150 between the stacked pillars and the barrier film The part of 140 can be removed in one step, for example, by a single etching step, thereby forming a top gate layer 112T above the conductive layer 112, and forming a discrete confined structure structures) S _C 11MP stacked sidewall conductive layer 112 adjacent to the plurality of patterned multilayer (e.g., the first side wall 112S1) recessed area 13. Furthermore, the formed via hole H _C exposes the bottommost insulating layer 111 _L (for example, a buried oxide layer is formed on the substrate 10 ). In one example, the top conductive film 1120 shown in FIG. 1F extends along the first direction D1 (for example, X-direction) in the extension plane of the substrate 10, and the etching step is shown in FIG. 1G through the edge The relevant material layer is cut in the second direction D2 (for example, Z-direction). The second direction D2 is perpendicular to the first direction D1. According to an embodiment, the patterned multilayer stack 11MP has uniform profiles, that is, the relevant elements of the patterned multilayer stack 11MP (such as the top gate layer 112T, the conductive layer 112, and the insulating layer 111) do not form waves Shaped side surface.

Further, after the single etching step, based on the recessed areas 13 form separate structural limitations (discrete confined structures) S _C, as shown on FIG. 1G, wherein the plurality of separate structural limitations S _C to the insulation between the lines Layer 111 is isolated from each other. In one example, each separated limitations structure S _C lines include 14 is formed like a liner (Liner) a barrier layer (blocking layer) to 13, and a charge trapping element (charge chapping element) recessed region 15 on the barrier layer 14 In between, the charge trapping element 15 is in contact with the barrier layer 14.

After forming the via hole H _C , a tunneling layer 16 is deposited on the patterned multilayer stack 11MP and covers the patterned multilayer stack 11MP, as shown in FIG. 1H. The tunnel layer 16 is deposited along the sidewalls of the patterned multilayer stack 11MP. Then, a channeling layer 17 is formed on the tunneling layer 16. In FIG. 1H, the top gate layer 112T of each patterned multilayer stack 11MP is buried in the tunneling layer 16. According to an embodiment, the tunneling layer 16 directly contacts the lateral sides 112T-S of the top gate layer 112T of the patterned multilayer stack 11MP. In FIG. 1H, for example, the two opposite sides 112T-S of the top gate layer 112T completely contact the tunnel layer 16 and are completely covered by the tunnel layer 16. Further, in the embodiment, the side wall 16 in direct contact with the patterned multilayer stack 11MP tunneling layer of the insulating layer 111 (i.e., a second side wall 111S2), and in direct contact limitations separation structure S _C; e.g., tunneling layer 16 The side surface 151S of the charge trapping element 15 is directly contacted.

In one embodiment, the tunneling layer 16 may include a bandgap engineered composite tunneling dielectric layer (bandgap engineered composite tunneling dielectric layer), which includes a silicon dioxide layer. In an example (but not limited to this), the composite tunneling dielectric layer is composed of an ultra-thin silicon oxide layer, an ultra-thin silicon nitride layer, and an ultra-thin silicon oxide layer. Furthermore, in one embodiment, the channel layer 17 includes polysilicon, for example.

After that, a dielectric layer 18 is deposited on the pattern On the multi-layer stack 11MP, and the dielectric layer 18 fills the remaining space between the adjacent patterned multi-layer stack 11MP, as shown in FIG. 1I. In one example, the dielectric layer 18 contacts the channel layer 17 between the patterned multilayer stack 11MP. In an example, the dielectric layer 18 may include oxide.

FIG. 2 is a schematic diagram of a three-dimensional stacked semiconductor device according to an embodiment of the invention. FIG. 2 only shows a configuration of a three-dimensional stacked semiconductor device formed in the array area A _A of the substrate 10 for clear description. In FIG. 2, a plurality of patterned multilayer stacks 11MP in the array area A _A are formed above the substrate 10, and the patterned multilayer stacks 11MP are spaced apart from each other. One of the patterned multi-layer stack 11MP includes a plurality of insulating layers 111 and a plurality of conductive layers 112 arranged alternately, and a top gate layer 112T is formed above the conductive layers 112. Furthermore, a vertical channel structure is disposed between the patterned multilayer stack 11MP, wherein the vertical channel structure includes a tunneling layer 16 formed on the patterned multilayer stack 11MP, and a channel layer 17 formed on On the tunneling layer 16. In the embodiment, the side 112T-S of the top gate layer 112T of one of the patterned multilayer stacks 11MP directly contacts the tunneling layer 16. Further, in the embodiment of the three-dimensional stacked semiconductor device of the embodiment, the isolated structure S _C-based limitations recessed region formed adjacent to the patterned multilayer stack sidewalls (i.e., a first side wall 112S1) 11MP 112 of the conductive layer 13, and each limitations isolated structure S _C comprises 13 lines, and in contact with the recessed area comprises a charge trapping element (charge chapping element) 15 and the barrier layer 14 and the tunneling layer 16 is formed of a barrier 14 such as a liner layer (blocking layer). In an example, the data storage structures of the three-dimensional stacked semiconductor device of an embodiment include a barrier layer 14, a charge trapping element 15 and a tunneling layer 16.

In FIG. 2, the barrier layer 14 can be regarded as being formed between two adjacent insulating layers 111. Furthermore, the separated charge limited structure S _C of the catch element 15 is also provided spaced apart along a second direction D2 (e.g. the Z direction). According to the manufacturing method of the embodiment, patterned multilayer stack on top of the gate layer and the separation 112T 11MP limitations structure S _C may be formed at the same time; for example, using the same etching step simultaneously formed, as shown on FIG. 1G. Therefore, the side surface 112T-S of the top gate layer 112T of the patterned multilayer stack 11MP is substantially flush with the side surface 151S of the charge trapping element 15.

Furthermore, according to the device manufactured by the method of the embodiment, the top conductive layer 112T of one of the patterned multilayer stacks 11MP has a first width W1 parallel to the first direction D1 (eg X-direction), The conductive layer 112 of the patterned multilayer stack 11MP (stacked along the second direction D2 such as the Z-direction) has a second width W2 parallel to the first direction D1. The first width W1 is greater than the second width W2. In an exemplary (but non-limiting) configuration of the conductive layer 112 and the top conductive layer 112T, one of the first conductive layers 112 _B has a first thickness t1 (along the second direction D2; for example, Z- Direction), one of the second conductive layers 112WL has a second thickness t2 (along the second direction D2), wherein the first thickness t1 is substantially equal to the second thickness t2, and the first thickness t1 or the second thickness t2 It is substantially smaller than the thickness t3 of the top gate layer 112T (along the second direction D2).

According to the above embodiment, a three-dimensional stacked semiconductor device and a manufacturing method thereof are proposed. In one embodiment, a top conductive film is formed Before (the top conductive layer was made into the top selective gate in the next step), a charge trapping layer was deposited to fill the area between the patterned multi-layered stacks, and then the removal process was performed ( For example, an etching step) to isolate the charge trapping elements and form confined structures in the recessed regions adjacent to the sidewalls of the conductive layers of the patterned multilayer stack. Therefore, no confinement structure is formed adjacent to the side of the top conductive layer of the embodiment. According to a method for manufacturing a three-dimensional stacked semiconductor device according to an embodiment, data storage structures of the three-dimensional stacked semiconductor device include, for example, a barrier layer 14, a charge trapping element 15, and a tunneling layer 16 (as shown in FIG. 2) It has a uniform surface, and can solve the problem of generating a wavy surface in the data storage structure in the conventional three-dimensional stacked semiconductor device. Therefore, the manufacturing method of the embodiment can make a device with a device having a uniform and uniform surface, thereby improving the reliability of the electrical performance of the three-dimensional stacked memory device. Furthermore, the embodiment method does not cause damage to related layers and components in the device, and the embodiment method is also suitable for manufacturing a three-dimensional stacked memory device with a large number of stacked layers without affecting the configuration of the device of the embodiment (i.e. , The device of the embodiment has a stable architecture, and the related components and layers have a complete configuration). Furthermore, the three-dimensional stacked memory device of the embodiment is manufactured by a time-consuming and non-expensive process, which is very suitable for mass production.

The structures and steps shown above are used to describe some embodiments or application examples of the present disclosure, and the present disclosure is not limited to the scope and application of the above structures and steps. Other embodiments of different structural aspects, such as known components of different internal components, can be applied, and the example structure and steps can be based on actual application requirements. Adjustment. Therefore, the illustrated structure is for illustrative purposes only, not for limitation. Generally, the knowledgeable person knows that the related structures and steps of the present disclosure, such as the arrangement or configuration of related elements and layers in the array area in the three-dimensional stacked semiconductor device, or the details of the manufacturing steps, etc., may be based on the actual application. There may be corresponding adjustments and changes required by the state.

In summary, although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application.

10: substrate

11MP: patterned multilayer stack

111: Insulation

111 _L : the lowest insulating layer

111 _U : uppermost insulating layer

112: conductive layer

112 _B : the first conductive layer

112 _WL : second conductive layer

112S1: First side wall

111S2: second side wall

H _C : channel hole

112T: top gate layer

112T-S: the side of the top gate layer

S _C : Separated limited structure

14: barrier

15: charge trapping element

151S: The side of the charge trapping element

16: Tunneling layer

17: channel layer

18: Dielectric layer

W1: first width

W2: second width

t1: first thickness

t2: second thickness

t3: third thickness

D1: First direction

D2: Second direction

Claims (10)

A three-dimensional stacked semiconductor device includes: a substrate having an array area and a staircase area; a bottommost insulating layer formed on the substrate; a plurality of patterned multi-layer stacks (patterned multi- layered stacks) are formed above the bottom-most insulating layer and within the array area, and the patterned multilayer stacks are spaced apart from each other, wherein one of the patterned multilayer stacks includes a plurality of insulating layers and a plurality of insulating layers Conductive layers are alternately arranged, and a top gate layer is formed above the conductive layers; a vertical channel structure is located between the patterned multilayer stacks And the vertical channel structure includes a tunneling layer formed on the patterned multilayer stacks and a channeling layer formed on the tunneling layer, wherein the patterned multilayer stacks are one of the aforementioned The lateral sides of the top gate layer directly contact the tunneling layer, wherein a bottom surface of the tunneling layer directly contacts the bottommost insulating layer; and separate confined structures (discrete confined structures) are Formed in recessed regions adjacent to the sidewalls of the conductive layers of the patterned multilayer stacks, and the separate confinement structures each include a blocking layer lined in the A charge trapping element is in contact with the barrier layer and the tunneling layer in the recessed area. The three-dimensional stacked semiconductor device as described in item 1 of the patent application range, wherein the conductive layers and the insulating layers of the patterned multilayer stacks have first sidewalls and second sidewalls, respectively And the first side walls are relatively recessed in the second side walls to define the recessed areas. The three-dimensional stacked semiconductor device as described in item 1 of the scope of the patent application, wherein the tunneling layer directly contacts the sidewalls of the insulating layers of the patterned multilayer stacks. The three-dimensional stacked semiconductor device as described in item 1 of the patent application range, wherein the top conductive layer of the aforementioned one of the patterned multilayer stacks has a first width parallel to a first direction, and the patterns The conductive layers of the multi-layer stack are stacked along a second direction, which is perpendicular to the first direction, wherein the patterned multi-layer stack has one of the second widths of the conductive layers ( The second width is parallel to the first direction, and the first width is greater than the second width. The three-dimensional stacked semiconductor device as described in item 1 of the patent application range, wherein the conductive layers of the aforementioned one of the patterned multilayer stacks include: a plurality of first conductive layers formed on the substrate And as a bottom gate layer (a bottom gate layer); and a plurality of second conductive layers (second conductive layers) formed on the first conductive layers; One of the first conductive layers has a first thickness, one of the second conductive layers has a second thickness, and the first thickness is substantially equal to the second thickness. A method for manufacturing a three-dimensional stacked semiconductor device, comprising: forming a bottommost insulating layer on a substrate; forming a plurality of patterned multi-layered stacks above the bottommost insulating layer and an array on the substrate In an array region, wherein the patterned multilayer stacks are spaced apart from each other, and channel holes are formed between the adjacently arranged patterned multilayer stacks, one of the patterned multilayer stacks includes A plurality of insulating layers and a plurality of conductive layers are alternately arranged; a top gate layer is formed above the conductive layers of the aforementioned one of the patterned multilayer stacks And a plurality of discrete confined structures are formed in recessed regions adjacent to the sidewalls of the conductive layers of the patterned multilayer stacks, wherein the discrete confined structures each include A blocking layer is lined in the recessed area and a charge chapping element is in contact with the blocking layer; and a vertical channel structure is formed on the patterned multilayer stacks The vertical channel structure includes a tunneling layer disposed on the patterned multilayer stacks and a channeling layer. layer) is formed on the tunneling layer, wherein a bottom surface of the tunneling layer directly contacts the bottommost insulating layer; wherein the patterned multilayer stacks one of the aforementioned lateral sides of the top gate layer It directly contacts the tunneling layer. The manufacturing method as described in item 6 of the patent application scope, wherein the conductive layers and the insulating layers of the patterned multilayer stacks have first sidewalls and second sidewalls, respectively, and The first side walls are relatively recessed in the second side walls to define the recessed regions. The manufacturing method as described in item 6 of the patent application scope, wherein the top conductive layer of one of the aforementioned patterned multilayer stacks has a first width parallel to a first direction, and the patterned multilayers The stacked conductive layers are stacked along a second direction that is perpendicular to the first direction, wherein the second widths of the conductive layers of the one of the patterned multilayer stacks are parallel to The first direction, and the first width is greater than the second width. The manufacturing method as described in item 6 of the patent application scope, wherein the conductive layers of the patterned multilayer stack of the foregoing one include: a plurality of first conductive layers formed on the substrate and serving as A bottom gate layer (a bottom gate layer); and a plurality of second conductive layers (second conductive layers) formed on the first conductive layers, One of the first conductive layers has a first thickness, one of the second conductive layers has a second thickness, and the first thickness is substantially equal to the second thickness. The manufacturing method as described in item 6 of the patent application range, wherein the step of forming the patterned multilayers stacked on the substrate includes: the insulating layers and the conductive layers are alternately formed on the substrate; The conductive layers are relatively recessed in the insulating layers to form a plurality of stacked pillars on the substrate and the recessed regions are adjacent to the sidewalls of the conductive layers of the stacked pillars Depositing a blocking film (blocking film) to form blocking linings (blocking liners) in the recessed areas; depositing a charge trapping film (charge chapping film) on the blocking film, and the charge trapping film completely fills the Spaces between the stacked pillars; forming a top conductive film on the charge trapping film, the barrier film, and the stacked pillars; and removing a portion of the top conductive film, located on the stacks A portion of the charge trapping film between the pillars and a portion of the barrier film to form the channel holes to expose the sidewalls of the insulating layers, wherein the channel holes are along one perpendicular to the substrate Extend in the direction of the extension plane.

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