CN109801919B - Method for fabricating three-dimensional stacked semiconductor structure and structure fabricated thereby - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 54
- 229920005591 polysilicon Polymers 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000002093 peripheral effect Effects 0.000 claims abstract description 3
- 230000008569 process Effects 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000003475 lamination Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 5
- 230000005641 tunneling Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention discloses a three-dimensional laminated semiconductor structure, comprising: a substrate having an array region and a peripheral region; a plurality of patterned multi-layer stacks are formed above the substrate and in the array region, the patterned multi-layer stacks are spaced from each other, and a plurality of channel holes are formed between the adjacently arranged patterned multi-layer stacks; a charge trapping layer formed on the patterned multi-layer stack and liner-deposited in the via hole; a polysilicon channel layer deposited along the charge trapping layer; and a plurality of conductive pads formed on the polysilicon channel layer and respectively corresponding to the patterned multi-layer stack, wherein the polysilicon channel layer has a first thickness, one of the conductive pads has a second thickness, and the second thickness is greater than the first thickness.
Description
Technical Field
The present invention relates to a method for fabricating a three-dimensional stacked semiconductor structure and a three-dimensional stacked semiconductor structure fabricated by the same, and more particularly, to a method for fabricating a three-dimensional stacked semiconductor structure having thick conductive pads (thick conductive pads).
Background
Non-volatile memory devices have a great feature in their design that preserves the integrity of the data state when the memory device is powered down or removed. Many different types of non-volatile memory devices have been proposed. However, those skilled in the art are still developing new designs or combining the existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, three-dimensional stacked NAND (NAND) type flash memory structures have been proposed. However, there are still some problems to be solved in the conventional three-dimensional stacked memory structure.
For example, in the case of a single gate vertical channel (single gate vertical-channel) type three-dimensional stacked nand-gate flash memory structure, a thin channel must be formed in consideration of device performance. However, the channel is too thin, it may be difficult to form a good contact landing (contact landing) state, and how to balance the channel thickness and the contact landing is one of the manufacturing problems for manufacturers.
Disclosure of Invention
The invention relates to a manufacturing method of a three-dimensional laminated semiconductor structure and a manufactured structure thereof. According to an embodiment, the semiconductor structure has a conductive pad with an increased thickness for contact landing (contact landing), thereby improving reliability of electrical performance of the three-dimensional stacked memory structure.
According to an embodiment, a three-dimensional stacked semiconductor structure is provided, comprising: a substrate having an array region and a peripheral region; a plurality of patterned multi-layered stacks (patterned multi-layered stacks) formed above the substrate and within the array region, the patterned multi-layered stacks being spaced apart from each other, and a plurality of via holes (channels) formed between the adjacently disposed patterned multi-layered stacks; a charge trapping layer (charge trapping layer) formed on the patterned multi-layer stack and liner-deposited in the via holes; a polysilicon channel layer (polysilicon channel layer) deposited along the charge trapping layer; and a plurality of conductive pads (conductive pads) formed on the polysilicon channel layer and respectively corresponding to the patterned multi-layer stack, wherein the polysilicon channel layer has a first thickness, one of the conductive pads has a second thickness, and the second thickness is greater than the first thickness.
According to an embodiment, a method for fabricating a three-dimensional stacked semiconductor structure is provided, comprising: forming a plurality of patterned multi-layer stacks over a substrate and within an array region of the substrate, wherein the patterned multi-layer stacks are spaced apart from each other and a plurality of via holes are formed between adjacently disposed patterned multi-layer stacks; forming a charge-trapping layer on the patterned multi-layer stacks, the charge-trapping layer being liner-deposited in the via hole; forming a polysilicon channel layer over and deposited along the charge-trapping layer; and forming a plurality of conductive pads (conductive pads) on the polysilicon channel layer and corresponding to the patterned multi-layer stacks, wherein the polysilicon channel layer has a first thickness, the conductive pads have a second thickness, and the second thickness is greater than the first thickness.
In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings, in which:
drawings
Fig. 1A to 1H illustrate a method for fabricating a three-dimensional stacked semiconductor structure according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a three-dimensional stacked semiconductor structure according to an embodiment of the invention.
[ notation ] to show
10: a substrate;
11M: a plurality of layers of lamination;
11M': patterning the multilayer stack;
111. 111': an insulating layer;
112. 112': a conductive layer;
113. 113': a bottom oxide layer;
114. 114': a bottom gate layer;
115. 115': burying an oxide layer;
116. 116': a top polysilicon layer;
117. 117': a top oxide layer;
118. 118': a cover layer;
12: a passage hole;
13: a charge trapping layer;
13 a: an upper surface of the charge trapping layer;
14: a polysilicon channel layer;
140: the upper part of the polysilicon channel layer;
15. 15': a dielectric medium layer;
16: a conductive pad;
17: a conductive contact;
t 1: a first thickness;
t 2: a second thickness;
w1: a first width;
w2: a second width;
d1: a first direction;
d2: a second direction.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
In an embodiment of the present disclosure, a method for fabricating a three-dimensional stacked semiconductor structure and a three-dimensional stacked semiconductor structure fabricated by the same are provided. According to an embodiment, the conductive pads (conductive pads) above the patterned multi-layer stacks (patterned multi-layered stacks) are increased in thickness, for example, by a selective epitaxial growth process. Accordingly, the resulting semiconductor structure has a conductive pad with an increased thickness, which solves the problems encountered in conventional processes and structures for making contact landings (contact landings) on thin pads. Therefore, according to the embodiments, a reliable conductive pad structure can be provided, and the conductive pad with the increased thickness can make a conductive contact (such as a conductive contact of a bit line) land well, thereby improving the reliability of the electrical performance of the three-dimensional stacked memory structure. Furthermore, the embodiment methods do not cause damage to related elements and layers in the structure, and the embodiment methods are also suitable for manufacturing a three-dimensional stacked memory structure with a large number of stacked layers without affecting the structural configuration of the embodiment.
Embodiments of the present disclosure have a wide range of applications and can be applied to many processes for three-dimensional stacked semiconductor structures. For example, the embodiments can be applied to a semiconductor device of a three-dimensional vertical-channel (VC) type, but the invention is not limited to this application. The following embodiments are provided to explain in detail the method for fabricating a three-dimensional stacked semiconductor structure and related structures in accordance with the present invention with reference to the accompanying drawings. However, the present invention is not limited thereto. The description of the embodiments, such as detailed structure, process steps, and material applications, is for illustrative purposes only, and the scope of the present invention is not limited to the embodiments described.
It is to be noted that the present invention does not show all possible embodiments, and those skilled in the relevant art can change or modify the structure and process of the embodiments to meet the needs of practical applications without departing from the spirit and scope of the present invention. Thus, other embodiments not set forth herein may also be applicable. Furthermore, the drawings have been simplified to illustrate the content of the embodiments clearly, and the dimensional proportions on the drawings are not drawn to scale according to actual products. Accordingly, the description and drawings are only for the purpose of illustrating embodiments and are not to be construed as limiting the scope of the invention.
Furthermore, the use of ordinal numbers such as "first," "second," "third," etc., in the specification and in the claims to modify a corresponding element, is not intended to imply any previous order to the element, nor is the order in which an element may be sequenced or a method of manufacture.
Fig. 1A to 1H illustrate a method for fabricating a three-dimensional stacked semiconductor structure according to an embodiment of the invention. As shown in fig. 1A, a multi-layered stack 11M is formed on a substrate 10, and the multi-layered stack 11M includes a plurality of insulating layers (insulating layers)111 and a plurality of conductive layers (conductive layers)112 alternately stacked along a second direction D2 (e.g., Z direction) perpendicular to the substrate 10. In one embodiment, the insulating layer 111 is, for example, an oxide layer (oxide layers), and the conductive layer 112 is, for example, a polysilicon layer (e.g., an N-type heavily doped polysilicon layer or a P-type heavily doped polysilicon layer).
In one example, but not limited thereto, the three-dimensional stacked semiconductor structure may further include a buried oxide layer (buried oxide layer)115 formed on the substrate 10, a bottom gate layer (e.g., serving as an inversion gate) 114 formed on the buried oxide layer 115, and a bottom oxide layer (bottom oxide layer)113 formed on the bottom gate layer 114, and the multi-layer stack 11M formed on the bottom oxide layer 113, as shown in fig. 1A. Further, in an example, but not by way of limitation, a top polysilicon layer (e.g., a String Select Line (SSL) polysilicon layer) 116 is formed on the multi-layer stack 11M, a top oxide layer (e.g., a string select line oxide (SSL oxide))117 is formed on the top polysilicon layer 116, and a cap layer (e.g., silicon nitride as a Hard Mask (HM))118 is formed on the top oxide layer 117.
Thereafter, the multi-layer stack 11M is patterned, for example, by etching, to form a plurality of via holes (channels) 12 and a plurality of patterned multi-layer stacks (patterned multi-layered stacks) 11M' perpendicular to the substrate 10. As shown in fig. 1B, the plurality of patterned multi-layer stacks 11M' on the substrate 10 are spaced apart from each other. And via hole 12 passes through capping layer 118, top oxide layer 117, top polysilicon layer 116, multi-layer stack 11M, bottom oxide layer 113, and bottom gate layer 114. The via hole 12 extends downward perpendicular to the substrate 10 and stops on the buried oxide layer 115 ' and exposes sidewalls of the insulating layer 111 ' and the conductive layer 112 '.
Thereafter, a charge trapping layer (13) is formed on the patterned multi-layer stack 11M', and the charge trapping layer 13 is deposited along the via hole 12 in a liner configuration, as shown in FIG. 1C. In one embodiment, the charge trapping layer functions as a storage layer and is, for example, an ONO layer or an ONOONOONO layer. For example, the charge trapping layer 13 may include a blocking oxide layer (adjacent to the sidewalls of the insulating layer 111 and the conductive layer 112), a nitride trapping layer (tunneling oxide layer), and a tunneling oxide layer (tunneling oxide layer). In the example drawings of the embodiments, an integration layer is depicted to represent the charge trapping layer 13 for clarity of illustration.
Then, a polysilicon channel layer 14 is formed on the charge trapping layer 13 and deposited along the charge trapping layer 13 (i.e., the polysilicon channel layer 14 is conformally deposited on the charge trapping layer), as shown in FIG. 1D. In one example, the via hole 12 extends downward and stops on the buried oxide layer 115 ', so that the charge trapping layer 13 deposited in the via hole 12 is formed on the buried oxide layer 115 ' and directly contacts the buried oxide layer 115 '; the polysilicon channel layer 14 and the buried oxide layer 115' are thus separated by the charge trapping layer 13.
After depositing the polysilicon channel layer 14 on the charge trapping layer 13, the method of an embodiment may further include: a dielectric layer (e.g., oxide) 15 is deposited over the patterned multi-layer stack 11M' to cover the polysilicon channel layer 14, and the dielectric layer 15 fills the remaining space in the via hole 12, as shown in fig. 1E.
The dielectric layer 15 is then recessed (recessed) to expose an upper portion (top portion)140 of the polysilicon channel layer 14, as shown in fig. 1F. In one embodiment, the dielectric layer 15 is recessed by an etch back (etchback) step.
Then, a plurality of conductive pads (conductive pads)16 are formed on the polysilicon channel layer 14, and the conductive pads are formed on the polysilicon channel layerThe electrical pads 16 correspond to the patterned multi-layer stack 11M', respectively, as shown in fig. 1G. In one embodiment, a selective epitaxial growth process (a selective epitaxial growth process) is applied to grow some of the conductive pads 16 on the polysilicon channel layer 14, and the material of the conductive pads 16 is thus the same as that of the polysilicon channel layer 14. In one example, in a DCS-HCl-H2All together (gas ratio DCS/HCl/H)2200sccm/180sccm/25slm) and a temperature of about 800 deg.c for about 6 minutes (program time for main step) with a silicon loss of about
According to the structure of the embodiment, the polysilicon channel layer 14 has a first thickness (first thickness) t1, and one of the conductive pads 16 has a second thickness (second thickness) t2, wherein the second thickness t2 is greater than the first thickness t 1.
According to one embodiment, the polysilicon channel layer 14 also covers the upper surface 13a of the charge trapping layer 13, and the upper portion 140 of the polysilicon channel layer 14 is formed on the upper surface 13a of the charge trapping layer 13. When a selective epitaxial growth process is applied, epitaxial polysilicon (epi-polysilicon film) is grown only over the upper portion 140 of the polysilicon channel layer 14 to form the conductive pad, and not over other materials such as oxide (i.e., not over the dielectric layer 15).
After the conductive pads 16 are formed, a plurality of conductive contacts (e.g., bit line pads) 17 are formed over the conductive pads 16, wherein the conductive contacts 17 are electrically connected to the corresponding conductive pads 16, as shown in fig. 1H. In an embodiment of a three-dimensional vertical channel semiconductor device, the conductive layer 112 can be used as Word Lines (WLs), the conductive pads 16 as bit line pads (BL pads), and the conductive contacts 17 as bit line contacts (BL contacts).
Fig. 2 is a schematic diagram of a three-dimensional stacked semiconductor structure according to an embodiment of the invention. As shown in fig. 2, the polysilicon channel layer 14 has a first thickness t1, and a conductive pad 16 has a second thickness t2, wherein the second thickness t2 is greater than the first thickness t 1. As shown in fig. 2, a length of the polysilicon channel layer 14 parallel to the first direction D1 (e.g., along the X-direction) can be defined as a first thickness t1, and a length of the conductive pad 16 parallel to the second direction D2 (e.g., along the Z-direction) can be defined as a second thickness t2, wherein the second direction D2 is perpendicular to the first direction D1. Furthermore, according to an embodiment structure as shown in fig. 2, the conductive layer 112 of a patterned multi-layer stack 11M' is configured to have a first width (first width) W1 along the first direction D1, and the conductive pads 16 have a second width (second width) W2 along the second direction D2, wherein the second width W2 is greater than the first width W1.
Furthermore, in an embodiment, a ratio of the second thickness t2 to the first thickness t1 is in a range of 2 to 10, for example, a ratio is in a range of 2 to 5. In one embodiment, the first thickness t1 is, for example, at
To
Within the range of (1). In one embodiment, the second thickness t2 is, for example, at
To
Within the range of (1). In one example (but not limited to this example), when the adjacent conductive pads 16 are spaced apart by about 100nm, the second thickness t2 is about
It should be noted that these values are presented for illustrative purposes and are not intended to limit the scope of the invention.
In addition, the structural configuration of the embodiment application may be slightly different depending on the layer and element requirements required for the actual application. For example, in one example (but not limited to this example), the charge-trapping layer 13 is formed on the capping layer 118, such that for a patterned multi-layer stack, the capping layer 118, the top oxide layer 117, the top polysilicon layer 116, the patterned multi-layer stack 11M', the bottom oxide layer 113, the bottom gate layer 114, and the buried oxide layer 115 are wrapped in the charge-trapping layer 13, as shown in FIG. 2. However, the related elements and layers of the multi-layer stack can be modified and changed according to the structure of the application, and are not limited to the drawings.
According to the method for fabricating a three-dimensional stacked semiconductor structure in accordance with the above embodiments, conductive pads (conductive pads) over a patterned multi-layer stack are increased in thickness, for example, by a selective epitaxial growth process. The structure of the embodiments thus has a conductive pad with an increased thickness, providing a reliable structure for good landing of the associated conductive contact (e.g., of a bitline). In one embodiment, the adjacent conductive pads are kept well isolated because the selective epitaxial growth is performed only on the polysilicon material, not on other materials such as oxide. Therefore, the contact etching can be stopped on the thickened conductive connecting pad (such as the conductive connecting pad of the bit line) without increasing the thickness of the polysilicon channel layer, thereby improving the reliability of the electrical performance of the three-dimensional laminated memory structure. Furthermore, the embodiment methods do not cause damage to related elements and layers in the structure, and the embodiment methods are also suitable for fabricating a three-dimensional stacked memory structure with a large number of stacked layers without affecting the structural configuration of the embodiment (i.e., the structure of the embodiment has a robust architecture, and related elements and layers have a complete configuration). Moreover, the three-dimensional laminated memory structure of the embodiment is manufactured by adopting a non-time-consuming and non-expensive process, and is very suitable for mass production.
The structures and steps disclosed in the above-mentioned figures are used to describe some embodiments or application examples of the present invention, and the present invention is not limited to the scope and application examples of the structures and steps. Other embodiments of different configurations, such as known components of different internal components, may be used, and the illustrated configurations and steps may be modified as desired for the particular application. Accordingly, the structures disclosed in the drawings are illustrative only and not limiting. It will be appreciated by those skilled in the art that the structure and process steps involved in implementing the present invention, such as the arrangement of the elements and layers involved in the array region in a three-dimensional stacked semiconductor structure, or the details of the fabrication steps, may be modified and varied accordingly as desired for a particular application.
While the present invention has been described with reference to the above embodiments, it is not intended to be limited thereto. Those skilled in the art to which the invention pertains will readily appreciate that various modifications and adaptations can be made without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the claims defined by the claims.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A three-dimensional stacked semiconductor structure, comprising:
a substrate having an array region and a peripheral region;
a plurality of patterned multi-layer stacks are formed above the substrate and in the array region, the patterned multi-layer stacks are spaced apart from each other, and a plurality of channel holes are formed between the adjacently arranged patterned multi-layer stacks;
a charge trapping layer formed on the patterned multi-layer stacks and liner-deposited in the via holes;
a polysilicon channel layer deposited along the charge trapping layer; and
a plurality of conductive pads are formed on the polysilicon channel layer and respectively correspond to the patterned multi-layer stacks,
wherein the polysilicon channel layer has a first thickness, one of the conductive pads has a second thickness, and the second thickness is greater than the first thickness; wherein a selective epitaxial growth process is applied to grow the conductive pads on the polysilicon channel layer; the conductive pads correspondingly positioned above each patterned multilayer lamination are aligned with the inner walls of the polysilicon channel layers above the patterned multilayer lamination.
2. The three-dimensional stacked semiconductor structure of claim 1, wherein one of the patterned multi-layer stacks comprises a plurality of insulating layers and a plurality of conductive layers stacked alternately, and one of the conductive pads is formed over a corresponding one of the patterned multi-layer stacks, wherein the conductive layers of the one of the patterned multi-layer stacks has a first width, the one of the conductive pads has a second width, and the second width is greater than the first width.
3. The three-dimensional stacked semiconductor structure of claim 1, wherein a ratio of the second thickness to the first thickness is in a range of 2 to 10.
4. The three-dimensional stacked semiconductor structure of claim 1, wherein the second thickness is within
To
Within a range of (a).
5. A method of fabricating a three-dimensional stacked semiconductor structure, comprising:
forming a plurality of patterned multi-layer stacks over a substrate and within an array region of the substrate, wherein the patterned multi-layer stacks are spaced apart from each other and a plurality of via holes are formed between adjacently disposed patterned multi-layer stacks;
forming a charge-trapping layer on the patterned multi-layer stacks, the charge-trapping layer being liner-deposited in the via holes;
forming a polysilicon channel layer over and deposited along the charge-trapping layer; and
forming a plurality of conductive pads on the polysilicon channel layer and corresponding to the patterned multi-layer stacks respectively,
wherein the polysilicon channel layer has a first thickness, one of the conductive pads has a second thickness, and the second thickness is greater than the first thickness; wherein a selective epitaxial growth process is applied to grow the conductive pads on the polysilicon channel layer; the conductive pads correspondingly positioned above each patterned multilayer lamination are aligned with the inner walls of the polysilicon channel layers above the patterned multilayer lamination.
6. The method of claim 5, wherein one of the patterned multi-layer stacks comprises a plurality of insulating layers and a plurality of conductive layers stacked alternately, the via holes extend downward perpendicular to the substrate to penetrate the insulating layers and the conductive layers, wherein one of the conductive pads is formed above the corresponding one of the patterned multi-layer stacks, wherein the conductive layers of the one of the patterned multi-layer stacks has a first width, the one of the conductive pads has a second width, and the second width is greater than the first width.
7. The method of claim 5, wherein after depositing the polysilicon channel layer over the charge trapping layer, the method further comprises:
depositing a dielectric medium layer on the patterned multi-layer stacks to cover the polysilicon channel layer, and filling the residual space in the channel holes with the dielectric medium layer,
the dielectric medium layer is etched back to expose an upper part of the polysilicon channel layer.
8. The method of claim 5, wherein a ratio of the second thickness to the first thickness is in a range of 2 to 10.
9. The method of claim 5, wherein the second thickness is within
To
Within a range of (a).
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| CN106558590A (en) * | 2015-09-24 | 2017-04-05 | 旺宏电子股份有限公司 | Memory component and its manufacture method |
| CN108666324A (en) * | 2017-03-31 | 2018-10-16 | 旺宏电子股份有限公司 | Memory construction and its manufacturing method |
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| US8796098B1 (en) * | 2013-02-26 | 2014-08-05 | Cypress Semiconductor Corporation | Embedded SONOS based memory cells |
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| CN106558590A (en) * | 2015-09-24 | 2017-04-05 | 旺宏电子股份有限公司 | Memory component and its manufacture method |
| CN108666324A (en) * | 2017-03-31 | 2018-10-16 | 旺宏电子股份有限公司 | Memory construction and its manufacturing method |
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