TWI499038B - Three dimensional gate structures with horizontal extensions - Google Patents

Description

Horizontally extended three-dimensional gate structure

The present invention relates to a stacked transistor structure, for example, for use in a high-density three-dimensional (3D) memory device, and a memory device using the structure.

FIG. 1A is a perspective view of a 3D NAND flash memory device, which is described in a US patent pending co-pending application, application number 13/078,311. This application is hereby incorporated by reference as if fully described. The 3D NAND flash memory device described in FIG. 1A includes a stack of alternating semiconductor lines and insulated lines. The insulated wires are removed to reveal additional structure. For example, the insulated wires between the semiconductor lines in the stack are removed, and the insulated wires between the semiconductor wire stacks are removed.

A multilayer array is formed on the insulating layer, the multilayer array including conforming to a plurality of stacked plurality of word lines 305-1, ..., 325-N. In a multi-layer plane, the plurality of stacks includes semiconductor lines 312, 313, 314, and 315. In the same plane, the semiconductor lines are electrically coupled together via a bit line structure (eg, 302B).

The word line number shown in FIG. 1A, in the even memory pages, the word line number from the back to the front of the overall structure is gradually increased from 325-1 to 325-N. In the odd memory page, the word line number from the back to the front of the overall structure is gradually decreasing from 325-1 to 325-N. (descends).

The semiconductor lines terminate in bit line structures 312A, 313A, 314A, and 315A, such as semiconductor lines 312, 313, 314, and 315. As shown, within the array, the bit line structures 312A, 313A, 314A, and 315A are electrically coupled to different bit lines for connection to decoding circuitry to select a plane. These bit line structures 312A, 313A, 314A, and 315A can be simultaneously patterned while defining a plurality of stacks.

The semiconductors terminate in bit line structures 302B, 303B, 304B, and 305B, such as semiconductor lines 302, 303, 304, and 305. As shown, within the array, these bit line structures 302B, 303B, 304B, and 305B are electrically coupled to different bit lines for connection to a decoding circuit to select a plane. These bit line structures 302B, 303B, 304B, and 305B can be simultaneously patterned while defining a plurality of stacks.

Any given semiconductor line stack is coupled to one of the bit line structures 312A, 313A, 314A, and 315A, or one of the bit line structures 302B, 303B, 304B, and 305B, but not simultaneously coupled to two By. The semiconductor bit line stack has a directivity from the end of the bit line to the end of the source line, or one of the two opposite directions in the directivity of the end of the source line to the end of the bit line. For example, semiconductor line stacks 312, 313, 314, and 315 have directionality from the end of the bit line to the end of the source line, while semiconductor line stacks 302, 303, 304, and 305 have positions from the end of the source line. The directionality of the end of the line.

Semiconductor line stacks 312, 313, 314, and 315 terminate at an end point via bit line structures 312A, 313A, 314A, and 315A, while semiconductor line stacking 312, 313, 314, and 315 pass through the SSL gate structure 319, the ground select line GSL 326, then the word lines of the 325-1 WL to 325-N WL, and the ground selection line GSL327, ending at another A source line 328 of an endpoint. The semiconductor line stacks 312, 313, 314, and 315 do not reach the bit line structures 302B, 303B, 304B, and 305B.

The semiconductor line stacks 302, 303, 304, and 305 terminate at one end via bit line structures 302B, 303B, 304B, and 305B, while the semiconductor line stacks 302, 303, 304, and 305 pass through the SSL gate structure 309, ground select line GSL 327 Then, the word line of 325-N WL to 325-1 WL, and the ground selection line GSL 326, terminate at the source line at the other end (masked by other parts in the figure). The semiconductor line stacks 302, 303, 304, and 305 are not connected to the bit line structures 312A, 3103A, 314A, and 315A.

A layer of memory material is deposited at the intersections in the interface region, the intersections being between the semiconductor lines 312-315 and 302-305, and between the plurality of word lines from 325-1 to 325-N. Similar to the word line, the ground select line GSL 326 and GSL 327 are conformed to a plurality of stacks.

Each semiconductor line stack is terminated by one end of the bit line structure and terminated by the source line. For example, semiconductor line stacks 312, 313, 314, and 315 terminate at bit line structures 312A, 313A, 314A, and 315A, while the other end terminates at source line 328. At the proximal end of FIG. 1A, each other semiconductor line stack terminates at bit line structures 302B, 303B, 304B, and 305B ends, with each other semiconductor line stack terminating at a different source line. At the distal end of FIG. 1A, each other semiconductor line stack terminates in a bit line structure 312A, 313A, 314A And the 315A end, and each other semiconductor line stack stops at a different source line.

A bit line and string select lines are formed in the metal layers ML1, ML2, and ML3. The bit line is coupled to a plane decoder (not shown). The string selection line is coupled to a string selection line decoding device (not shown).

In the steps defined by word lines 325-1 through 325-N, ground select lines GSL 326 and 327 can be simultaneously patterned. Ground select devices are formed at intersections between the plurality of stacked surfaces and ground select lines GSL 326 and 327. In the steps defined by word lines 325-1 through 325-N, SSL gate structures 319 and 309 can be simultaneously patterned. String select devices are formed at the intersection between a plurality of stacked surfaces and string select (SSL) gate structures 319 and 309. Within a particular stack in the array, these devices are coupled to a decoding circuit to select strings.

In a three-dimensional (3D) memory device as shown in FIG. 1A, a semiconductor line (such as 312 and 327) and a ground selection line GSL (such as 326 and 327) (such as 312-315) It has a relatively high resistance with 302-305), which in turn reduces the performance of the 3D memory device.

Therefore, it is expected to provide a three-dimensional memory device having a lower resistance in a semiconductor line passing through an SSL gate structure and a ground selection line.

The device on the integrated circuit includes alternating semiconductor and insulated wire stacks. The sides of the insulated wire may be recessed compared to the sides of the semiconductor wire, so at least one side of the stack includes a recess between the semiconductor wires. The device includes a gate structure on a stack of semiconductor lines, such as the SSL gate structure 319 as described above. The gate structure includes a vertical portion and a horizontal extension between the semiconductor lines, the vertical portion being adjacent to at least one side of the stack, and the horizontal extension being in the recess. The horizontal extension has an inner side surface and an outer side surface, and the inner side surface is adjacent to a side edge of the insulated wire. The outer side surface of the horizontal extension may be flushed with the sides of the semiconductor wire.

The device includes a second gate structure, such as may be used for ground selection line GSL 326 as described above, the second gate structure being spaced apart from the first mentioned gate structure. The second gate structure includes a vertical portion and a horizontal extension between the semiconductor lines, the vertical portion being adjacent to at least one side of the stack, and the horizontal extension portion being receivable in the recess portion. The device may comprise an insulating element between the horizontal extension of the second gate structure and the horizontal extension of the first mentioned gate structure.

In order to better understand the above and other aspects of the present disclosure, the following detailed description of the embodiments and the accompanying drawings are set forth below.

The three-dimensional memory device on the integrated circuit has a string select line (SSL) and a ground select line (GSL, ground select line), wherein the string select line structure is used as a string select switch. Gate, ground selection line structure as ground selection switch The gates of the ground select switches, when the switches are turned on using extended gate structures, the string select line structure and the ground select line structure reduce the resistance of the semiconductor lines in the stack. The device includes alternating semiconductor and insulated wire stacks. The sides of the insulated wire may be recessed compared to the sides of the semiconductor wire, so at least one side of the stack includes a recess between the semiconductor wires. The device includes a gate structure on a stack of semiconductor lines. The gate structure includes a vertical portion and a horizontal extension between the semiconductor lines, the vertical portion being adjacent to at least one side of the stack, and the horizontal extension being in the recess.

When a voltage is applied to the gate structure, an inversion layer having a low resistance is formed on the semiconductor line, and the inversion layer is under the gate structure of the normal channel region, and along the horizontal extension. The horizontal extension increases the length of the inversion region along the semiconductor line. The horizontal extensions can be embedded between the semiconductor lines, so the horizontal extension has a lower impact on the memory array layout efficiency.

1 is a perspective view showing a semiconductor line stack having a gate structure on an integrated circuit in accordance with an embodiment of the present invention. As described herein, embodiments may employ a string select line/ground select line oxide-nitride-oxide (SSL/GSL ONO) method. The device includes alternating semiconductor and insulated wire stacks. The semiconductor line can be used as a bit line. For example, as shown in the stack 110 of four stacks, the stack 110 includes alternating semiconductor lines 112 and 114, and insulated lines 111, 113 and 115, while the stack 130 includes alternating semiconductor lines. 132 and 134, and insulated wires 131, 133 and 135. In the example, the sides of the insulated wire are recessed compared to the sides of the semiconductor wire, so at least one side of the stack includes a recess between the semiconductor wires. For example, the sides of the insulated lines 111, 113, and 115 are recessed relative to the sides of the semiconductor lines 112 and 114, so the stack 110 includes recesses 108 and 118 between the semiconductor lines 112 and 114. Likewise, the sides of the insulated lines 131, 133, and 135 are recessed relative to the sides of the semiconductor lines 132 and 134, so the stack 130 includes recesses 128 and 138 between the semiconductor lines 132 and 134.

As shown in FIG. 1, semiconductor lines 112, 114, 132, and 134 include strip of semiconductor material, and strips of semiconductor material have sides and a gate dielectric layer on the side of the semiconductor material. (gate dielectric layer) 150. FIG. 2 further illustrates a semiconductor line including a gate dielectric layer 150.

The device includes a gate structure, and the gate structure includes a GSL gate structure and an SSL gate structure, and the GSL gate structure is a portion of the GSL line 327, and the SSL gate structure is a portion of the SSL gate structure 309 on the semiconductor line stack. The gate structure includes a vertical portion and a horizontal extension, the vertical portion being adjacent to at least one side of the stack, and the horizontal extension being recessed between the semiconductor lines. In some embodiments, the horizontal extensions may not be within recesses.

As shown in FIG. 1, the GSL gate structure includes a vertical portion 160 and a horizontal extension portion 143, and the vertical portion 160 is adjacent to the stack 130, and the horizontal extension portion 143 is between the semiconductor lines 132 and 134, preferably in a recess. In section 138. The vertical portion 160 is also adjacent to the stack 110, and the stack 110 includes a horizontal extension 123, The horizontal extension 123 is in the recess 118 between the semiconductor lines 112 and 114. The stack 110 and stack 130 may include additional horizontal extensions, such as horizontal extensions 121 and 141, while horizontal extensions 121 and 141 are between the semiconductor lines 112 and 132 at the bottom of the stack and the substrate.

2 is a cross-sectional view showing a stacked section of the apparatus in FIG. 1 , the cross-sectional view being taken along the gate structure of the GSL and the stacked AA line. The elements in Fig. 2 are labeled with the same numbers as those in Fig. 1.

The semiconductor lines in the stack may comprise a strip of semiconductor material, and a gate dielectric layer, while the strip of semiconductor material has sides and the gate dielectric layer is on the side of the semiconductor material. The sides 152 and 154 of the semiconductor lines 132 and 134 are the outer surface of the gate dielectric layer 150. 2 depicts semiconductor lines 112, 114, 132, and 134 including semiconductor strips 212, 214, 232, and 234, and a gate dielectric layer 150, and a strip of semiconductor material 212, 214, 232 and 234 have sides and gate dielectric layer 150 is on the sides of strips of semiconductor material 212, 214, 232 and 234, respectively. The sides 152 and 154 of the semiconductor lines 132 and 134 are the outer side surfaces of the gate dielectric layer 150, and the side edges 152 and 154 of the semiconductor lines 132 and 134 are on the sides of the semiconductor materials 232 and 234, respectively.

In the device, the horizontal extension has an inner side surface and an outer side surface, the inner side surface being adjacent to a side of the insulated wire. The outer surface of the horizontal extension can be flush with the sides of the semiconductor line. For example, referring to FIG. 2, in stack 130, horizontal extension 143 has an inner side surface 156 and an outer side surface 158 with inner side surface 156 adjacent the side of insulated wire 133. Outer surface 158 The sides 152 and 154 of the semiconductor lines 132 and 134 can be flushed, respectively.

The gate structure includes a GSL gate structure and an SSL gate structure, and the gate structure can be formed by anisotropic etching. The anisotropic etch produces sharp, well-controlled features such that the outer surface of the horizontal extension of the gate structure can be perpendicular, or nearly vertically flat or flush the semiconductor on the side of the stacked structure Overhanging sides of the semiconductor lines.

Figure 3 is a side elevational view of the stack 110, the side views being depicted along a direction orthogonal to the cross-section shown in Figure 2. In FIG. 3, gate dielectric layer 150 is shown over insulated line 115 and insulating element 170. When gate dielectric layer 150 is removed from semiconductor lines 114 and 112, strips of semiconductor material 214 and 212 are exposed. The elements in Fig. 3 are assigned the same numbers as the elements corresponding to those in Figs. 1 and 2.

Figure 3 shows one side of the SSL gate structure, which is separated from the GSL gate structure along the stack. When the SSL gate structure can be used as a string select line, the GSL gate structure can be used as a ground selection line. The SSL gate structure includes a vertical portion 180, and horizontal extensions 121b and 123b, while the vertical portion 180 is adjacent on at least one side of the stack, and the horizontal extensions 121b and 123b are on the sides of the vertical portion 180. The horizontal extensions 123b are in recesses between the semiconductor lines 114 and 112, while the semiconductor lines 114 and 112 comprise strips of semiconductor material 214 and 212. The horizontal extension 121b is in a recess between the semiconductor line 112 and the substrate at the bottom of the stack, wherein the semiconductor line 112 comprises a strip of semiconductor material 212.

As shown in FIG. 3, the GSL gate structure includes a vertical portion 160, and horizontal extensions 123 and 121, while the vertical portion 160 is adjacent to at least one side of the stack, and the horizontal extensions 123 and 121 are at the side of the vertical portion 160. On the side. The horizontal extension 123 is in the recess between the semiconductor lines 214 and 212. The horizontal extension 121 is in a recess between the strip of semiconductor material 212 and the substrate at the bottom of the stack.

The device includes an insulating element 170, wherein the insulating element 170 is between a horizontal extension of the SSL gate structure and a horizontal extension of the GSL gate structure. Insulation element 170 blocks the path between the GSL gate structure and the SSL gate structure. Therefore, the insulating member 170 can block the path between the horizontal extensions 123 and 123b and the path between the horizontal extensions 121 and 121b.

When a voltage is applied to the GSL gate structure (vertical portion 160 and horizontal extensions 121 and 123) to turn on the GSL switch, channel regions in the strips of semiconductor material 212, 214 adjacent to the vertical portion 160 are also turned on. Moreover, the inversion layer in the region 282a-282b is sensed, and the induced inversion layer is induced in the strip of semiconductor material 212 along the upper end edge of the horizontal extension portion 121, and the inversion layer in the region 292a-292b is sensed. The induced inversion layer is induced in the strip of semiconductor material 212 along the lower end edge of the horizontal extension 123, and the inversion layer in the region 284a-284b, which is induced in the reverse edge along the upper edge of the horizontal extension 123 In the strip of semiconductor material 214. Compared to the length of the inversion region where the GSL gate structure is formed, wherein the GSL gate structure has only a vertical portion and no horizontal extension as described herein, the horizontal extension of the GSL gate structure is increased along the semiconductor Strips 212 and 214 Reverse the length of the area.

Similarly, when a voltage is applied to the SSL gate structure (vertical portion 180 and horizontal extensions 121b and 123b) to turn on the SSL switch, the channel regions in the strips of semiconductor material 212 and 214 adjacent to the vertical 180 are also turned on, and The inversion layer in the region 282c-282d is induced, the induced inversion layer is in the strip of semiconductor material 212 along the upper edge of the horizontal extension 121b, and the inversion layer in the region 292c-292d is induced The induced inversion layer is induced in the strip of semiconductor material 212 along the lower end edge of the horizontal extension 123b, and the inversion layer in the region 284c-284d is induced in the horizontally extending portion 123b. The upper end edge of the strip of semiconductor material 214.

4 is a perspective view showing a semiconductor line stack having a gate structure on an integrated circuit in accordance with another embodiment of the present invention. As described herein, embodiments may employ a string select line/ground select line gate-oxide (SSL/GSL GOX) method. The device includes alternating semiconductor and insulated wire stacks. The semiconductor line can be used as a bit line. For example, as shown in the stack 410 of four stacks, stack 410 includes alternating semiconductor lines 412 and 414, and insulated lines 411, 413, and 415, while stack 430 includes alternating semiconductor lines 432 and 434, and insulated lines 431. , 433 and 435. In the example, the sides of the insulated wire are recessed compared to the sides of the semiconductor wire, so at least one side of the stack includes a recess between the semiconductor wires. For example, the sides of the insulated lines 411, 413, and 415 are recessed relative to the sides of the semiconductor lines 412 and 414, so the stack 410 includes a semiconductor Depressions 408 and 418 between body lines 412 and 414. Likewise, the sides of the insulated lines 431, 433, and 435 are recessed relative to the sides of the semiconductor lines 432 and 434, so the stack 430 includes recesses 428 and 438 between the semiconductor lines 432 and 434.

As shown in FIG. 4, semiconductor lines 412, 414, 432, and 434 include strips of semiconductor material having sides, and insulating layers 422, 424, 442, and 444 on sides of the semiconductor material, respectively. Figure 5 further illustrates a semiconductor line comprising a strip of semiconductor material.

The device includes a gate structure, and the gate structure includes a GSL gate structure and an SSL gate structure, and the GSL gate structure is part of the GSL line 327, and the SSL gate structure is part of the SSL gate structure 309 on the semiconductor line stack . The gate structure includes a vertical portion and a horizontal extension, the vertical portion being adjacent to at least one side of the stack, and the horizontal extension being in the recess between the semiconductor lines. In some embodiments, the horizontal extension may not be within the recess.

As shown in FIG. 4, the gate structure includes a vertical portion 460, and a horizontal extension portion 443, the vertical portion 460 is adjacent to the stack 430, and the horizontal extension portion 443 is between the semiconductor lines 432 and 434, preferably in the recess portion. 438. The vertical portion 460 is also adjacent to the stack 410, and the stack 410 includes a horizontal extension 423 and a horizontal extension 423 is a recess 418 between the semiconductor lines 412 and 414. Stack 410 and stack 430 may include additional horizontal extensions, such as horizontal extensions 421 and 441, while horizontal extensions 421 and 441 are between semiconductor lines 412 and 432 at the bottom of the stack and the substrate.

Figure 5 is a cross-sectional view showing the stacked section of the apparatus in Figure 4, the section The picture shows the gate structure along the GSL and the CC line of the stack. The elements in Fig. 5 are labeled with the same numbers as those in Fig. 4. 5 illustrates semiconductor lines 412, 414, 432, and 434, and semiconductor lines 412, 414, 432, and 434 include strips 512, 514, 532, and 534 of semiconductor material, and insulating layers 422, 424, 442, and 444, and semiconductor materials. Strips 512, 514, 532 and 534 have sides and insulating layers 422, 424, 442 and 444 are on the sides of strips of semiconductor material 512, 514, 532 and 534, respectively. Since in an alternative embodiment, a gate oxide growth mode is employed, as in the alternative embodiment depicted in FIG. 5, strips of semiconductor material 512, 514, 532 and 534 in semiconductor lines 412, 414, 432 and 434 For example, FIG. 2 illustrates the strips of semiconductor material 212, 214, 232, and 234 used in the embodiment, which may have a narrower width.

The semiconductor lines in the stack may comprise a strip of semiconductor material, and an insulating layer, while the strip of semiconductor material has sides and the insulating layer is on the side of the semiconductor material. The sides 533 and 537 of the semiconductor lines 432 and 434 are the outer side surfaces of the insulating layers (e.g., 442, 444). As shown in FIG. 5, the semiconductor lines 434 in the stack 430 can include a strip of semiconductor material 534, and an insulating layer 444, wherein the strip of semiconductor material 534 has sides 535 and the insulating layer 444 is on the side 535 of the strip of semiconductor material 534. on. The side 537 of the strip of semiconductor material 534 is the outer side surface of the insulating layer 444. The insulating layer 444 can include an oxide of strips of semiconductor material 534.

In the device, the horizontal extension has an inner side surface and an outer side surface, the inner side surface being adjacent to a side of the insulated wire. The outer side surface of the horizontal extension may be flush with the sides of the semiconductor line. For example, see Figure 5, in stack 430, The horizontal extension 441 has an inner side surface 531 and an outer side surface 532, wherein the inner side surface 531 is adjacent to the side of the insulated wire 431. The outer side surfaces 532 can be flush with the sides 533 and 537 of the semiconductor lines 432 and 434, respectively.

Figure 6 is a side elevational view of the stack 410, the side view being depicted along a cross-sectional view orthogonal to Figure 5. In FIG. 6, insulating layers 422, 424 are removed from semiconductor lines 412 and 414 to expose strips of semiconductor material 512 and 514. The elements in Fig. 6 correspond to those in Figs. 4 and 5, and the same reference numerals are used. Fig. 6 is similar to Fig. 3 but differs in the structure of the insulating member 470. In Fig. 6, when charge storage structures are formed in the memory, the insulating member 470 is formed, and the insulating member 470 has the same basic multilayer dielectric layer structure as the charge storage structure. In Fig. 3, the insulating member 170 is a remnant of a dielectric layer (e.g., insulated wires 131, 133, 135) which is etched back from the horizontal extension to form a depressed portion, Will be explained in more detail.

Figure 6 illustrates one side of the SSL gate structure that is spaced apart from the GSL gate structure along the stack. When the SSL gate structure can be used as string select lines, the GSL gate structure can be used as ground select lines. The SSL gate structure includes a vertical portion 480, and horizontal extensions 421b and 423b, while the vertical portion 480 is adjacent on at least one side of the stack, and the horizontal extensions 421b and 423b are on the sides of the vertical portion 480. The horizontal extension 423b is in a recess between the semiconductor lines 412 and 414, wherein the semiconductor lines 412 and 414 comprise strips 514 of semiconductor material. The horizontal extension 421b is in a recess between the semiconductor line 412 and the substrate at the bottom of the stack, The mid-semiconductor line 412 includes a strip of semiconductor material 512.

As shown in FIG. 6, the GSL gate structure includes a vertical portion 460, and horizontal extensions 421 and 423, while the vertical portion 460 is adjacent to at least one side of the stack, and the horizontal extensions 421 and 423 are at the side of the vertical portion 460. On the side. Horizontal extensions 423 are in recesses between semiconductor lines 412 and 414, while semiconductor lines 412 and 414 include strips of semiconductor material 512 and 514. The horizontal extension 421 is in a recess between the semiconductor line 412 and the substrate at the bottom of the stack, while the semiconductor line 412 includes a strip of semiconductor material 512.

The device includes an insulating element 470 with the insulating element 470 between a horizontal extension of the SSL gate structure and a horizontal extension of the GSL gate structure. Insulation element 470 blocks the path between the GSL gate structure and the SSL gate structure. Therefore, the insulating member 470 can block the path between the horizontal extensions 423 and 423b and the path between the horizontal extensions 421 and 421b.

When a voltage is applied to the GSL gate structure (vertical portion 460 and horizontal extensions 421 and 423) to turn on the GSL switch, the channel regions in the strips of semiconductor material 512 and 514 adjacent in the vertical 460 are also turned on. Moreover, the inversion layers in the 582a-582b region are sensed, and the induced inversion layer is reversed in the region 592a-592b of the strip of semiconductor material 512 along the upper edge of the horizontal extension 421. The layer is induced, and the induced inversion layer is sensed in the strip of semiconductor material 512 along the lower end edge of the horizontal extension 423, and the inversion layer in the region of 584a-584b is sensed. The upper edge of the extension 423 is in the strip of semiconductor material 514. Compared to the length of the inversion region where the GSL gate structure is formed, where GSL The gate structure, as described herein, has only vertical portions and no horizontal extensions, and the horizontal extension of the GSL gate structure increases the length along the inversion regions of the strips of semiconductor material 512 and 514.

Similarly, when a voltage is applied to the SSL gate structure (vertical portion 480 and horizontal extensions 421b and 423b) to turn on the SSL switch, the channel regions in the strips of semiconductor material 512 and 514 adjacent to the vertical 480 are also turned on. The inversion layer in the region of 582c-582d is sensed, and the induced inversion layer is in the strip of semiconductor material 512 along the upper edge of the horizontal extension 421b, and the inversion layer in the region 592c-592d is sensed. The inductive inversion layer is induced in the strip of semiconductor material 512 along the lower end edge of the horizontal extension 423b, and the inversion layer in the region of 584c-584d, which is induced in the reverse layer along the upper edge of the horizontal extension 423b In the strip of semiconductor material 514.

7 through 12 illustrate a method of fabricating a device on an integrated circuit in accordance with an embodiment of the present invention. The method of fabrication includes forming a stack of alternating strips of semiconductor material and insulated wires. The strip of semiconductor material can be used as a bit line. Referring to Figure 7, a stack 710 of alternating strips of semiconductor material 714 and insulated lines 711, 713 and 715 are formed. Likewise, alternating rows 730 and 734 of semiconductor material and stacks 730 of insulated lines 731, 733 and 735 are formed.

The fabrication method includes forming etch masks on the stack and etching the stack using an etch mask to define the insulating elements. Referring to FIG. 8, etching masks 870 and 872 are formed on the stack, and the stack includes a stack 710 and a stack 730. The etch masks 870 and 872 avoid pull-back etching from the insulated portions of the etched portions on the stack, so the insulated portions (portions) Of the insulating lines) no depressions were formed. As shown in FIG. 9, after the etch back is removed, and after the etch mask is removed, the remaining insulated line portions form the insulating member 970.

The method of fabrication includes recessing the sides of the insulated wire, the recess being compared to the sides of the strip of semiconductor material such that at least one side of the stack includes recesses between the strips of semiconductor material. Recessing can include using an etched back etched in the stack to define a recess between the strips of semiconductor material. Referring to FIG. 9, the result of using the pull-back etching on the insulated wire is to define a depressed portion 913 on the side of the insulated wire 713, and a depressed portion 903 on the opposite side of the insulated wire 713, and the depressed portions 903 and 913 are in the semiconductor material. Between strips 712 and 714. Similarly, a depressed portion 933 is defined on the side of the insulated wire 733, and a depressed portion 923 is defined on the opposite side of the insulated wire 733, and the depressed portions 923 and 933 are between the strips of semiconductor material 732 and 734. Under the etch masks 870 and 872, the recesses are separated by an insulating member 970.

The method of fabrication further includes depositing a gate dielectric layer on a side of the strip of semiconductor material. The stack includes a line of semiconductor material and a gate dielectric layer, and the strip of semiconductor material has sides and a gate dielectric layer is deposited on the sides of the strip of semiconductor material. The side of the semiconductor line is the outer side surface of the gate dielectric layer. Referring to FIG. 10, a gate dielectric layer 1050 is deposited on the sides of strips 714 of semiconductor material 714 in stack 710. Gate dielectric layer 1050 is also deposited on the sides of strips of semiconductor material 732 and 734 in stack 730. Semiconductor lines 1012 and 1014 in stack 710 include strips of semiconductor material 712 and 714 and gate dielectric layer 1050, while strips of semiconductor material 712 and 714 have sides, gate dielectric layers 1050 is deposited on the sides of the strips of semiconductor material 712 and 714. Semiconductor lines 1032 and 1034 in stack 730 include strips of semiconductor material 732 and 734 and gate dielectric layer 1050, while strips of semiconductor material 732 and 734 have sides, and gate dielectric layer 1050 is deposited over strips 732 and 734 of semiconductor material. On the side. The gate dielectric layer 1050 can be a multilayer dielectric layer, such as an oxide-nitride-oxide (ONO) dielectric material used for charge storage in memory cells. .

As shown in FIG. 11, the fabrication method includes depositing a gate material 1060 on stack 710 and stack 730. The gate material can be polysilicon, metal, multilayer conductive materials, or other types of gate materials.

The fabrication method includes using a patterned etch of gate material 1160 on the semiconductor line stack to define a gate structure. The gate structure includes a GSL gate structure and an SSL gate structure 1280 on a stack of semiconductor lines, wherein the GSL gate structure is part of the GSL line 327 (FIG. 1A), and the SSL gate structure 1280 is an SSL gate structure 309. Part of it (Figure 1A). The patterned etch can be done by anisotropic etching, which does not remove the gate material from the recess. As a result, the gate structure includes a vertical portion and a horizontal extension, and the vertical portion is adjacent to at least one side of the stack, and the horizontal portion is in the recess between the semiconductor lines. The horizontal extension has an inner side surface and an outer side surface, and the inner side surface is adjacent to the side of the insulated wire. The method of fabrication includes etching the horizontal extensions and the semiconductor lines such that the outer side surfaces of the horizontal extensions are flush with the sides of the semiconductor lines.

Referring to FIG. 12, the gate structure includes a vertical portion 1260 and a vertical portion 1260. Adjacent to stack 710 and stack 730. In stack 710, the gate structure includes a horizontal extension 723 between the strips of semiconductor material 712 and 714 and another horizontal extension (masked by other portions of the figure), wherein the horizontal extension 723 is at the recess 913, Another horizontal extension that is obscured by other portions of the figure is in the recess 903. In stack 730, the gate structure includes a horizontal extension 743 between the strips of semiconductor material 732 and another horizontal extension (masked by other portions of the figure), wherein the horizontal extension 743 is in the recess 933, Another horizontal extension that is obscured by other portions of the figure is in the recess 923.

Figures 13 through 18 illustrate a method of fabricating a device on an integrated circuit in accordance with another embodiment of the present invention. The method of fabrication includes forming a stack of alternating strips of semiconductor material and insulated wires. The strip of semiconductor material can be used as a bit line. Referring to Fig. 13, an alternating stack 1310 of semiconductor material strips 1314 and insulated lines 1311, 1313 and 1315 is formed. Likewise, alternating strips 1332 of semiconductor material and 1334 and stacks 1330 of insulated lines 1331, 1333 and 1335 are formed. The method of fabrication can include depositing a dielectric material 1370 on the stacks 1310 and 1330. The dielectric layer 1370 can be a multilayer dielectric layer, such as an oxide-nitride-oxide dielectric material used for charge storage in memory cells.

The method of fabrication can include forming an etch mask on the stack and etching the stack using an etch mask to define the insulating elements. Referring to FIG. 14, after the dielectric layer 1370 is deposited on the stack, etch masks 1470 and 1472 are formed on the stack, the stack including the stack 1310 and the stack 1330. Etching the reticle 1470 and 1472 avoids patterned etching from the etched portion of the dielectric layer 1370 on the stack. The patterned etch removes a portion of the dielectric layer 1370, and the removed dielectric layer 1370 is non-etched light. The portions under the covers 1470 and 1472, and then the etch masks 1470 and 1472 are removed, and as a result, as shown in Fig. 15, an insulating member 1570 is formed on the stack.

The method of fabricating can further include forming an insulating layer on the side of the strip of semiconductor material, and the method of forming the insulating layer includes oxidizing the sides of the strip of semiconductor material. Referring to Fig. 16, semiconductor lines 1612 and 1614 in stack 1310 include strips 1312 and 1314 of semiconductor material, and insulating layers 1322 and 1324, while strips 1312 and 1314 of semiconductor material have sides, and insulating layers 1322 and 1324 are formed respectively in the semiconductor. The sides of the strips 1312 and 1314 are, for example, on the sides of the strip of oxidized semiconductor material. The semiconductor lines 1632 and 1634 on the stack 1330 include strips of semiconductor material 1332 and 1334, and insulating layers 1342 and 1344, while the strips of semiconductor material 1332 and 1334 have sides, and insulating layers 1322 and 1324 are formed on strips of semiconductor material 1332 and 1334, respectively. On the side. As a result of the formation of the insulating layer on the side of the strip of semiconductor material, a recess 1613 is defined on the side of the insulated line 1313, and a recess 1603 is defined on the opposite side of the insulated line 1313, while the recesses 1603 and 1613 are in the strip of semiconductor material 1612 and Between 1614. Similarly, a recess 1633 is defined on the side of the insulated wire 1333, and a recess 1623 is defined on the opposite side of the insulated wire 1333, and the recesses 1623 and 1633 are between the strips of semiconductor material 1632 and 1634.

As shown in FIG. 17, the fabrication method includes depositing a gate material 1760 on the stack 1310 and the stack 1330. The gate material 1160 can be a polysilicon, a metal, a multilayer conductive material, or other type of gate material.

The fabrication method includes using a patterned etch of gate material 1760 on the semiconductor line stack to define the gate structure. The gate structure is included in the semiconductor line stack The upper GSL gate structure and SSL gate structure 1880, wherein the GSL gate structure is part of the GSL line 327 (FIG. 1A), and the SSL gate structure 1880 is part of the SSL gate structure 309 (FIG. 1A). The patterned etch can be done by anisotropic etching, which does not remove the gate material from the recess. As a result, the gate structure includes a vertical portion and a horizontal extension portion, and the vertical portion is adjacent to at least one side of the stack, and the horizontal extension portion is a recess portion between the semiconductor lines. The horizontal extension has an inner side surface and an outer side surface, and the inner side surface is adjacent to the side of the insulated wire. The manufacturing method includes etching the horizontal extension and the semiconductor line such that an outer surface of the horizontal extension is flush with a side of the semiconductor line, wherein a side of the semiconductor line is an outer side surface of the insulating layer, and an insulating layer is formed on the semiconductor line On the strip of semiconductor material.

Referring to Figure 18, the gate structure includes a vertical portion 1860 that is adjacent to the stack 1310 and the stack 1330. In stack 1310, the gate structure includes a horizontal extension 1323 between the strips of semiconductor material 1312 and 1314 and another horizontal extension (masked by other portions of the figure), wherein the horizontal extension 1323 is at the recess 1613 Another horizontal extension that is obscured by other portions of the figure is in the recess 1603. In stack 1330, the gate structure includes a horizontal extension 1343 between the strips of semiconductor material 1332 and 1334 and another horizontal extension (masked by other portions of the figure), wherein the horizontal extension 1343 is in the recess 1633, Another horizontal extension that is obscured by other portions of the figure is in the recess 1623.

In summary, although the present invention has been disclosed above in the preferred embodiment, It is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

108, 118, 128, 138, 408, 418, 428, 438, 903, 913, 923, 933, 1603, 1613, 1623, 1633‧‧‧

110, 130, 410, 430, 710, 730, 1310, 1330‧‧‧ stack

111, 113, 115, 131, 133, 135, 411, 413, 415, 431, 433, 435, 711, 713, 715, 731, 733, 735, 1311, 1313, 1331, 1333, 1335‧‧‧ insulated wire

112, 114, 132, 134, 302, 303, 304, 305, 312, 313, 314, 315, 412, 414, 432, 434, 1012, 1014, 1032, 1034, 1612, 1614, 1632, 1634‧‧ Semiconductor line

121, 121b, 123, 123b, 141, 143, 421, 421b, 423, 423b, 441, 443, 723, 743, 1323, 1343 ‧ ‧ horizontal extension

150, 1050‧‧‧ gate dielectric layer

152, 154, 533, 537‧‧‧ side

156, 531‧‧‧ inside surface

158, 532‧‧‧ outside surface

160, 180, 460, 480, 1260, 1860‧‧‧ vertical

170, 470, 970, 1570‧‧‧ insulation components

212, 214, 232, 234, 512, 514, 532, 534, 712, 714, 732, 734, 1312, 1314, 1332, 1334, 1612, 1614, 1632, 1634 ‧ ‧ semiconductor material strip

282a, 282b, 282c, 282d, 284a, 284b, 284c, 284d, 292a, 292b, 292c, 292d, 582a, 582b, 582c, 582d, 584a, 584b, 584c, 584d, 592a, 592b, 592c, 592d‧‧‧

302B, 303B, 304B, 305B, 312A, 313A, 314A, 315A‧‧‧ bit line structure

309, 319, 1280, 1880‧‧‧ string selection line gate structure

325-1, 325-N‧‧‧ character line

326, 327‧‧‧ Grounding selection line

328‧‧‧ source line

422, 424, 442, 444, 1322, 1324, 1342, 1344‧ ‧ insulation

870, 872, 1470, 1472‧‧‧ etching mask

1060, 1160, 1760‧‧‧ gate materials

1370‧‧‧ dielectric layer

ML1, ML2, ML3‧‧‧ metal layer

FIG. 1A is a perspective view of a 3D NAND flash memory device.

1 is a perspective view showing a semiconductor line stack having a gate structure on an integrated circuit in accordance with an embodiment of the present invention.

Figure 2 is a cross-sectional view showing a stacked cross section in the apparatus of Figure 1.

Figure 3 is a side elevational view of the stack in the apparatus of Figure 1.

4 is a perspective view showing a semiconductor line stack having a gate structure on an integrated circuit in accordance with another embodiment of the present invention.

Figure 5 is a cross-sectional view showing a stacked cross section in the apparatus of Figure 4.

Figure 6 is a side elevational view of the stack in the apparatus of Figure 4.

7 through 12 illustrate a method of fabricating a device on an integrated circuit in accordance with an embodiment of the present invention.

Figures 13 through 18 illustrate a method of fabricating a device on an integrated circuit in accordance with another embodiment of the present invention.

108, 118, 128, 138‧‧‧ recessed

110, 130‧‧‧ Stacking

111, 113, 115, 131, 133, 135‧‧‧ insulated wire

112, 114, 132, 134‧‧‧ semiconductor lines

121, 123, 141, 143‧‧‧ horizontal extension

150‧‧‧ gate dielectric layer

160, 180‧‧‧ vertical section

170‧‧‧Insulation components

Claims (31)

An apparatus for an integrated circuit, comprising: an alternating plurality of semiconductor lines and a plurality of insulated lines stacked, wherein side edges of the insulated lines are recessed compared to sides of the semiconductor lines; And a gate structure on the plurality of semiconductor line stacks, the gate structure comprising: a vertical portion adjacent to at least one side of the stack, and a plurality of horizontal extensions, the semiconductors Between the lines. The device of claim 1, wherein at least one side of the stack includes a plurality of recesses, the recesses being between the semiconductor lines, and the horizontal extensions of the gate structure At least partially within the depressions. The device of claim 2, wherein the semiconductor lines in the stack comprise a strip of semiconductor material having a plurality of sides and a gate dielectric layer attached to the semiconductor The sides of the material, the sides of the semiconductor lines are an outer side surface of the gate dielectric layer. The device of claim 2, wherein the horizontal extensions have a plurality of inner surfaces adjacent to sides of the insulated wires and a plurality of outer sides The outer suurfaces are flush with the sides of the semiconductor lines. The device of claim 2, wherein the plurality of semiconductor wires in the stack comprise a strip of semiconductor material having a plurality of sides and an insulating layer on a side of the semiconductor material, The side edges of the semiconductor lines are an outer side surface of the insulating layer. The device of claim 5, wherein the insulating layer comprises an oxide of a semiconductor material. The device of claim 1, comprising: a second gate structure, the second gate structure being spaced apart from the first mentioned gate structure; the second gate structure, The method includes: a vertical portion adjacent to at least one side of the stack, and a plurality of horizontal extensions between the semiconductor lines; and an insulating member attached to the second gate structure A horizontal extension is between the horizontal extensions of the first mentioned gate structure. The device of claim 7, wherein the side edges of the insulated wires are recessed compared to the sides of the semiconductor wires, so at least one side of the stack includes a plurality of recesses. The plurality of semiconductor lines and the horizontal extensions of the second gate structure are at least partially within the recesses. The device of claim 8, wherein the horizontal extensions of the second gate structure have a plurality of inner side surfaces adjacent to the insulation The sides of the line, as well as the plurality of outside surfaces, are flush with the sides of the semiconductor lines. A method of fabricating an apparatus on an integrated circuit, comprising: forming an alternating plurality of semiconductor lines and a plurality of insulated line stacks, wherein sides of the insulated lines are recessed relative to sides of the semiconductor lines Recessed; depositing a gate material on the stack; and etching the gate material to define a gate structure on the stack of the stacked semiconductor lines, the gate structure comprising: a vertical portion, Adjacent to at least one side of the stack, and a plurality of horizontal extensions between the plurality of semiconductor lines. The manufacturing method of claim 10, wherein one side of the stack includes a plurality of recesses between the plurality of semiconductor lines, and the horizontal extensions of the gate structure are at least partially Inside the recesses. The manufacturing method of claim 11, wherein the recessing comprises: using a pullback etch of the insulated wires in the stack to define between the semiconductor lines The depressions. The manufacturing method of claim 11, wherein the semiconductor wires in the stack comprise a strip of semiconductor material having a plurality of sides The method further includes depositing a gate dielectric layer on a side of the semiconductor material, and a side of the semiconductor lines is an outer side surface of the gate dielectric layer. The manufacturing method of claim 11, wherein the horizontal extensions have a plurality of inner side surfaces adjacent to sides of the insulated wires, and a plurality of outer side surfaces, further comprising etching the levels And extending the semiconductor lines such that the outer surfaces of the horizontal extensions are flush with the sides of the semiconductor lines. The manufacturing method of claim 11, wherein the semiconductor wires in the stack comprise the strip of semiconductor material having a plurality of sides, further comprising forming an insulating layer on a side of the semiconductor material The side edges of the semiconductor lines are an outer side surface of the insulating layer. The method of manufacturing of claim 15, wherein forming an insulating layer comprises oxidizing the sides of the semiconductor material. The manufacturing method of claim 10, wherein forming a stack further comprises depositing a dielectric layer on the plurality of semiconductor lines in the stack and the insulated lines. The manufacturing method of claim 10, further comprising: Etching the gate material to define a second gate structure, the second gate structure being spaced apart from the first mentioned gate structure, the second gate structure comprising: a vertical portion, a phase Adjacent to at least one side of the stack, and a plurality of horizontal extensions between the plurality of semiconductor lines; and etching the stack using an etch mask to define an insulating element in the second The horizontal extensions of the gate structure are between the horizontal extensions of the first mentioned gate structure. The manufacturing method of claim 18, further comprising: recessing a plurality of sides of the insulated wires compared to sidewalls of the semiconductor wires, so that at least one side of the stack includes a plurality of recesses ( The recesses are between the plurality of semiconductor lines, and the horizontal extensions of the second gate structure are at least partially within the recesses. The manufacturing method of claim 19, wherein the horizontal extensions in the second gate structure have a plurality of inner side surfaces adjacent to sides of the insulated wires and a plurality of outer sides The surface further includes: etching the horizontal extensions and the insulated wires such that the outer surfaces of the horizontal extensions are flush with the sides of the semiconductor lines. A memory device comprising a three-dimensional array of non-volatile memory cells, comprising: an integrated circuit substrate; a plurality of stacks, which are alternating a plurality of semiconductor lines and a plurality of insulated lines, the stacks being in a plurality of planes on the integrated circuit substrate; a plurality of string select gate structures </ RTI> are disposed orthogonally on the stacks, and the string selection gate structures have a plurality of surfaces conformal to the stacks, the gate structures comprising: a vertical portion adjacent to the stack On at least one side, and a plurality of horizontal extensions between the plurality of semiconductor lines; a plurality of word lines are orthogonally disposed on the stacks, and the word lines have the stacks a plurality of conformal surfaces; a plurality of memory cells in a plurality of interface regions at a plurality of intersections, the intersections being between the surfaces of the stacks and the word lines, the memories The cell line is disposed in the plurality of word lines and is between the plurality of word line structures and the plurality of source line structures, wherein the string selection gate structures comprise a plurality of conductive lines Shaped structure The conductive conformal structures establish a plurality of string selection means at the intersection between the surfaces of the stacks and the conductive conformal structures. The memory device of claim 21, wherein the side edges of the insulated wires are recessed compared to the sides of the semiconductor wires, so at least one side of the stack includes a plurality of recesses (recesses ), the depressions are tied The plurality of semiconductor lines and the horizontal extensions of the string selection gate structures are at least partially within the recesses. The memory device of claim 22, wherein the semiconductor lines in the stack comprise a strip of semiconductor material having a plurality of sides and a gate dielectric layer attached to the semiconductor material On the side of the strip, the sides of the semiconductor lines are an outer side surface of the gate dielectric layer. The memory device of claim 22, wherein the horizontal extensions of the string selection gate structures have a plurality of inner side surfaces adjacent to sides of the insulated lines. And a plurality of outer side surfaces that are flush with the side edges of the plurality of semiconductor wires. The memory device of claim 22, wherein the semiconductor lines in the stack comprise the strip of semiconductor material having a plurality of sides and an insulating layer on a side of the semiconductor material The side edges of the semiconductor lines are an outer side surface of the insulating layer. The memory device of claim 25, wherein the insulating layer comprises an oxide of a semiconductor material. The memory device as described in claim 21, comprising: a ground selection gate structure disposed orthogonally on the stacks, and the ground selection gate structure having a plurality of surfaces conformal to the stacks, and the ground selection gate structures are located in the strings Selecting a plurality of terminals of the stack to which the gate structure is coupled, the ground selection gate structures including: a vertical portion adjacent to the stacks on the at least one side, and a plurality of horizontal extensions a portion between the plurality of semiconductor lines; and an insulating member between the horizontal extensions of the ground selection gate structure and the horizontal extensions of the string selection gate structures, wherein the plurality of Ground select devices establish a plurality of intersections of the surfaces of the stacks with the ground selection gate structure. The memory device of claim 27, wherein the side edges of the insulated wires are recessed compared to the side edges of the semiconductor wires, so at least one side of the stack includes a plurality of recesses, The recesses are between the plurality of semiconductor lines, and the horizontal extensions of the ground selection gate structures are at least partially within the recesses. The memory device of claim 28, wherein the horizontal extensions of the ground selection gate structure have a plurality of inner side surfaces adjacent to sides of the insulated lines, and A plurality of outer side surfaces that are flush with the sides of the plurality of semiconductor lines. The memory device as described in claim 21, comprising: A one-line structure electrically couples the semiconductor lines of the same layer in a multi-layer plane. The memory device of claim 21, comprising: a plurality of string selection lines disposed on the stacks, wherein the string selection lines of the string selection lines are electrically coupled to the plurality of strings The string selection gates have different string selection gate structures and a string of selection line decoding devices.