TWI431695B - Fabrication methods for trench mosfet - Google Patents

Description

Method for manufacturing trench type metal oxide semiconductor field effect transistor

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a trench metal oxide semiconductor field effect transistor (trench MOSFET).

The high-voltage component technology is suitable for the field of high-voltage and high-power integrated circuits. The conventional power transistor is designed to achieve high withstand voltage and high current, and the component current flow direction is designed as a vertical structure by a planar structure. With the technical breakthrough of wafer technology, there are different approaches to power transistors. At present, the development of extremely low voltage power transistor technology has a trench gate with a variety of process structure power transistors (Trench MOSFET).

Since the trench field effect transistor can effectively reduce the on-resistance of the product and has a large current processing capability, in recent years, the trench type metal oxide semiconductor field effect transistor has been rapidly developed in the fields of computers and consumer electronics. Currently, Trench MOSFET technology has been widely accepted in the low voltage MOSFET product market and has a high market share. In the high-voltage MOSFET market, although the voltage withstand capability of the Trench MOSFET process technology has been improved, there is still a certain gap in the withstand voltage capability of the Trench MOSFET compared to the Plannar product. In the future, planar technology with high-end processes will be the development trend of high-voltage MOSFETs.

Figure 1 is a schematic cross-sectional view showing a conventional trench metal oxide semiconductor field effect transistor (trench MOSFET). Referring to FIG. 1A, there is a trench structure in a semiconductor substrate 100. The semiconductor substrate 100 further includes an N-type doping region 102, a P-type well region (PW) 104, and an N ⁺ -type heavily doped region 106, respectively serving as a drain and a channel of the trench transistor. District and source. An oxide layer 120 conformally forms and covers the trench structure and the surface of the semiconductor substrate as a gate dielectric layer of the trench transistor. A doped polysilicon 130 is deposited and fills the trench as the gate of the trench transistor. However, the trench gate structure power transistor has difficulty in the process, and the depth of the transistor trench gate must be considered. In particular, the thickness of the oxide layer at the bottom of the trench of the conventional trench MOSFET is the same as the thickness of the oxide layer at other locations, which is liable to cause a parasitic capacitance (Qgd) effect. Therefore, there is a need in the industry for a trench metal oxide semiconductor field effect transistor and a manufacturing method capable of effectively reducing the parasitic capacitance (Qgd) effect.

An embodiment of the present invention provides a method for fabricating a trench metal oxide semiconductor field effect transistor, comprising: providing a substrate having a trench structure in the substrate; forming a sacrificial oxide layer to conformally cover the trench a groove structure and a surface of the substrate; forming an oxide layer in a vertical direction to thicken the portion of the sacrificial oxide layer on the surface of the substrate and the bottom portion of the trench; removing the oxide layer and a portion of the sacrificial oxide layer, Depositing a portion of the oxide layer on the surface of the substrate and at the bottom of the trench; growing an additional oxide layer conformally overlying the substrate structure; and depositing a conductive layer on the substrate structure and filling the substrate A trench is used as the gate of the trench transistor.

Another embodiment of the present invention provides a method of fabricating a trench metal oxide semiconductor field effect transistor, comprising: providing a semiconductor substrate having a trench structure in the substrate, the semiconductor substrate including an N-type in a vertical direction a doped region, a P-type well region, and an N-type heavily doped region are respectively used as a drain, a channel region and a source of the trench transistor; a sacrificial oxide layer is formed to conformally cover the trench a trench structure and the surface of the semiconductor substrate; applying a high-density plasma chemical vapor deposition method to form an oxide layer in a vertical direction, so that the sacrificial oxide layer is thickened on a surface of the substrate and a portion at a bottom portion of the trench; Removing the oxide layer and a portion of the sacrificial oxide layer, leaving a portion of the oxide layer on the surface of the substrate and at the bottom of the trench; growing an additional oxide layer conformally overlying the substrate structure; forming a doped polysilicon is deposited on the substrate structure and fills the trench; a chemical mechanical polishing is applied to remove the excess doped germanium on the surface; and a portion of the germanium oxide layer on the surface of the base structure is removed to expose the trench The top of the doped polysilicon is used as the gate of the trench transistor.

In order to make the invention more apparent, the following detailed description of the embodiments and the accompanying drawings are as follows:

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

In view of this, the main features and aspects of the present invention are in the form of grooved gold. The dielectric layer of the trench at the bottom of the oxide semiconductor field effect transistor is thickened, so that the parasitic capacitance (Qgd) effect of the device can be effectively reduced, and the manufacturing cost can be effectively reduced by a process technology compatible with the conventional process. .

2A-2I is a schematic cross-sectional view showing a method of fabricating a trench type metal oxide semiconductor field effect transistor according to an embodiment of the present invention at each process step. Referring to FIG. 2A, first, a substrate 200, such as a semiconductor substrate, including a single crystal germanium substrate, an epitaxial germanium substrate, a germanium substrate, a germanium-on-insulator (SOI) substrate, and a compound semiconductor substrate are provided. A trench structure 210 is formed in the substrate 200. Alternatively, an isotropic etching, such as wet etching, may be employed to micro-removal the surface 212 of the trench 210.

Referring to FIG. 2B, a sacrificial oxide layer (SAC oxide) 215 is formed to conformally cover the trench structure 210 and the surface of the semiconductor substrate 200. In one embodiment, an oxide layer may be grown on the surface of the semiconductor substrate 200 by thermal oxidation.

Next, referring to FIG. 2C, a portion of the oxide layer 217 is formed in a vertical direction, for example, by a high density plasma chemical vapor deposition (HDP CVD), the sacrificial oxide layer 215 is applied to the surface of the substrate and The portion at the bottom of the groove is thickened. It should be noted that the step of depositing the oxide layer 217 is not limited to HDP CVD, and other suitable directional thin film deposition processes may be selected.

Next, referring to FIG. 2D, the oxide layer 217 and a portion of the sacrificial oxide layer 215 are removed such that a portion of the oxide layer 215' remains on the surface of the substrate and at the bottom of the trench. For example, immersing in a wet etching solution leaves a portion of the oxide layer 215' on the surface of the substrate and the bottom of the trench. In addition, you can choose to apply An isotropic etching, such as wet etching, slightly removes the sidewall surface 219 of the trench 210.

Referring to FIG. 2E, an additional oxide layer 222 is grown, conformally overlying the underlying substrate structure. Therefore, the oxide layer 222 at the bottom of the trench 210 may be thicker than the oxide layer of other portions of the trench 210. Next, a doped polysilicon gate 230 is formed on the base structure and fills the trench, as shown in FIG. 2F.

Referring to FIG. 2G, a chemical mechanical polishing 240 is applied to remove excess doped polysilicon 230 from the surface such that the doped polysilicon 230 is on the same level as the oxide layer 222 on the surface of the substrate. Next, the partial ruthenium oxide layer 222 of the surface of the base structure is removed, for example, a portion of the ruthenium oxide layer 222 is removed by wet dip 245 so as to expose the top of the doped polysilicon 230 above the trench, such as Figure 2H shows.

It should be noted that the top of the doped polysilicon can be optionally removed by chemical mechanical polishing 250, as shown in FIG. In an embodiment, after the above structure is completed, an N-type doping region 202, a P-type well region (PW) 204, and an N ⁺ -type heavily doped region 206 may be formed in the substrate 200. They are used as the drain, channel and source of the trench transistor. According to the embodiment of the present invention, since the oxidized layer thickening step in one direction is used, the oxide layer at the bottom of the trench is thicker than the oxide layer in other portions of the trench, thereby effectively reducing the parasitic capacitance (Qgd) effect of the device. Improve the electrical performance of high voltage semiconductor devices and reduce manufacturing costs.

The present invention has been disclosed above in various embodiments, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims.

100‧‧‧Semiconductor substrate

102‧‧‧N-doped area

104‧‧‧P type well area (PW)

106‧‧‧N ⁺ type heavily doped area

120‧‧‧Oxide layer

130‧‧‧Doped polysilicon

200‧‧‧Base

202‧‧‧N-doped area

204‧‧‧P type well area (PW)

206‧‧‧N ⁺ type heavily doped area

210‧‧‧ trench structure

212‧‧‧The surface of the trench

215‧‧‧Sacrificial oxide layer (SAC oxide)

215'‧‧‧ Residual part of the oxide layer

217‧‧‧Oxide layer

219‧‧‧ sidewall surface of the trench

222‧‧‧Additional oxide layer

230‧‧‧Doped polysilicon gate

240‧‧‧Chemical mechanical grinding

245‧‧‧wet dip (wet dip)

250‧‧‧Chemical mechanical grinding

Figure 1 is a schematic cross-sectional view showing a conventional trench metal oxide semiconductor field effect transistor (trench MOSFET).

2A-2I is a schematic cross-sectional view showing a method of fabricating a trench type metal oxide semiconductor field effect transistor according to an embodiment of the present invention at each process step.

200‧‧‧Base

210‧‧‧ trench structure

215‧‧‧Sacrificial oxide layer (SAC oxide)

217‧‧‧Oxide layer

Claims (13)

A method of fabricating a trench metal oxide semiconductor field effect transistor, comprising: providing a substrate having a trench structure in the substrate; forming a sacrificial oxide layer compliantly covering the trench structure and a surface of the substrate Forming an oxide layer in a vertical direction to thicken the surface of the sacrificial oxide layer on the surface of the substrate and the bottom portion of the trench; immediately after forming the oxide layer in the vertical direction, removing the oxide layer and the portion a sacrificial oxide layer leaving a portion of the oxide layer on the surface of the substrate and at the bottom of the trench; growing an additional oxide layer compliantly overlying the substrate structure; and depositing a conductive layer on the substrate structure The trench is filled up and used as the gate of the trench transistor. The method for manufacturing a trench metal oxide semiconductor field effect transistor according to claim 1, wherein the substrate is a semiconductor substrate, including a single crystal germanium substrate, an epitaxial germanium substrate, a germanium substrate, and an insulating layer. A bismuth (SOI) substrate, and a compound semiconductor substrate. The method for fabricating a trench metal oxide semiconductor field effect transistor according to claim 1, further comprising forming an N-type doped region, a P-type well region, and an N-type heavily doped region. Among them, the drain, the channel region and the source of the trench transistor are respectively used. The method for fabricating a trench metal oxide semiconductor field effect transistor according to claim 1, wherein the step of forming a sacrificial oxide layer Before the step, an isotropic etching is applied to micro-removal the surface of the trench. The method for manufacturing a trench type metal oxide semiconductor field effect transistor according to claim 1, wherein the step of forming an oxide layer in a vertical direction comprises applying a high density plasma chemical vapor deposition method. . The method for manufacturing a trench metal oxide semiconductor field effect transistor according to claim 1, wherein after the step of removing the oxide layer and a portion of the sacrificial oxide layer, the method further comprises: The etch is etched to slightly remove the surface of the trench. The method for fabricating a trench metal oxide semiconductor field effect transistor according to claim 1, wherein the depositing a conductive layer on the base structure and filling the trench comprises: forming a doped polysilicon The substrate structure fills the trench; applying a chemical mechanical polishing to remove the excess doped germanium on the surface; and removing a portion of the germanium oxide layer on the surface of the base structure to expose the doped polysilicon above the trench the top of. The method for fabricating a trench metal oxide semiconductor field effect transistor according to claim 7, further comprising applying a chemical mechanical polishing method to remove the top of the doped polysilicon. A method of fabricating a trench metal oxide semiconductor field effect transistor, comprising: providing a semiconductor substrate having a trench structure in the substrate, the semiconductor substrate including an N-type doped region and a P-type well region in a vertical direction And an N-type heavily doped region, respectively serving as a drain, a channel region and a source of the trench transistor; Forming a sacrificial oxide layer compliantly covering the trench structure and the surface of the semiconductor substrate; applying a high-density plasma chemical vapor deposition method to form an oxide layer in a vertical direction to make the sacrificial oxide layer on the substrate The surface and a portion at the bottom of the trench are thickened; immediately after the formation of the oxide layer in the vertical direction, the oxide layer and a portion of the sacrificial oxide layer are removed, leaving a surface on the substrate and at the bottom of the trench a portion of the oxide layer; growing an additional oxide layer, conformally overlying the substrate structure; forming a doped polysilicon on the substrate structure and filling the trench; applying a chemical mechanical polishing to remove excess surface The doped polysilicon layer; and a portion of the yttrium oxide layer on the surface of the base structure is removed to expose the top of the doped polysilicon above the trench as the gate of the trench transistor. The method for manufacturing a trench metal oxide semiconductor field effect transistor according to claim 9, wherein the substrate is a semiconductor substrate, including a single crystal germanium substrate, an epitaxial germanium substrate, a germanium substrate, and an insulating layer. A bismuth (SOI) substrate, and a compound semiconductor substrate. The method for fabricating a trench metal oxide semiconductor field effect transistor according to claim 9, wherein before the step of forming a sacrificial oxide layer, the method further comprises: applying an isotropic etching to micro-removal The surface of the groove. The method for manufacturing a trench type metal oxide semiconductor field effect transistor according to claim 9, wherein the removing the oxide layer and After the step of sacrificing the oxide layer, the method further comprises applying an isotropic etching to slightly remove the surface of the trench. The method for fabricating a trench metal oxide semiconductor field effect transistor according to claim 9, further comprising applying a chemical mechanical polishing method to remove the top of the doped polysilicon.