TWI429358B - Bonding pad structure - Google Patents

Description

Connection pad structure

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a connection pad structure, and more particularly to a connection pad structure for adjusting the distribution of vias to avoid stress concentration regions during wire bonding.

Generally, when a semiconductor wafer is packaged in a package component, a bonding pad is a connection interface between the semiconductor wafer and the package component, and signals in the semiconductor wafer must be transferred to the package component via the connection pad.

With the development of semiconductor technology, the line density in integrated circuits (ICs) is getting higher and higher, so that semiconductor wafers with integrated circuits also require more and more signal transmission paths. Here, in order to respond to today's high line density IC designs, it is common practice to reduce the pitch and size of the connection pads to increase the number of connection pads. However, in the process of coupling the pins and the connection pads in the package component, the high mechanical stress on the surface of the connection pad tends to cause cracking or peeling of the internal structure of the connection pad.

For example, when a soldering wire is used to bond a wire to a surface of a connection pad, the conventional connection pad structure cannot withstand high mechanical stress and is easily damaged. Please refer to FIG. 1. FIG. 1 is a top plan view showing a structure of a connection pad in the prior art. As shown in FIG. 1, the conventional connection pad structure 9 has the through holes 92 disposed in the dielectric material layer 90. Due to the different arrangement of the through holes 92, it is possible to form a plurality of blank areas in the dielectric material layer 90. 94, this blank region 94 represents the region of the dielectric material layer 90 without the vias 92. However, the position where the blank region 94 appears is not fixed and does not necessarily disperse the mechanical stress effectively. Therefore, during the wire bonding process, the dielectric material layer 90 between the via holes 92 is still subjected to high mechanical stress and cracks, etc. Happening. In other words, the dielectric material layer 90 of the conventional connection pad structure 9 cannot be strengthened by the blank region 94 against mechanical stress.

On the other hand, please refer to FIG. 2. FIG. 2 is a top view showing another connection pad structure in the prior art. As shown in FIG. 2, the conventional connection pad structure 9' has all the through holes 92 disposed in an extension portion 96, so that the dielectric material layer 90 becomes a large-area blank area and has better mechanical stress resistance. Thereby, the dielectric material layer 90 can be prevented from being subjected to high mechanical stress and cracking, but also because the dielectric material layer 90 in the blank region does not have the through holes 92, so that the dielectric material layer 90 and other material layers in the blank region are formed. The connection relationship between the two is weak, and it is easy to cause peeling. In addition, as the function of the IC becomes more and more complicated, the number of the through holes 92 is inevitably increased, but the area of the extension portion 96 is very limited. If the space of the dielectric material layer 90 cannot be fully utilized, it will not be able to cope with the future. The trend is not sufficient to configure all of the through holes 92 in the limited space of the extension 96.

An embodiment of the present invention provides a connection pad structure, which prevents a through hole from being disposed in a stress concentration region of a dielectric material layer, so as to prevent excessive mechanical stress from being directly applied to the periphery of the through hole, thereby preventing the passage of the through hole. The layer of dielectric material around the hole is cracked or peeled off.

Embodiments of the present invention provide a connection pad structure including a first conductive material layer, a second conductive material layer, a dielectric material layer, a plurality of first via holes, and a third conductive material layer. The dielectric material layer is formed on the second conductive material layer, and when the solder wire is wire bonded to the first conductive material layer, a stress concentration region is correspondingly generated in the dielectric material layer. A plurality of first via holes are disposed in the dielectric material layer, each of the first via holes is located outside the stress concentration region, and the plurality of first via holes surround the stress concentration region. The third conductive material layer is formed in the plurality of first via holes for electrically connecting the first conductive material layer and the second conductive material layer.

In an exemplary embodiment of the present invention, when the soldering wire is wire-bonded to the first conductive material layer, a layer of stress concentration is generated in the dielectric material layer, and a part of the plurality of first through holes surround The annular stress concentration region is outside, and a part of the plurality of first through holes are located inside the annular stress concentration region. Here, the soldering wire vibrates and welds the bonding wire to the first conductive material layer, and the bonding wire is used to electrically connect the first conductive material layer and the inner lead of one of the lead frames. In addition, the welding pin guides the bonding wire and fixes the bonding wire to the first conductive material layer, and the shape and size of the stress concentration region correspond to the shape and size of the welding pin.

In summary, the connection pad structure provided by the embodiment of the present invention avoids the position where the through hole is disposed in the stress concentration region of the dielectric material layer, so as to avoid excessively high mechanical stress applied directly to the through hole. Surrounding, while preventing the layer of dielectric material around the through hole from cracking or peeling. Further, the connection pad structure of the present invention does not need to leave a large area of blank space in the dielectric material layer, and only needs to design the through hole outside the stress concentration area, so that the space of the dielectric material layer can be more effectively utilized. Compared with the conventional technology, not only the cracking or peeling of the dielectric material layer can be effectively avoided, but also the configurable number of the through holes can be improved.

For a better understanding of the features and technical aspects of the present invention, reference should be made to the accompanying drawings.

[Connection pad structure embodiment]

Please refer to FIG. 3A and FIG. 3B together. FIG. 3A is a cross-sectional view showing the structure of the connection pad according to an exemplary embodiment of the present invention. Fig. 3B is a plan view showing the plane of the line A-A' in Fig. 3A. As shown, the connection pad structure 1 applied to a semiconductor wafer includes a first conductive material layer 10, a dielectric material layer 12, and a second conductive material layer 14, and the dielectric material layer 12 is located on the first conductive material layer 10 and The second conductive material layer 18 has a plurality of first through holes 16 , and the third conductive material layer 18 is filled in the first through holes 16 for electrically connecting the first conductive material layer 10 . And a second layer of conductive material 14. In addition, the connection pad structure 1 further has a protective layer 20 covering a part of the surface of the first conductive material layer 10. The relative relationship and function of the various components in the connection pad structure 1 will be separately described below.

The first conductive material layer 10 is used for wire bonding of the bonding wires for electrically connecting the first conductive material layer 10 and one of the lead pins (not shown). In practice, the connection pad structure 1 may have a plurality of metal layers, and the first conductive material layer 10 is the uppermost metal layer. Here, the first conductive material layer 10 is formed on the dielectric material layer 12, the upper surface of the first conductive material layer 10 is exposed to the environment, and is used for contacting the solder pins (not shown in FIGS. 3A and 3B) and is suitable for The wire bonding is performed (not shown in FIGS. 3A and 3B), and the lower surface of the first conductive material layer 10 is used to contact the upper surface of the dielectric material layer 12. Of course, a protective layer 20 may be formed on the first conductive material layer 10 for sealing the semiconductor wafer, which can avoid contamination of the contaminant and provide protection against scratches.

The dielectric material layer 12 is formed on the second conductive material layer 14 . When the solder wire is wire bonded to the first conductive material layer 10 , a stress concentration region 22 is correspondingly formed in the dielectric material layer 12 . Referring to FIG. 3C together, FIG. 3C is a schematic view showing the bonding of the bonding wires to the first conductive material layer according to an exemplary embodiment of the invention. As shown, the solder pins 30 direct the bond wires 32 and secure the bond wires 32 to the first layer of conductive material 10. After the soldering pin 30 fixes the bonding wire 32, the bonding wire 32 is ultrasonically vibrated and pressed against the upper surface of the first conductive material layer 10. In practice, when the soldering pin 30 vibrates ultrasonically and presses the bonding wire 32, the first conductive material layer 10 is subjected to maximum mechanical stress with respect to the periphery of the soldering pin 30, and the stress concentration region 22 can be defined.

For example, the user may first measure the state of force distribution when the welding wire is wire-bonded using a standard piece, and the standard piece may be a layer of dielectric material having an evenly distributed through hole. Then, the user can determine the size of the stress concentration region by measuring the state of the force distribution. In other words, when the specified mechanical stress is greater than a threshold value and the damage of the dielectric material layer is easily generated, the designated region is a stress concentration region. It should be apparent to those having ordinary skill in the art that the stress concentration region can be appropriately adjusted corresponding to the type, material, thickness, and the like of the dielectric material layer, and the present invention does not limit the size of the stress concentration region herein.

Here, since the welding pin 30 does not only apply the pressing force, ultrasonic vibration is applied to the first conductive material layer 10, so the stress concentration region 22 can be slightly larger than the actual position of the welding pin 30 to extend to the corresponding welding pin. Within a certain range around. In practice, since the solder pins are of a tubular structure, the maximum mechanical stress applied to the first conductive material layer 10 should be concentrated around a ring to form an annular stress concentration region 22. Of course, those skilled in the art should understand that the shape of the stress concentration region 22 corresponds to the shape of the soldering pin 30. Therefore, the present invention does not limit the shape of the stress concentration region 22, and the shape of the soldering pin 30 changes. The concentration area 22 can of course be changed accordingly. For example, when the shape of the welding pin 30 is square, the shape of the stress concentration region 22 should correspond to a square shape.

It should be noted that although the dielectric material layer 12 only shows a single deposited layer in FIG. 3A, it should be apparent to those skilled in the art that the dielectric material layer 12 can also be used to indicate the overlapping of multiple dielectric layers. A layer of composite dielectric material. For example, when the composite dielectric material layer can be a double-layer oxide structure, one of the layers can be made of high density plasma (HDP), and the other layer can be made of tetraethoxy. Fabrication of tetraethylorthosilicate (TEOS) by plasma enhanced vapor deposition.

A plurality of first through holes 16 are disposed in the dielectric material layer 12, each of the first through holes 16 has a first opening portion and a second opening portion, and the first opening portion and the second opening portion respectively contact the first opening portion The conductive material layer 10 and the second conductive material layer 14 are each located outside the stress concentration region 22, and the plurality of first through holes 16 surround the stress concentration region 22. Here, the plurality of first via holes 16 may be arrayed in the dielectric material layer 12 outside the stress concentration region 22 for communicating the first conductive material layer 10 and the second conductive material layer 14 each. The first through hole 16 has a fixed distance from the adjacent first through hole 16. In addition, the shape of the first through hole 16 in the planar shape of the dielectric material layer 12 is not limited herein. For example, the first through hole 16 may be circular, square, rectangular or other suitable shape.

In practice, a plurality of adjacent first through holes 16 may form a group of through holes, and the group of through holes may be arranged in a specified pattern. For example, if the first through hole 16 has a rectangular shape in plan view of the dielectric material layer 12, the through hole group may include a plurality of first through holes 16 arranged in different directions to help reduce the dielectric material layer. 12 internal stresses are taken to reduce the occurrence of cracks between adjacent first through holes 16. In addition, adjacent via groups may also have appropriate spacing between them, such that a plurality of via groups are arranged in a specified pattern to increase the ability of the dielectric material layer 12 to resist stress.

The third conductive material layer 18 is formed in the plurality of first via holes 16 for electrically connecting the first conductive material layer 10 and the second conductive material layer 14 . In practice, the plurality of first via holes 16 may be filled with the third conductive material layer 18 by using a tungsten plug process, an aluminum plug process, a copper plug process, a germanium plug process, or other suitable filling. The process of the present invention is not limited herein. After the third conductive material layer 18 is filled in the plurality of first via holes 16, a chemical mechanical polishing (CMP) or other suitable polishing process may be used to planarize the surface of the dielectric material layer 12.

In general, the connection pad structure 1 of the present invention can form a blank region in the dielectric material layer 12 in the stress concentration region 22, and arrange the first via holes 16 in an array outside the stress concentration region 22. When the solder wire is bonded to the bonding wire, the dielectric material layer 12 between the adjacent first through holes 16 can be prevented from being subjected to excessive mechanical stress and cracked.

[Another connection pad structure embodiment]

Referring to FIG. 4, FIG. 4 is a top view of a connection pad structure according to another exemplary embodiment of the present invention. As shown in FIG. 4, the connection pad structure 1' applied to a semiconductor wafer may further include an extended conductive material layer 24, a plurality of second via holes 26, and a fourth conductive material layer 28. Here, the extended conductive material layer is used to electrically connect the first conductive material layer 10 to form a protruding region. In practice, the extended conductive material layer 24 can be considered as an extension of the first conductive material layer 10, or the first conductive material layer 10 can be specifically divided into a region to extend the conductive material layer 24. In general, the extended conductive material layer 24 should be covered under the protective layer 20 to avoid direct contact with the solder pins 30, that is, the solder pins 30 wire bond the bonding wires 32 to the surface of the first conductive material layer 10, and extend the conductive The material layer 24 is electrically connected to the bonding wire 32 through the first conductive material layer 10.

A plurality of second through holes 26 are disposed in the dielectric material layer 12, each of the second through holes 26 has a third opening portion and a fourth opening portion, and the third opening portion and the fourth opening portion respectively contact the extended conductive portion. Material layer 24 and second conductive material layer 14. A fourth conductive material layer 28 is formed in the plurality of second via holes 26 for electrically connecting the extended conductive material layer 24 and the second conductive material layer 14. In practice, when the first conductive material layer 10 can specifically define a region to extend the conductive material layer 24, the second via hole 26 is the same as the first via hole 16 and can be completed by the same process step. The fourth conductive material layer 28 is the same as the third conductive material layer 18 and can be completed by the same process step.

Compared with the conventional technology, the first through hole 16 and the second through hole 26 are simultaneously present on the first conductive material layer 10 and the extended conductive material layer 24 of the present invention, so that the semiconductor wafer is connected. The number of holes is greatly increased, so that the same connection pad structure 1' can transmit and receive more signals. Therefore, compared with the conventional technology, the present invention is more compatible with semiconductor chips having increasingly complex functions and structures due to the greatly increased configurable number of via holes.

[Further connection pad structure embodiment]

Please refer to FIG. 3B and FIG. 5 together. FIG. 5 is a plan view showing a structure of a connection pad according to still another exemplary embodiment of the present invention. The main difference between FIG. 3B and FIG. 5 is that the stress concentration regions 22 are different in size, and the maximum mechanical stress is not necessarily an annular hollow range. The user as described in the foregoing embodiment can determine the size of the stress concentration region by measuring the state of the force distribution. That is to say, the stress concentration region 22 of the connection pad structure 1" of the present embodiment is large and a solid range. When the function and structure of the semiconductor wafer are relatively simple, the connection pad structure 1" may not maximize the first via hole. The configurable number of 16.

Although the connection pad structure 1" of the present embodiment has a large blank area, the first through hole 16 is not disposed only around the blank area, but after the stress concentration area 22 is first determined, the first through hole 16 is disposed. Outside the stress concentration region 22, the stress concentration region 22 appears to be a blank region. From the viewpoint of motivation, the blank region is not arbitrarily defined. In fact, the user should first judge the stress of the dielectric material layer 12. In the distributed state, the arrangement position of the first through holes 16 needs to be outside the stress concentration region 22 to effectively reduce the damage of the dielectric material layer 12.

In summary, the connection pad structure provided by the embodiment of the present invention avoids the position where the through hole is disposed in the stress concentration region of the dielectric material layer, so as to avoid excessively high mechanical stress applied directly to the through hole. Surrounding, while preventing the layer of dielectric material around the through hole from cracking or peeling. Further, the connection pad structure of the present invention does not need to leave a large area of blank space in the dielectric material layer, and only needs to design the through hole outside the stress concentration area, so that the space of the dielectric material layer can be more effectively utilized. Compared with the conventional technology, not only the cracking or peeling of the dielectric material layer can be effectively avoided, but also the configurable number of the through holes can be improved.

The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the invention, and the equivalents of the invention are included in the scope of the invention.

1, 1', 1"... connection pad structure

10. . . First conductive material layer

12. . . Dielectric material layer

14. . . Second conductive material layer

16. . . First through hole

18. . . Third conductive material layer

20. . . The protective layer

twenty two. . . Stress concentration area

twenty four. . . Extended conductive material layer

26. . . Second through hole

28. . . Fourth conductive material layer

30. . . Solder pin

32. . . Welding wire

9, 9’. . . Connection pad structure

90. . . Dielectric material layer

92. . . Through hole

94. . . Blank area

96. . . Extension

1 is a top plan view showing a structure of a connection pad in the prior art.

2 is a top plan view showing another connection pad structure in the prior art.

3A is a cross-sectional view showing the structure of a connection pad in accordance with an exemplary embodiment of the present invention.

Fig. 3B is a plan view showing the plane of the line A-A' in Fig. 3A.

3C is a schematic view showing the bonding of a bonding wire to a first conductive material layer according to an exemplary embodiment of the invention.

4 is a top plan view of a connection pad structure in accordance with another exemplary embodiment of the present invention.

FIG. 5 is a top plan view showing a structure of a connection pad according to still another exemplary embodiment of the present invention.

1. . . Connection pad structure

12. . . Dielectric material layer

16. . . First through hole

18. . . Third conductive material layer

twenty two. . . Stress concentration area

Claims (10)

A connection pad structure comprising: a first conductive material layer; a second conductive material layer; a dielectric material layer formed over the second conductive material layer, when a soldering wire bonds a bonding wire to the wire In the first conductive material layer, a stress concentration region is generated in the dielectric material layer, the dielectric material layer has a plurality of first through holes, each of the first through holes is located outside the stress concentration region, and the The first via holes surround the stress concentration region; and a third conductive material layer is formed in the first via holes for electrically connecting the first conductive material layer and the second conductive material layer. The connection pad structure according to claim 1, wherein when the soldering wire is wire-bonded to the first conductive material layer, the stress concentration region corresponding to the ring shape is generated in the dielectric material layer, A portion of the first through holes surround the outer side of the annular stress concentration region, and a portion of the first through holes are located inside the annular stress concentration region. The connection pad structure of claim 1, wherein the bonding wire is used for electrically connecting the first conductive material layer and one of the lead pins of a lead frame. The connection pad structure of claim 1, wherein the welding pin vibrates and presses the wire with the first conductive material layer. The connection pad structure of claim 1, wherein the first via holes are arranged in an array in the dielectric material layer outside the stress concentration region. The connection pad structure of claim 5, wherein the first through holes further form a plurality of first through hole groups, each of the first through hole groups includes at least one first through hole, and The first group of through holes are arranged in a specified pattern. The connection pad structure of claim 1, further comprising: an extended conductive material layer electrically connected to the first conductive material layer, the extended conductive material layer having a plurality of second through holes Each of the second via holes is located outside the stress concentration region; and a fourth conductive material layer is formed in the second via holes for electrically connecting the extended conductive material layer and the second conductive layer Material layer. The connection pad structure of claim 1, wherein the welding pin guides the bonding wire and wire bonding the bonding wire to the first conductive material layer, and the shape and size of the stress concentration region are correspondingly soldered The shape and size of the needle. The connection pad structure of claim 1, wherein a protective layer is formed over the first conductive material layer, the protective layer covering a portion of the surface of the first conductive material layer. The connection pad structure of claim 1, wherein a portion of the first through holes are arranged along an edge of the stress concentration region.