201244575 六、發明說明： 【發明所屬之技術領域】 本發明有關於-種連接墊結構，且特別是有關於調整 通孔_分布以避開打線時之應力集中區域的— 結構。 【先前技術】 -般來說’半導體晶片被封I於封裝元件時，連接塾 (bonding _係為半導體晶片與封裝树之間的連接介面 ’而半導體^中的信號必須經由連接墊傳送至封裝元件 中。 化者牛導體技術的舰，積體電路⑽中的線路密度越 來越兩，使得具有積體電路的半__ 多的信號傳送路徑。在此’為了因應現今高線路密度ic設 計，普遍的做法是縮小連接墊的間距與尺寸，以辦加連接 塾的數量。然而，在祕封裝林之内⑽與^塾的過 程中，於連接縣面所受到的高機械應力容易使連接塾的 内部結構產生龜裂或剝離的情況。 舉例來說，ϋ用銲針(Capillary)將銲線打線接合 bonding)在連接墊表面時，傳統的連接墊結構|法 古 械應力而十分容錢壞。請參見圖〗，圖丨騎示^ = 中一種連接塾結構的俯視圖。如圖i所示，傳統的連接塾 結構9將通孔92設置於介電材料層90中，因通孔％的疏 密排列不同’而有可能於介電材料層9〇中形成數個空白區L 94’此空白區94表示沒有通孔92的介電材料層9〇^域： 然而’此空白區94出現之位置不固定且不—定能有效分散e 4/15 201244575 機械應力’因此於打線接合的過財，通孔％之間的介電 材料層90仍然會受到高機械應力而出現龜裂等情況。換句 傳統的連接塾結構9之介電材料層9〇無法藉由空白 區94而加強抵抗機械應力的能力。 另-方面，請參見圖2，圖2 _示f知 圖。如圖2所示’傳統的連接塾結構9, 伸部％中，使得介電材料層 90—成為^積的空白區而有較佳的機械應力抵抗能力，雖 才料層90受到高機械應力而出現龜裂，但 =為工白區中的介電材料層9G不具有通孔92，使得空白 ==層90與其他材料層之間的連接關係較弱， 易產生剝離的情況。另外，隨著IC的功 ，92的數量必然會越來越多，但延伸部9心;:4 ^ ’右無法充分利用介電材料層90的空間，將益法因： =趨—㈣部96咖物配置所有㈣ 【發明内容】 ^發明實施例在於提供—種連接塾結構，將通孔白卜 、置避開鲜針施加在介電材料層中的應力集中區域/又 ，免過高的機械應力直接施加於通孔 而、通’= 圍的介電材料層產錢裂或_。 ㈣止通孔周 ㈣Ϊ發明實施例提供—種連接構，包括1-導雷 、=層、—第二導電材料層、—介電材料層、多數f i材:d,才料層。介電材料層係形成於第二導 "曰方，*銲針將銲線打線接合於第一導電材料層 5/15 201244575 時，介電材料層中對應產生—應力針區域。多數 通孔設置於介電材料層之中，每一個第一通孔係位於 集中區域外，且所述多個第一通孔圍繞應力集中區域: 三導電材料層係形成於所述多個第一通孔中，用 接第一導電材料層與第二導電材料層。 在本發明-示範實施例中，當薛針將鲜線打線接合於 第-導電材料層時’介電材料層中對應產生環狀之應力集 中區域，部分之所述多個第一通孔圍繞環狀之應力集中區 域外側，且部分之所述多個第一通孔位於環狀之應力集; 區域内側。在此，銲針將銲線以超音波振動並壓於第」導 電材料層，而銲線係用以電性連接第一導電材料層與一導 線架之-㈣腳。此外’銲針引導銲線並將銲線固定於第 一導電材料層，而應力集中區域之形狀與大小係對應銲針 之形狀與大小。 綜上所述，本發明實施例所提供的連接墊結構，將通 孔的設置位置避開銲針施加在介電材料層中的應力集中區 域，以避免過高的機械應力直接施加於通孔周圍，而防止 通孔周圍的介電材料層產生龜裂或剝離。進一步的，本發 明之連接墊結構不需要在介電材料層中留下大面積的空白 區，僅需將通孔設計在應力集中區域之外，因此更能有效 利用介電材料層之空間。相對於傳統技術來說，不僅可有 效避免介電材料層產生龜裂或剝離的情況，更可提升通孔 的可配置數量。 為使能更進一步瞭解本發明之特徵及技術内容，請參 閱以下有關本發明之詳細說明與附圖，然而所附圖式僅提 供參考與說明用，並非用來對本發明加以限制者。 6/15 201244575 【實施方式】 〔連接墊結構實施例〕 一 μ凊一併參見圖3A與圖3b，圖3八係繪示依 不乾貫施例之連接祕構的㈣目。_ Α，連線之平面的俯視圖。如圖所示 、之ί接墊結構1包括第一導電材料層10、介電材料芦12 ^及第二導電材料層14,介電材料層12位於第-導電^才料 層10以及第-塞φΜ 1/( 乐導電材料 多數個第「 之間，且介電材料層12具有 =用 =1广而第三導電材料層18填於第-通孔 a 連接墊結構1更具有保護層20覆罢第一導電 =之:分表面。以下分別說明連接心： 4凡件的相對關係以及功能。 r續t導電材料層1G用以供銲針將銲線打線接合，所述 以電性連接第—導電材料層1Q與—導線架之一内 ^不）。於實務上，連接墊結構】可具有多層的金屬 導電材料層〗G即為最上層之金。在此第-&電材料層1G形成於介電材料層12上方，第—導電材料 暴露㈣境中’並用以接觸銲針(未緣示於圖 ，”圖3B)且適於輝線打線接合(未繪示於目3八與圖犯） 導電材料層10之下表面用以接觸介電材料層12 钱/面。當然’第—導電材料層1()上方更可形成有一保 曰2〇帛以封合半導體晶片，可避免汙染物的汙染及提 供預防刮傷的保護。 1电材料層12係形成於第二導電材料層14上方，當 、+將‘線打線接合於第_導電材料層1㈣，介電材料層 7/15 201244575 12中對應產生-應力集中區域22。請—併參見圖咒 明—雜纽狀銲針將銲❸了線接合 於第-導電材料層的示意圖。如圖所示，銲針 32並將録線32 11定於第—導電材料層1()。銲針如固定在曰 銲線32以超音波振祕壓於第-導電材料： 之m實務上’ t銲針⑽超音波振動並下壓鲜 線32時，第-導電材料層1〇相對於辉針％周圍會 大的機械應力，而可定義出所述應力集中區域曰 舉例來說’使用者可先使用標準片測量於 =線接合時之受力分布狀態，所述標準片可為平ς分 介電材料層。接著，使用者可藉由測的 力刀布狀態’以決定應力集中區域的大小。 = ===大於，值而容易：電: Ή層之破壞時，所述指疋區域即為應力集 技術領域具有通常知識者應可明瞭，應力=域可^ 介電材料層之種類、材料、厚度等做適當魅=對應 此不加以限織力集巾區域的大小。田。，本發明在 在此，由於銲針30並不僅僅施加下壓 音波振動於第-導電材料層1G，因 ’更曰把加超 可略大於騎3〇的魏妓而 集巾區域22 範圍内。於實務上，-定 圍’而形成環狀之應力集中區域22。告妙/、中在一0展周 應可明瞭應力集中區域22之形_^=此技藝者 故本發明在此不限錢力射區 ^之形狀’ 針3〇之形㈣糾，應力集作域 8/15 201244575 舉例來說，銲針30之形狀為方形時，應力集中區域^之 形狀應對應為方形。 值侍注思的是，雖然介電材料層12於圖3八僅繪示單 一沉積層，但於所屬技術領域具有通f知識者應可^瞭， 介電材料層12亦可用以表示疊合多個介電層的的複合式介 電材料層。舉例來說，t所述複合式介電材料層可為雜層 氧化層結構時，其中—層可為高密度電裝“二; pla讓,脈)的方式製作，而另一層可使用四乙氧基魏氣 體(她aethyl〇rth〇silicate, TE0S)之電黎加強式氣相沉 作。 夕數個第一通孔16設置於介電材料層〗2之中，每一 個第-通孔16具有一第一開口部與一第二開口部，第一開 口部與第二開口部分別接觸第一導電材料層1〇與第二導電 材料層14 ’每一個第一通孔16係位於應力集中區域22外 ，且所述多個第一通孔16圍繞應力集中區域22。在此，所 述多個第一通孔16可陣列地排列於應力集中區域22外之 介電材料層12中，用以連通第—導電材料層1()與第二導 電材料層14 ’而每個第-通孔16與相鄰之第一通孔16之 間具有-固定距離。此外’第一通孔16於介電材料層12 的俯視形狀本發明在此不加以限定，舉例來說，第一通孔 16可為圓形、正方形、長方形或者其他適當的形狀。 於貝務上，相鄰的多數個第一通孔16更可形成通孔群 組，而通孔群組可以排列成一指定圖樣。舉例來說，若第 一通孔16於介電材料層12的俯視形狀是長方形時，通孔 群組内可以包含多個不同方向排列的第一通孔16，有助於 降低介電材料層12承受的内部應力，以減輕相鄰第一通孔 9/15 201244575 16之^裂現象的發生。此外，相鄰的通孔群組之間也可 距’而使得多個通孔群組排列成指定圖樣，以 增加介電材料層12抵抗應力的能力。 第二導電材料層18係形成於所述多個第-通孔16中 性連接第—導電材料層1G與第二導電材料層Μ 。於貫務上’於所述多個第—通孔16填充第三導電材料層 之方式可以使關減製程、_塞製程、銅插塞製程 、石夕化物插塞f程或其他it當的填絲程，本發明在此並 不加以限制。當第二導電材料層18填充於所述多個第一通 孔.16之後’更可使用化學機械研磨(chemid mechanical polishing, CMP)或者其他適當的研磨製程以整平介電材料 層12之表面。 整體來說，本發明之連接墊結構丨可在應力集中區域 22内的介電材料層12形成^區域，而將第—通孔⑹車 列地排列於應力集中區域22外。於銲針打線接合銲線時， 可避免相鄰第一通孔16之間的介電材料層12承受過大機 械應力而龜裂。 〔另一連接塾結構實施例〕 請參見圖4，圖4係繪示依據本發明另一示範實施例之 連接墊結構的的俯視圖。如圖4所示，應用於一半導體晶 片之連接墊結構Γ更可包括延伸導電材料層24、多數個第 一通孔26以及第四導電材料層28。在此，延伸導電材料層 用以電性連接第一導電材料層10,而形成一突出區域。於 實務上，延伸導電材料層24可視為第一導電材料層1〇的 延伸部分’或者第一導電材料層10可特別劃分出一區域而 為所述之延伸導電材料層24。一般來說，延伸導電材料層 10/15 201244575 24應覆蓋於保護層2〇 就是銲針30將辑線32 面，而延伸導電材料層 32電性連接。 之下而避免直接與銲針30接觸，也 打線接合於第一導電材料層1〇之表 24透過第一導電材料層]〇與銲線 —夕數個第—通孔26設置於介電材料層12之中，每— 弟二，孔26具有—第三開口部與-第四開口部，第三開 #與第四開口部分別接觸延伸導電材料層24與第二導電 材料層14。第四導電材料層28係形成於所述多個第二通孔 26中’ ^以電性連接延伸導電材料層％與第二導電材料層 14、於Λ務上，當第一導電材料層1〇可特別劃分出一區域 而為所述之延伸導電材料層24日寺，第二通孔26與第-通 孔16相同而可藉同一製程步驟完成，而第四導電材料層28 與第二導電材料層18相同而可藉同一製程步驟完成。 本發明此示範實施例相較於傳統技術來說，因本發明 第一導電材料層10與延伸導電材料層24上同時存在第一 通孔16與第二通孔26,使得連接半導體晶片的通孔數量大 幅增加，而可使同一個連接墊結構丨，可傳遞與接收更多的 k號。因此’相較於傳統技術，本發明由於大幅提升通孔 的可配置數量，而更能搭配功能與結構日益複雜的半導體 晶片。 〔再一連接墊結構實施例〕 請一併參見圖3B與圖5，圖5係繪示依據本發明再一 示範實施例之連接墊結構的的俯視圖。圖3B與圖5之主要 差異在於應力集中區域22的大小不同，而機械應力最大處 未必是一環狀中空範圍。如前述實施例中所述之使用者可 藉由測量到的受力分布狀態，以決定應力集中區域的大小 11/15 201244575 。也就是說，本實施例之連接墊結構i，’的應力集中區域22 較大而為一實心範圍，當半導體晶片功能與結構較為簡單 時’連接墊結構1”亦可不用最大化第一通孔16的玎配置數 量。 雖本實施例之連接墊結構1”具有較大的空白區域，但 第一通孔16並不是僅配置在空白區域周圍而已，而是先決 定應力集中區域22之後，再配置第一通孔16於應力集中 區域22之外，使得應力集中區域22看起來是個空白區域 。從動機上來看，所述空白區域並不是隨意定義的，實際 上使用者應先判斷此一介電材料層12的應力分布狀態，第 一通孔16的配置位置需在應力集中區域22之外以有效降 低介電材料層12的損壞。 綜上所述，本發明實施例所提供的連接墊結構，將通 孔的設置位置避開銲針施加在介電材料層中的應力集中區 域’以避免過高的機械應力直接施加於通孔周圍，而防止 通孔周圍的介電材料層產生龜裂或剝離。進一步的，本發 明之連接墊結構不需要在介電材料層中留下大面積的空白 區，僅需將通孔設計在應力集中區域之外，因此更能有效 利用介電材料層之空間。相對於傳統技術來說，不僅可有 效避免介電材料層產生龜裂或剝離的情況，更可提升通孔 的可配置數量。 以上所述僅為本發明之較佳可行實施例，非因此侷限 本發明之專利範圍，故舉凡運用本發明說明書及圖式内容 所為之等效技術變化，均包含於本發明之範圍内。 【圖式簡單說明】 圖1係繪示習知技術中一種連接整結構的俯視圖。 12/15 201244575 圖2係繪示習知技術中另一種連接墊結構的俯視圖。 圖3A係繪示依據本發明一示範實施例之連接墊結構 的剖面圖。 圖3B係繪示圖3A中A-A’連線之平面的俯視圖。 圖3C係繪示依據本發明一示範實施例之銲針將銲線 打線接合於第一導電材料層的示意圖。 圖4係繪示依據本發明另一示範實施例之連接墊結構 的的俯視圖。 圖5係繪示依據本發明再一示範實施例之連接墊結構 的的俯視圖。 【主要元件符號說明】 1、Γ、Γ :連接墊結構 10 :第一導電材料層 12 :介電材料層 14 :第二導電材料層 16 :第一通孔 18 :第三導電材料層 20 :保護層 22 :應力集中區域 24 :延伸導電材料層 26 :第二通孔 28 :第四導電材料層 30 :銲針 32 :銲線 9、9’ ：連接墊結構 90 :介電材料層 92 :通孔 94 :空白區 96 :延伸部 13/15201244575 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a connection pad structure, and more particularly to a structure for adjusting a through hole_distribution to avoid a stress concentration region when a wire is wound. [Prior Art] Generally speaking, when a semiconductor wafer is encapsulated in a packaged component, bonding (bonding is a connection interface between the semiconductor wafer and the package tree) and signals in the semiconductor must be transferred to the package via the connection pad. In the component, the ship of the cattle conductor technology, the line density in the integrated circuit (10) is more and more two, so that the signal transmission path of the integrated circuit has half __. Here, in order to meet the current high line density ic design The common practice is to reduce the spacing and size of the connection pads to increase the number of connection ports. However, in the process of (10) and ^塾 in the secret packaging forest, the high mechanical stress on the connection to the county is easy to connect. The internal structure of the crucible is cracked or peeled off. For example, when the welding pin (Capillary) is used to bond the bonding wire to the bonding pad surface, the conventional connection pad structure is very difficult. Bad. Please refer to the figure, the figure shows the top view of a connection structure. As shown in FIG. 1, a conventional connection structure 9 has a via hole 92 disposed in the dielectric material layer 90, and a plurality of blanks may be formed in the dielectric material layer 9 due to the difference in the dense arrangement of the via holes. Zone L 94 'This blank zone 94 represents the dielectric material layer 9 without the via 92: However, the location of this blank zone 94 is not fixed and does not - effectively disperse the mechanical stress of e 4/15 201244575' In the case of wire bonding, the dielectric material layer 90 between the via holes is still subject to high mechanical stress and cracking. In other words, the dielectric layer 9 of the conventional connection structure 9 cannot be strengthened by the blank region 94 against mechanical stress. On the other hand, please refer to Figure 2, Figure 2 shows the diagram. As shown in Fig. 2, the 'conventional joint structure 9, the portion of the joint, so that the dielectric material layer 90- becomes a blank area and has better mechanical stress resistance, although the layer 90 is subjected to high mechanical stress. The crack occurs, but the dielectric material layer 9G in the white area does not have the through hole 92, so that the connection relationship between the blank == layer 90 and other material layers is weak, and peeling is likely to occur. In addition, with the work of the IC, the number of 92 will inevitably increase, but the extension 9 heart;: 4 ^ 'right can not make full use of the space of the dielectric material layer 90, will benefit the cause: = trend - (four) 96 coffee configuration all (four) [Summary of the Invention] ^Inventive embodiment is to provide a connection structure, the through hole, the avoidance of the fresh needle applied to the stress concentration area of the dielectric material layer / again, from excessive The mechanical stress is applied directly to the through hole, and the dielectric material layer of the '= surrounding is produced or cracked. (4) Stopping the through hole circumference (4) The invention embodiment provides a connection structure including 1-lead, = layer, - second conductive material layer, - dielectric material layer, most f i material: d, material layer. The dielectric material layer is formed on the second conductor, and the soldering pin bonds the bonding wire to the first conductive material layer 5/15 201244575, and the stressing pin region is correspondingly generated in the dielectric material layer. a plurality of via holes are disposed in the dielectric material layer, each of the first via holes is located outside the concentrated region, and the plurality of first via holes surround the stress concentration region: a layer of three conductive materials is formed on the plurality of layers In a through hole, a first conductive material layer and a second conductive material layer are used. In the exemplary embodiment of the present invention, when the Xue needle is wire bonding the fresh wire to the first conductive material layer, a stress concentration region corresponding to the ring is formed in the dielectric material layer, and a part of the plurality of first through holes surround The annular stress concentration region is outside, and a part of the plurality of first through holes are located in the annular stress set; the inner side of the region. Here, the soldering wire vibrates the bonding wire with ultrasonic waves and presses it on the first conductive material layer, and the bonding wire is used to electrically connect the first conductive material layer with the - (four) leg of a wire guide. In addition, the soldering pin guides the bonding wire and fixes the bonding wire to the first conductive material layer, and the shape and size of the stress concentration region correspond to the shape and size of the soldering pin. In summary, the connection pad structure provided by the embodiment of the present invention avoids the position where the through hole is disposed in the stress concentration region of the dielectric material layer, so as to avoid excessively high mechanical stress applied directly to the through hole. Surrounding, while preventing the layer of dielectric material around the through hole from cracking or peeling. Further, the connection pad structure of the present invention does not need to leave a large area of blank space in the dielectric material layer, and only the through hole is designed outside the stress concentration area, so that the space of the dielectric material layer can be more effectively utilized. Compared with the conventional technology, not only can the crack of the dielectric material layer be cracked or peeled off, but also the configurable number of through holes can be improved. The detailed description of the present invention and the accompanying drawings are to be understood as the 6/15 201244575 [Embodiment] [Connection pad structure embodiment] Referring to Fig. 3A and Fig. 3b, Fig. 3 shows the (4) mesh of the connection structure according to the embodiment. _ Α, a top view of the plane of the connection. As shown, the pad structure 1 includes a first conductive material layer 10, a dielectric material 12 and a second conductive material layer 14, and the dielectric material layer 12 is located on the first conductive layer 10 and the first The plug φ Μ 1 / (the majority of the conductive material between the first ", and the dielectric material layer 12 has = wide = 1 and the third conductive material layer 18 is filled in the first through hole a. The connection pad structure 1 has a protective layer 20 The first conductive = the sub-surface. The following describes the connecting core: 4 the relative relationship and function of the parts. r continued t conductive material layer 1G for the soldering wire to bond the bonding wire, the electrical connection The first conductive material layer 1Q and one of the lead frames are not. In practice, the connection pad structure can have a plurality of layers of metal conductive material, that is, the uppermost layer of gold. Here, the first & electrical material The layer 1G is formed on the dielectric material layer 12, and the first conductive material is exposed (in the fourth) and used to contact the soldering pin (not shown in the figure, FIG. 3B) and is suitable for the bonding of the wire (not shown in FIG. The lower surface of the conductive material layer 10 is used to contact the dielectric material layer 12 money/face. Of course, a protective layer 2 can be formed over the first conductive material layer 1 to seal the semiconductor wafer, thereby avoiding contamination of the contaminant and providing protection against scratches. A layer of electrical material 12 is formed over the second layer of conductive material 14, and when + is bonded to the first layer of conductive material layer 1 (four), the layer of dielectric material 7/15 201244575 12 corresponds to a region 22 of stress-concentration. Please—and see the illustrations—a schematic diagram of a hybrid needle that bonds the wire to the first conductive layer. As shown, the solder pins 32 and the recording line 32 11 are positioned on the first conductive material layer 1 (). If the soldering pin is fixed on the soldering wire 32 and ultrasonically vibrates in the first conductive material: the m conductive needle (10) ultrasonically vibrates and presses the fresh wire 32, the first conductive material layer 1〇 is opposite to There is a large mechanical stress around the glow pin %, and the stress concentration region can be defined. For example, the user can first measure the force distribution state when the wire is joined using the standard piece, and the standard piece can be flat. Divide the layer of dielectric material. Next, the user can determine the size of the stress concentration region by measuring the state of the blade. = === is greater than, value is easy: electricity: When the ruthenium layer is destroyed, the finger 疋 area is the stress set. The general knowledge of the technical field should be clear, stress = domain can ^ the type of dielectric material layer, material , thickness, etc. to make the appropriate charm = corresponding to this size is not limited to the weave area. field. Here, in the present invention, since the welding pin 30 does not only apply the lower pressure sound wave to the first conductive material layer 1G, since the 'more 曰 曰 加 加 can be slightly larger than the riding 〇 妓 妓 妓 妓 妓 妓 妓 妓 妓 妓. In practice, the annular stress concentration region 22 is formed by "defining".妙妙 /, in the middle of a 0 exhibition week should be able to understand the shape of the stress concentration area 22 _ ^ = this artist, the invention in this is not limited to the shape of the power of the area ^ pin 3 〇 shape (four) correction, stress set Field 8/15 201244575 For example, when the shape of the welding pin 30 is square, the shape of the stress concentration area should correspond to a square shape. It is important to note that although the dielectric material layer 12 only shows a single deposited layer in FIG. 38, it should be possible to have a knowledge of the prior art, and the dielectric material layer 12 can also be used to indicate the superposition. A composite dielectric material layer of a plurality of dielectric layers. For example, when the composite dielectric material layer can be a hetero-layer oxide layer structure, wherein the layer can be made of high-density electrical equipment "two; pla let, pulse", and the other layer can use four The oxidized Wei gas (her aethyl 〇rth silicate, TE0S) is electrically reinforced by gas phase deposition. The first plurality of first through holes 16 are disposed in the dielectric material layer 2, each of the first through holes 16 The first opening portion and the second opening portion respectively contact the first conductive material layer 1 and the second conductive material layer 14', and each of the first through holes 16 is located in the stress concentration. Outside the region 22, the plurality of first through holes 16 surround the stress concentration region 22. Here, the plurality of first through holes 16 may be arrayed in the dielectric material layer 12 outside the stress concentration region 22, It is used to connect the first conductive material layer 1 () with the second conductive material layer 14' and each of the first through holes 16 has a fixed distance between the first through holes 16 and the adjacent first through holes 16. Further, the first through holes 16 The shape of the dielectric material layer 12 is not limited herein. For example, the first through hole 16 may be circular. Square, rectangular or other suitable shape. On the peripheral, a plurality of adjacent first through holes 16 can form a group of through holes, and the group of through holes can be arranged into a specified pattern. For example, if the first When the through hole 16 has a rectangular shape in a plan view of the dielectric material layer 12, the through hole group may include a plurality of first through holes 16 arranged in different directions, which helps to reduce internal stress on the dielectric material layer 12, The occurrence of the cracking phenomenon of the adjacent first through holes 9/15 201244575 16 is alleviated. In addition, the adjacent through hole groups may also be spaced from each other such that a plurality of through hole groups are arranged in a specified pattern to increase the mediation. The second conductive material layer 18 is formed on the plurality of first through-holes 16 to be neutrally connected to the first conductive material layer 1G and the second conductive material layer 。. The manner in which the plurality of first vias 16 fill the third conductive material layer may be such as a turn-off process, a stencil process, a copper plug process, a lithium plug, or other wire-filling process, the present invention There is no limitation here. When the second conductive material layer 18 is filled in the After the plurality of first via holes .16, it is more preferable to use a chemical mechanical polishing (CMP) or other suitable polishing process to planarize the surface of the dielectric material layer 12. Overall, the connection pad structure of the present invention The dielectric material layer 12 in the stress concentration region 22 is formed into a region, and the first via hole (6) is arranged in the outer region of the stress concentration region 22. When the bonding wire is bonded to the bonding wire, the adjacent portion can be avoided. The dielectric material layer 12 between the through holes 16 is subjected to excessive mechanical stress and cracks. [Another connection structure embodiment] Referring to FIG. 4, FIG. 4 illustrates a connection pad according to another exemplary embodiment of the present invention. Top view of the structure. As shown in FIG. 4, the connection pad structure applied to a semiconductor wafer may further include an extended conductive material layer 24, a plurality of first via holes 26, and a fourth conductive material layer 28. Here, the extended conductive material layer is used to electrically connect the first conductive material layer 10 to form a protruding region. In practice, the extended conductive material layer 24 can be considered as an extended portion of the first conductive material layer 1' or the first conductive material layer 10 can be specifically divided into regions to extend the conductive material layer 24. Generally, the extended conductive material layer 10/15 201244575 24 should be covered by the protective layer 2, that is, the soldering pin 30 will be connected to the surface 32, and the extended conductive material layer 32 is electrically connected. Underneath, the contact with the soldering pin 30 is avoided, and the wire 24 is bonded to the first conductive material layer 1 through the first conductive material layer 〇 and the bonding wire - the plurality of first through holes 26 are disposed on the dielectric material. In the layer 12, each of the second holes, the holes 26 have a third opening portion and a fourth opening portion, and the third opening portion #4 and the fourth opening portion respectively contact the extending conductive material layer 24 and the second conductive material layer 14. The fourth conductive material layer 28 is formed in the plurality of second via holes 26 to electrically connect the extended conductive material layer % and the second conductive material layer 14 to the gate, when the first conductive material layer 1 The 导电 can be specifically divided into a region for extending the conductive material layer 24, the second through hole 26 is the same as the first through hole 16 and can be completed by the same process step, and the fourth conductive material layer 28 and the second The conductive material layer 18 is the same and can be completed by the same process step. Compared with the conventional technology, the first through hole 16 and the second through hole 26 are simultaneously present on the first conductive material layer 10 and the extended conductive material layer 24 of the present invention, so that the semiconductor wafer is connected. The number of holes is greatly increased, and the same connection pad structure can be made to transmit and receive more k numbers. Therefore, the present invention is more compatible with semiconductor chips having increasingly complex functions and structures due to the greatly increased number of configurable via holes compared to conventional techniques. [Further Connection Pad Structure Embodiment] Referring to Fig. 3B and Fig. 5 together, Fig. 5 is a plan view showing a structure of a connection pad according to still another exemplary embodiment of the present invention. The main difference between Fig. 3B and Fig. 5 is that the stress concentration regions 22 are different in size, and the maximum mechanical stress is not necessarily an annular hollow range. The user as described in the foregoing embodiment can determine the size of the stress concentration region by measuring the state of the force distribution 11/15 201244575. That is to say, the stress concentration region 22 of the connection pad structure i, 'in this embodiment is large and is a solid range. When the function and structure of the semiconductor wafer are relatively simple, the connection pad structure 1 may not maximize the first pass. The number of the cymbal arrangements of the holes 16. Although the connection pad structure 1" of the present embodiment has a large blank area, the first through holes 16 are not disposed only around the blank area, but after the stress concentration area 22 is first determined, The first through hole 16 is then disposed outside of the stress concentration region 22 such that the stress concentration region 22 appears to be a blank region. From the viewpoint of motivation, the blank area is not arbitrarily defined. In fact, the user should first judge the stress distribution state of the dielectric material layer 12, and the arrangement position of the first through hole 16 needs to be outside the stress concentration area 22. In order to effectively reduce the damage of the dielectric material layer 12. In summary, the connection pad structure provided by the embodiment of the present invention avoids the application of the through hole to the stress concentration region of the solder material layer in the dielectric material layer to avoid excessive mechanical stress applied directly to the through hole. Surrounding, while preventing the layer of dielectric material around the through hole from cracking or peeling. Further, the connection pad structure of the present invention does not need to leave a large area of blank space in the dielectric material layer, and only the through hole is designed outside the stress concentration area, so that the space of the dielectric material layer can be more effectively utilized. Compared with the conventional technology, not only can the crack of the dielectric material layer be cracked or peeled off, but also the configurable number of through holes can be improved. The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, and the equivalents of the present invention are included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a connection structure in the prior art. 12/15 201244575 Figure 2 is a top plan view showing another connection pad structure in the prior art. 3A is a cross-sectional view showing the structure of a connection pad in accordance with an exemplary embodiment of the present invention. Fig. 3B is a plan view showing the plane of the line A-A' in Fig. 3A. 3C is a schematic view showing the bonding of a bonding wire to a first conductive material layer in accordance with an exemplary embodiment of the present invention. 4 is a top plan view of a connection pad structure in accordance with another exemplary embodiment of the present invention. Figure 5 is a plan view showing the structure of a connection pad in accordance with still another exemplary embodiment of the present invention. [Main component symbol description] 1. Γ, Γ: connection pad structure 10: first conductive material layer 12: dielectric material layer 14: second conductive material layer 16: first via hole 18: third conductive material layer 20: Protective layer 22: stress concentration region 24: extended conductive material layer 26: second via hole 28: fourth conductive material layer 30: solder pin 32: bonding wire 9, 9': connection pad structure 90: dielectric material layer 92: Through hole 94: blank area 96: extension 13/15