TWI559411B - Semiconductor device and semiconductor process - Google Patents

Description

Semiconductor device and semiconductor process

This invention relates to the field of semiconductor packaging and, more particularly, to a 3-D semiconductor device and a semiconductor process for fabricating the 3-D semiconductor device.

In a stacked chip package, a plurality of integrated circuit chips can be packaged in a single package structure in a vertically stacked manner. This situation increases the stack density, resulting in a smaller package structure and often reduces the length of the path that the signal must traverse between the wafers. Therefore, stacked wafer packages tend to increase the signal transmission speed between the wafers. In addition, stacked chip packages allow wafers with different functions to be integrated into a single package structure. The use of Through Silicon Via (TSV) is a key technology for implementing stacked chip package integration due to its ability to provide short vertical conductive paths between wafers.

One aspect of the invention relates to a semiconductor device. In one embodiment, the semiconductor device includes a substrate; a conductive via formed in the substrate, the conductive via having substantially coplanar with one of the inactive surfaces of the substrate a first end; a circuit layer disposed adjacent to an active surface of the substrate and electrically connected to a second end of the conductive channel; a redistribution layer Adjacent to the inactive surface of the substrate, the redistribution layer has a first portion and a second portion, the first portion is located on the first end and is electrically connected to the first end, and the second portion is positioned upward And away from the first portion; and a die disposed adjacent to the inactive surface of the substrate and electrically connected to the second portion of the redistribution layer. The semiconductor device may further include a dielectric layer between the inactive surface of the substrate and the second portion of the redistribution layer, and a protective layer covering the redistribution layer and the dielectric layer, The protective layer has an opening to expose a portion of the redistribution layer. The openings promote the electrical connection between the die and the redistribution layer. In addition, the semiconductor device may include a plurality of under bump metallurgy (UBM) adjacent to the active surface of the substrate and electrically connected to the circuit layer. The circuit layer and the die each may include one or more Integrated Passive Devices (IPDs). The conductive via may comprise a conductive via comprising: a seed layer comprising one of the annular portions disposed vertically, and a base portion contiguous with the annular portion and adjacent and substantially parallel And the second metal layer on the inner surface of the seed layer. In other embodiments, the conductive channel can be a solid cylinder.

In another embodiment, the conductive via formed in the substrate of the substrate can protrude from the inactive surface of the substrate. In this case, the redistribution layer can be located on all surfaces (including side surfaces) of the protruding tip of the conductive channel to provide enhanced electrical contact and tighter attachment.

Another aspect of the invention relates to the fabrication of a semiconductor device. In one embodiment, a method of fabricating a semiconductor device includes: (a) providing a wafer having a substrate and a circuit layer, wherein the substrate has an active surface and an inactive surface, and the substrate a circuit layer adjacent to the active surface; (b) forming a plurality of under bump metallization layers (UBM) on the circuit layer; (c) attaching a carrier to the wafer, wherein the under bump metal layers (UBM) facing the carrier; (d) forming a redistribution layer on the inactive surface; (e) attaching a die adjacent to the inactive surface, wherein the die is electrically connected to the redistribution layer; (f) forming a gel adjacent to the inactive surface to coat the die. In the step (a), the circuit layer may include a plurality of first pads, a plurality of second pads, a first protective layer and a first dielectric layer; The first dielectric layer is located on the active surface of the substrate; the first pads and the second pads are located on the first dielectric layer; the first protective layer covers the first pads and There are a plurality of openings to expose the second pads. In the step (b), the under bump metal layers (UBM) may be formed in the openings of the first protective layer to contact the second pads. After the step (c), the semiconductor process may include the steps of: (c1) forming a plurality of interconnect metals in the substrate to electrically connect the circuit layer; and (c2) forming a redistribution layer adjacent to the inactive surface, Wherein the redistribution layer is electrically connected to the interconnect metal. In addition, step (c1) may comprise the steps of: (c11) forming a plurality of cylindrical cavities from the inactive surface of the substrate, wherein the cylindrical cavities expose a portion of the circuit layer; (c12) Forming the interconnecting metal in the cylindrical cavity; (c13) forming a plurality of circular grooves from the inactive surface of the substrate, wherein each of the circular grooves surrounds each of the interconnecting metals; C14) forming an insulating ring in each of the circular grooves.

1‧‧‧Semiconductor device

1a‧‧‧Semiconductor device

1b‧‧‧Semiconductor device

2‧‧‧ grain

3‧‧‧ Sealant

10‧‧‧ wafer

11‧‧‧Substrate

12‧‧‧First dielectric layer

13‧‧‧ circuit layer

14a‧‧‧First mat

14b‧‧‧second mat

15‧‧‧First Integrated Passive Device (IPD)

16‧‧‧First protective layer

18‧‧‧First seed layer

20‧‧‧ photoresist layer

21‧‧‧welding line

22‧‧‧First metal layer

24‧‧‧Under Bump Metal Layer (UBM)

26‧‧‧ Carrier

28‧‧‧Adhesive layer

29‧‧‧Second Integrated Passive Device (IPD)

30‧‧‧Photoresist layer

32‧‧‧Second seed layer

34‧‧‧Second metal layer

35‧‧‧Interconnect metal

36‧‧‧Center insulation

37‧‧‧ first end

38‧‧‧Photoresist layer

40‧‧‧Second dielectric layer

42‧‧‧ third seed layer

44‧‧‧ photoresist layer

46‧‧‧ Third metal layer

48‧‧‧ redistribution layer

50‧‧‧Second protective layer

52‧‧‧Surface treatment layer

54‧‧‧ solder balls

56‧‧‧Photoresist layer

111‧‧‧Active surface

112‧‧‧Inactive surface

113‧‧‧ cylindrical cavity

114‧‧‧Circular groove

115‧‧‧through hole

116‧‧‧ central part

121‧‧‧ openings

161‧‧‧ openings

201‧‧‧ openings

202‧‧‧Active surface

203‧‧‧Inactive surface

204‧‧‧ pads

211‧‧‧ first spherical

301‧‧‧ openings

351‧‧‧ internal part

361‧‧‧Insulation ring

381‧‧‧ openings

401‧‧‧ openings

441‧‧‧ openings

501‧‧‧ openings

561‧‧‧ ring opening

1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; FIG. 2(a) is a partially enlarged cross-sectional view showing the semiconductor device of FIG. 1, and FIG. 2(b) is a view showing a semiconductor according to another embodiment of the present invention; FIG. 3 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention; and FIGS. 4 to 19 are diagrams showing a semiconductor process for fabricating a semiconductor device according to an embodiment of the present invention; 20 to 23 show a semiconductor process for fabricating a semiconductor device in accordance with another embodiment of the present invention. Common reference numerals are used throughout the drawings and the detailed description to refer to the same. The invention will be more fully apparent from the following detailed description of the drawings.

Referring to Figure 1, there is shown a cross section of a semiconductor device 1 in accordance with an embodiment of the present invention. Figure. The semiconductor device 1 includes a substrate 11, a first dielectric layer 12, a circuit layer 13, a plurality of under bump metal layers (UBM) 24, a plurality of interconnecting metals 35, a central insulating material 36, and an insulating ring. 361, a second dielectric layer 40, a redistribution layer 48, a second protective layer 50, a die 2, a plurality of bonding wires 21, a plurality of solder balls 54 and a colloid (Molding Compound ) 3.

The substrate 11 has an active surface 111, an inactive surface 112, and a plurality of through holes 115. In this embodiment, the material of the substrate 11 is a semiconductor material such as tantalum or niobium. However, in other embodiments, the material of the substrate 11 may be glass.

The first dielectric layer 12 is located on the active surface 111 of the substrate 11. In this embodiment, the material of the first dielectric layer 12 is tantalum oxide or tantalum nitride. However, in other embodiments, the first dielectric layer 12 can comprise a polymer such as polyimide (PI) or polypropylene (PP).

The circuit layer 13 is disposed adjacent to the active surface 111 of the substrate 11. In this embodiment, the circuit layer 13 is located on the first dielectric layer 12 and includes a plurality of first pads (Pads) 14a, a plurality of second pads 14b, and a first protective layer 16. The first pads 14 a , the second pads 14 b , and the first protective layer 16 are located on the first dielectric layer 12 . The first pads 14a and the second pads 14b are part of one of the metal layers (not shown) of the circuit layer 13. In this embodiment, the material of the metal layers is copper. The first protective layer 16 covers the first pads 14a and has a plurality of openings 161 to expose the second pads 14b. In this embodiment, the first protective layer 16 comprises a polymer such as polyimine (PI) or polypropylene (PP). However, in other embodiments, the material of the first protective layer 16 may be tantalum oxide or tantalum nitride.

In this embodiment, the circuit layer 13 further includes at least one first integrated passive device (IPD) 15 on the first dielectric layer 12 and the first Covered by protective layer 16. Therefore, the first integrated passive device (IPD) 15 is adjacent to the active surface 111 of the substrate 11. In this embodiment, the first integrated passive device The set (IPD) 15 is an inductor. However, the first integrated passive device (IPD) 15 can include a capacitor, a resistor, or a combination of an inductor, a capacitor, and a resistor.

Each of the under bump metallurgy layers (UBM) 24 is located in each of the openings 161 of the first protective layer 16 to contact the second pads 14b such that the under bump metallurgy (UBM) 24 is electrically Connected to the circuit layer 13. In this embodiment, the under bump metallurgy (UBM) 24 includes a first metal layer 22 and a first seed layer 18. The first metal layer 22 is a single layer or a multilayer structure. The material of the first seed layer 18 is tantalum nitride, and the material of the first metal layer 22 is a mixture of nickel (Ni), palladium (Pd) and gold (Au); nickel (Ni) and Gold (Au); or nickel (Ni) and palladium (Pd). However, the first seed layer 18 can be omitted. The solder balls 54 are located on the under bump metallurgy (UBM) 24.

Each of the interconnecting metals 35 is located in each of the through holes 115 of the substrate 11 and electrically connected to the circuit layer 13 and the redistribution layer 48. In this embodiment, the interconnecting metals 35 further extend through the first dielectric layer 12 to contact the first pads 14a. The interconnect metal 35 has a second metal layer 34 and a second seed layer 32 surrounding the second metal layer 34, and the substrate of the second seed layer 32 contacts the first pad 14a. The second seed layer 32 includes an annular portion disposed vertically (relative to the through holes 115), and the base of the second seed layer 32 is adjacent to and adjacent to and substantially parallel to the active portion Face 111. In the present embodiment, the central insulating material 36 is located in the inner portion 351. It will be appreciated that the interconnect metal 35 may instead be a solid cylinder and thus the central insulating material 36 will be omitted. The material of the second seed layer 32 is tantalum nitride or tantalum tungsten, and the material of the second metal layer 34 is copper. However, the second seed layer 32 can be omitted.

In this embodiment, the insulating ring 361 is located in the through hole 115 and surrounds the interconnecting metal 35. As shown in FIG. 1, the insulating ring 361 has a bottom surface, and the bottom surface contacts the first dielectric layer 12; that is, the insulating ring 361 does not extend into the first dielectric layer 12, and the mutual The connecting metal 35 extends partially to the circuit layer 13. Therefore, the bottom surface of the interconnect metal 35 is not coplanar with the bottom surface of the insulating ring 361, and the length of the interconnect metal 35 is large. The length of the insulating ring 361. The material of the central insulating material 36 can be a polymer that is identical to the insulating ring 361.

The second dielectric layer 40 is located on the inactive surface 112 of the substrate 11 and has a plurality of openings 401 for exposing the interconnect metal 35. In this embodiment, the second dielectric layer 40 comprises a polymer such as polyimine (PI) or polypropylene (PP). However, in other embodiments, the material of the second dielectric layer 40 may be tantalum oxide or tantalum nitride.

The redistribution layer 48 is adjacent to the inactive surface 112 of the substrate 11 . In this embodiment, the redistribution layer 48 is located on the second dielectric layer 40 and the opening 401 of the second dielectric layer 40 to contact the interconnect metal 35. In this embodiment, the redistribution layer 48 includes a third seed layer 42 and a third metal layer 46. The material of the third seed layer 42 is tantalum nitride or tantalum tungsten, and the material of the third metal layer 46 is copper. However, the third seed layer 42 can be omitted.

The second protective layer 50 covers the redistribution layer 48 and the second dielectric layer 40 and has a plurality of openings 501 to expose portions of the redistribution layer 48. In this embodiment, a surface finish layer 52 is plated onto the exposed portions of the redistribution layer 48.

The die 2 is adjacent to the inactive surface 112 of the substrate 11 and electrically connected to the redistribution layer 48. In this embodiment, the die 2 has an active surface 202, an inactive surface 203, a plurality of pads 204, and at least one second integrated passive device (IPD) 29. The pads 204 and the second integrated passive device (IPD) 29 are adjacent to the active surface 202 of the die 2 . In this embodiment, the second integrated passive device (IPD) 29 is an inductor. However, the second integrated passive device (IPD) 29 can include a capacitor, a resistor, or a combination of an inductor, a capacitor, and a resistor. In this embodiment, the first integrated passive device (IPD) 15 is adjacent to the active surface 111 of the substrate 11 , and the second integrated passive device (IPD) 29 is adjacent to the active surface of the die 2 . 202. The magnetic field interference between the first integrated passive device (IPD) 15 and the second integrated passive device (IPD) 29 is inversely proportional to the distance. Therefore, if the die 2 is adjacent to the inactive face 112 of the substrate 11, the die 2 will have a larger distance than the die located on the active face 111 of the substrate 11. Based on the following formula:

The frequency Q-factor is related to the inductance (L) and is proportional to the inductance (L) when the resistance (R) and the capacitance (C) are constant. To this end, this embodiment with an enhanced inductor has an enhanced frequency Q factor.

The inactive surface 203 of the die 2 is adhered to the second protective layer 50. The pads 204 are electrically connected to the exposed surface treatment layer 52 of the redistribution layer 48 via the bonding wires 21 . That is, the bonding wires 21 connect the die 2 and the redistribution layer 48. In this embodiment, the bonding type of the bonding wires 21 is a reverse bond. The first step of the reverse bonding is to form a first spherical portion 211 on the pad 204 of the die 2. Next, the tip end of the wire 21 is formed into another spherical portion and bonded to the surface treatment layer 52. Finally, the wire 21 is cut after the wire 21 is pulled to contact the first ball portion 211.

The encapsulant 3 is disposed adjacent to the inactive surface 112 of the substrate 11 and covers the die 2 and the bonding wires 21 . In this embodiment, the encapsulant 3 is located on the second protective layer 50.

Referring to Fig. 2(a), a partially enlarged cross-sectional view of the semiconductor device 1 is shown. As shown, the conductive via (including the interconnect metal 35 in the via 115, the central insulating material 36, and the insulating ring 361) has a substantially coplanar with the inactive surface 112 of the substrate 11. First end 37. Additionally, the insulating ring 361 isolates the conductive via from the substrate 11. The insulating ring 361 is a hollow cylinder formed in the substrate 11. The second seed layer 32 is located on the inner side wall of the insulating ring 361. The second metal layer 34 is on the inner side wall of the second seed layer 32. The second seed layer 32 and the second metal layer 34 are also hollow cylinders similar to the insulating ring 361. The central insulating material 36 is located within the second metal layer 34. Accordingly, the conductive via comprises the outer insulating ring 361, the second seed layer 32, the second metal layer 34, and the central insulating material 36 formed in a concentric annular design.

In this embodiment, the die 2 is adjacent to and electrically connected to the inactive surface 112 of the substrate 11 , and the signal from the die 2 is transmitted to the substrate 11 via the interconnecting metal 35 . The circuit layer 13 on the face 111. That is, the bonding wires 21 are also disposed adjacent to the inactive surface 112 of the substrate 11, thereby preventing the circuit layer 13 on the active surface 111 of the substrate 11 from being damaged during the wire bonding process and the die attach process. . In addition, it is known that the bonding wire is pressed to a bonding pad, and ultrasonic friction is applied between the bonding wire and the bonding pad to complete the wire bonding process. The second pads 14b have a thickness of about 0.3 μm to 1 μm, and the redistribution layer 48 has a thickness of about 2 μm to 5 μm. However, the thickness of the second pad 14b is less than the thickness of the redistribution layer 48 or the surface treatment layer 52. Therefore, if the second bonding pads 14b of the active surface 111 of the substrate 11 are subjected to a wire bonding process, the second pads 14b are easily damaged.

In this embodiment, the second integrated passive device (IPD) 29 is adjacent to the active surface 202 of the die 2, and the first integrated passive device (IPD) 15 is adjacent to the active surface 111 of the substrate 11. . In addition, the inactive surface 203 of the die 2 is adhered to the second protective layer 50 and adjacent to the inactive surface 112 of the substrate 11 . Therefore, the inactive surface 203 of the die 2 and the inactive surface 112 of the substrate 11 are located between the active surface 202 of the die 2 and the active surface 111 of the substrate 11. Therefore, the distance between the second integrated passive device (IPD) 29 and the first integrated passive device (IPD) 15 is relatively large, which results in a high frequency Q factor.

Referring to Fig. 2(b), there is shown a partial enlarged cross-sectional view of a semiconductor device 1a according to another embodiment of the present invention. The semiconductor device 1a of this embodiment is substantially similar to the semiconductor device 1 of FIG. 1, and the same elements are assigned the same element numbers. The difference between the semiconductor device 1a of this embodiment and the semiconductor device 1 of FIG. 1 is that the first end 37 protrudes from the inactive surface 112 of the substrate 11. In this case, the insulating ring 361 is substantially coplanar with the inactive surface 112, but the interconnecting metal 35 and the central insulating material 36 protrude from the inactive surface 112. In this embodiment, the redistribution layer 48 is located on the lateral and end surfaces of the first end 37 of the conductive via, as shown, to provide reinforcement to the interconnect metal 35. The type is electrically contacted and provides a tighter attachment to the first end 37.

Referring to Figure 3, there is shown a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. The semiconductor device 1b of this embodiment is substantially similar to the semiconductor device 1 of FIG. 1, and the same elements are assigned the same element numbers. The difference between the semiconductor device 1b of this embodiment and the semiconductor device 1 of Fig. 1 is described as follows. In this embodiment, the bonding type of the bonding wires 21 is a forward bond. The first step of forward bonding is to bond the wire 21 to the pad 204 of the die 2. Next, the wires 21 are cut after the wires 21 are pulled to contact the surface treatment layer 52.

Referring to Figures 4 through 19, a semiconductor process for fabricating a semiconductor device in accordance with an embodiment of the present invention is shown.

Referring to Figure 4, a wafer 10 is provided. The wafer 10 has a substrate 11 , a first dielectric layer 12 and a circuit layer 13 . Generally, after the Foundry's Process, the first dielectric layer 12 and the circuit layer 13 will have been disposed on the substrate 11. The substrate 11 has an active surface 111 and an inactive surface 112. In this embodiment, the material of the substrate 11 is a semiconductor material such as tantalum or niobium. However, in other embodiments, the material of the substrate 11 may be glass. The first dielectric layer 12 is located on the active surface 111 of the substrate 11. In this embodiment, the material of the first dielectric layer 12 is tantalum oxide or tantalum nitride. However, in other embodiments, the first dielectric layer 12 can comprise a polymer such as polyimine (PI) or polypropylene (PP).

The circuit layer 13 is adjacent to the active surface 111 of the substrate 11 . In this embodiment, the circuit layer 13 is disposed on the first dielectric layer 12 and includes a plurality of first pads 14a, a plurality of second pads 14b, and a first protective layer 16. The first pads 14a and the second pads 14b are part of one of the metal layers (not shown) of the circuit layer 13. In this embodiment, the material of the metal layers is copper. The first protective layer 16 covers the first pads 14a and has a plurality of openings 161 to expose the second pads 14b. In this embodiment, the first protective layer 16 comprises a polymer such as polyimine (PI) or polypropylene (PP). However, in In other embodiments, the material of the first protective layer 16 may be tantalum oxide or tantalum nitride. It should be noted that if only the substrate 11 is provided at this initial step, the process further includes the steps of forming the first dielectric layer 12 and the circuit layer 13.

In this embodiment, the circuit layer 13 further includes at least one first integrated passive device (IPD) 15 on the first dielectric layer 12 and is configured by the first integrated passive device (IPD) 15 Covered by a protective layer 16. Therefore, the first integrated passive device (IPD) 15 is adjacent to the active surface 111 of the substrate 11. In this embodiment, the first integrated passive device (IPD) 15 is an inductor, however, the first integrated passive device (IPD) 15 can be a capacitor, a resistor, or an inductor, a capacitor, and a resistor. combination.

Referring to FIG. 5, a first seed layer 18 is formed on the first protective layer 16 and its opening 161. The first seed layer 18 contacts the second pads 14b of the openings 161. Next, a photoresist layer 20 is formed on the first seed layer 18, and the photoresist layer 20 has a plurality of openings 201 to expose portions of the first seed layer 18. The material of the first seed layer 18 is tantalum nitride. Next, a first metal layer 22 is formed in the opening 201 of the photoresist layer 20. The first metal layer 22 is a single layer or a multi-layer mechanism, and the material of the first metal layer 22 is a mixture of nickel (Ni), palladium (Pd) and gold (Au); nickel (Ni) and gold. (Au); or nickel (Ni) and palladium (Pd).

Referring to Figure 6, the photoresist layer 20 is removed. Next, the first seed layer 18 not covered by the first metal layer 22 is removed to form a plurality of sub-bump metal layers (UBM) 24.

Referring to FIG. 7, the wafer 10 is attached to the carrier 26 by using an adhesive layer 28, wherein the under bump metallurgy (UBM) 24 faces the carrier 26.

Referring to FIG. 8, a photoresist layer 30 is formed on the inactive surface 112 of the substrate 11, and the photoresist layer 30 has a plurality of openings 301 for exposure by an etching process such as wet etching or dry etching. Part of the active surface 112. Next, a plurality of cylindrical cavities 113 are formed from the inactive surface 112 of the substrate 11, which correspond to the openings 301 of the photoresist layer 30. The cylindrical cavity 113 extends through the substrate 11 and the first dielectric layer 12 such that the first dielectric layer 12 has a plurality of openings 121. That is, each of the openings 121 is a portion of each of the cylindrical cavities 113 and extends through the first dielectric layer 12. It should be noted that the positions of the cylindrical cavities 113 must correspond to the positions of the first pads 14a such that the first pads 14a are exposed by the cylindrical cavities 113.

Referring to FIG. 9, a plurality of interconnecting metals 35 are formed in the cylindrical cavities 113 to electrically connect the circuit layers 13. In this embodiment, a second seed layer 32 is formed in the cylindrical cavities 113, and the second seed layer 32 contacts the first pads 14a. Next, a second metal layer 34 is formed on the second seed layer 32. The material of the second seed layer 32 is tantalum nitride or tantalum tungsten, and the material of the second metal layer 34 is copper. The second seed layer 32 and the second metal layer 34 form the interconnect metal 35. However, the second seed layer 32 may be omitted, that is, the second metal layer 34 at this location is the interconnect metal 35. In this embodiment, the interconnect metal 35 defines an inner portion 351.

Referring to Figure 10, a central insulating material 36 is filled in the inner portion 351. In other embodiments, the second metal layer 34 of FIG. 7 can fill the cylindrical cavity 113, that is, the interconnect metal 35 can be a solid cylinder, and the central insulating material 36 can be omitted.

Referring to FIG. 11, a photoresist layer 38 is formed on the inactive surface 112 of the substrate 11, and the photoresist layer 38 has a plurality of openings 381 for exposing the interconnect metal 35. Next, a plurality of circular grooves 114 are formed from the inactive surface 112 of the substrate 11 according to the openings 381, wherein the circular grooves 114 surround the interconnecting metal 35. In this embodiment, the circular grooves 114 extend only through the substrate 11 to form a plurality of through holes 115.

Referring to FIG. 12, an insulating ring 361 is formed in the circular recess 114 to surround the interconnecting metal 35. In this embodiment, the material of the central insulating material 36 is a polymer which is the same as the material of the insulating ring 361. In this embodiment, the insulating ring 361 does not extend into the first dielectric layer 12; therefore, the bottom surface of the interconnect metal 35 is not coplanar with the bottom surface of the insulating ring 361.

Referring to FIG. 13, a second dielectric layer 40 is formed on the inactive surface 112 of the substrate 11. And the second dielectric layer 40 has a plurality of openings 401 to expose the interconnect metal 35. In this embodiment, the second dielectric layer 40 comprises a polymer such as polyimine (PI) or polypropylene (PP). However, in other embodiments, the material of the second dielectric layer 40 may be tantalum oxide or tantalum nitride. Next, a third seed layer 42 is formed on the second dielectric layer 40 and the opening 401 thereof to contact the interconnect metals 35 in the openings 401. The material of the third seed layer 42 is tantalum nitride or tantalum tungsten.

Referring to FIG. 14, a photoresist layer 44 is formed on the third seed layer 42, and the photoresist layer 44 has a plurality of openings 441 to expose portions of the third seed layer 42. Next, a third metal layer 46 is formed in the opening 441 of the photoresist layer 44. The material of the third metal layer 46 is copper.

Referring to Figure 15, the photoresist layer 44 is removed. Next, the third seed layer 42 not covered by the third metal layer 46 is removed to form a redistribution layer 48. However, the third seed layer 42 may be omitted, that is, the third metal layer 46 at this location is the redistribution layer 48.

Referring to FIG. 16, a second protective layer 50 is formed on the second dielectric layer 40 and the redistribution layer 48, and the second protective layer 50 has a plurality of openings 501 to expose portions of the redistribution layer 48. The material of the second protective layer 50 may be the same as the material of the second dielectric layer 40. Next, a surface treatment layer 52 is partially plated on the exposed portion of the redistribution layer 48.

Referring to FIG. 17, a die 2 is attached adjacent to the inactive face 112 of the substrate 11, and the die 2 is electrically connected to the under bump metallurgy (UBM) 24. In this embodiment, the die 2 has an active surface 202, an inactive surface 203, a plurality of pads 204, and at least one second integrated passive device (IPD) 29. The pads 204 and the second integrated passive device (IPD) 29 are adjacent to the active surface 202 of the die 2 . In this embodiment, the second integrated passive device (IPD) 29 is an inductor, however, the second integrated passive device (IPD) 29 can be a capacitor, a resistor, or an inductor, a capacitor, and a resistor. combination. The inactive surface 203 of the die 2 is adhered to the second protective layer 50. The pads 204 are electrically connected to the surface treatment layer 52 on the exposed portions of the redistribution layer 48 via the bonding wires 21 . also That is, the bonding wires 21 connect the die 2 and the redistribution layer 48. In this embodiment, the bonding type of the bonding wires 21 is a reverse bonding. The first step of the reverse bonding is to form a spherical portion 211 on the pads 204 of the die 2. Next, another spherical portion is formed on the tip end of the wire 21 and bonded to the surface conditioning portion 52. Finally, the wire 21 is cut after the wire 21 is pulled to contact the spherical portion 211.

In this embodiment, the die 2 and the bonding wires 21 are disposed adjacent to the inactive surface 112 of the substrate 11 , thereby preventing the circuit layer 13 on the active surface 111 of the substrate 11 from being in a wire bonding process and crystal. Damaged during the grain attachment process. It is known to press the wire to the bond pad and apply ultrasonic friction to complete the wire bond. However, the thickness of the second pads 14b is smaller than the thickness of the redistribution layer 48 or the surface treatment layer 52, so that if the second bonding pads 14b of the active surface 111 of the substrate 11 are to be subjected to a wire bonding process, the The second pad 14b will be susceptible to damage. Next, the encapsulant 3 is formed adjacent to the inactive surface 112 of the substrate 11 to cover the die 2 and the bonding wires 21 . In this embodiment, the encapsulant 3 is located on the second protective layer 50.

Referring to Figure 18, the carrier 26 and the bonding layer 28 are removed.

Referring to FIG. 19, a plurality of solder balls 54 are formed on the under bump metal layer (UBM) 24. Next, the wafer 10 is diced to form a plurality of semiconductor devices 1 as shown in FIG.

As is well known, Bonding and De-bonding are high-risk processes for thin wafers. Therefore, if a thin wafer undergoes a repetitive bonding and de-bonding process, the probability of cracking or breaking is relatively high. In this embodiment, only one carrier 26 is used in the process, and the wafer 10 is bonded to the carrier 26 and the wafer 10 is debonded from the carrier 26 only once to prevent the wafer 10 from cracking or fracture. That is, this embodiment has only one de-bonding step, and the encapsulant 3 has been formed on the wafer 10 before the de-bonding step, and therefore, the wafer 10 is strengthened and not easy during the de-bonding step. Damaged. Therefore, the yield is greatly improved. In addition, the semiconductor process of this embodiment is simplified to reduce manufacturing costs.

Referring to Figures 20 through 23, a semiconductor process for fabricating a semiconductor device in accordance with another embodiment of the present invention is shown. The initial steps of the semiconductor process of this embodiment are the same as those of Figures 1 through 7.

Referring to FIG. 20, a photoresist layer 56 is formed on the inactive surface 112 of the substrate 11, and the photoresist layer 56 has a plurality of ring openings 561 for exposure by an etching process such as wet etching or dry etching. The inactive surface 112 of the substrate 11. Then, a plurality of circular grooves 114 are formed from the inactive surface 112 of the substrate 11 according to the ring openings 561, wherein each of the circular grooves 114 surrounds a central portion 116, and the central portion 116 is the substrate Part of 11. In this embodiment, the circular groove 114 extends only through the substrate 11 to form a plurality of through holes 115.

Referring to Figure 21, an insulating ring 361 is formed in the circular recesses 114 to surround the central portion 116.

Referring to Figure 22, the central portion 116 is removed to form a plurality of cylindrical cavities 113. The cylindrical cavity 113 penetrates the substrate 11 and the first dielectric layer 12 such that the first dielectric layer 12 has a plurality of openings 121. That is, each of the openings 121 is part of each of the cylindrical cavities 113 and extends through the first dielectric layer 12. It should be noted that the positions of the cylindrical cavities 113 must correspond to the positions of the first pads 14a such that the first pads 14a are exposed by the cylindrical cavities 113.

Referring to FIG. 23, a plurality of interconnecting metals 35 are formed in the cylindrical cavities 113 to electrically connect the circuit layers 13. In this embodiment, a second seed layer 32 is formed in the cylindrical cavities 113, and the second seed layer 32 contacts the first pads 14a. Next, a second metal layer 34 is formed on the second seed layer 32. The material of the second seed layer 32 is tantalum nitride or tantalum tungsten, and the material of the second metal layer 34 is copper. The second seed layer 32 and the second metal layer 34 form the interconnect metal 35. However, the second seed layer 32 may be omitted, that is, the second metal layer 34 at this location is the interconnect metal 35. In this embodiment, the interconnect metal 35 defines an inner portion 351. Next, fill the inner portion 351 with one The central insulating material 36 is as shown in FIG. In other embodiments, the second metal layer 34 of FIG. 23 can fill the cylindrical cavity 113, that is, the interconnect metal 35 can be a solid cylinder, and the central insulating material 36 can be omitted. The subsequent steps of this embodiment are identical to the steps of Figures 12-19.

The present invention has been described and illustrated with reference to the particular embodiments of the invention. It will be understood by those skilled in the art that various changes and equivalents can be made without departing from the true spirit and scope of the invention as defined by the appended claims. The descriptions may not necessarily be drawn to scale. Due to the manufacturing process and tolerances, there may be differences between the artistic presentation of the present invention and the actual equipment. There may be other embodiments of the invention that are not specifically illustrated. The description and drawings are to be regarded as illustrative rather Modifications may be made to adapt a particular situation, material, material composition, method or process to the objectives, spirit and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to the specific operations performed in a particular order, it is understood that the operations can be combined, sub-divided or re-ordered to form equivalents without departing from the teachings of the present invention. method. Therefore, the order and grouping of such operations are not a limitation of the invention unless otherwise indicated.

1‧‧‧Semiconductor device

2‧‧‧ grain

3‧‧‧ Sealant

11‧‧‧Substrate

12‧‧‧First dielectric layer

13‧‧‧ circuit layer

14a‧‧‧First mat

14b‧‧‧second mat

15‧‧‧First Integrated Passive Device (IPD)

16‧‧‧First protective layer

18‧‧‧First seed layer

21‧‧‧welding line

22‧‧‧First metal layer

24‧‧‧Under Bump Metal Layer (UBM)

29‧‧‧Second Integrated Passive Device (IPD)

32‧‧‧Second seed layer

34‧‧‧Second metal layer

35‧‧‧Interconnect metal

36‧‧‧Center insulation

40‧‧‧Second dielectric layer

42‧‧‧ third seed layer

46‧‧‧ Third metal layer

48‧‧‧ redistribution layer

50‧‧‧Second protective layer

52‧‧‧Surface treatment layer

54‧‧‧ solder balls

111‧‧‧Active surface

112‧‧‧Inactive surface

115‧‧‧through hole

121‧‧‧ openings

161‧‧‧ openings

202‧‧‧Active surface

203‧‧‧Inactive surface

204‧‧‧ pads

211‧‧‧ first spherical

351‧‧‧ internal part

361‧‧‧Insulation ring

401‧‧‧ openings

501‧‧‧ openings

Claims (20)

A semiconductor device comprising: a substrate; a conductive via formed in the substrate, the conductive via having a first end substantially coplanar with an inactive surface of the substrate a circuit layer disposed adjacent to an active surface of the substrate and electrically connected to a second end of the conductive channel; a redistribution layer adjacent to The non-active surface of the substrate, the redistribution layer has a first portion and a second portion, the first portion is located on the first end and is electrically connected to the first end, and the second portion is positioned upward and away from the first portion a portion; and a die disposed adjacent to the inactive surface of the substrate and electrically connected to the second portion of the redistribution layer. The semiconductor device of claim 1, further comprising a dielectric layer between the inactive surface of the substrate and the second portion of the redistribution layer. The semiconductor device of claim 1, further comprising a protective layer covering the redistribution layer and the dielectric layer, the protective layer having an opening to expose a portion of the redistribution layer. The semiconductor device of claim 3, wherein the openings facilitate the electrical connection between the die and the redistribution layer. The semiconductor device of claim 1, further comprising a plurality of bonding wires electrically connected to the die and the redistribution layer. The semiconductor device of claim 1, further comprising a plurality of sub-bump metal layers (UBMs) adjacent to the active surface of the substrate and electrically Connected to the circuit layer. The semiconductor device of claim 1, wherein the circuit layer and the die each further comprise at least one integrated passive device. The semiconductor device of claim 1, wherein the conductive via comprises a first metal layer, the first metal layer comprising an annular portion and a base portion adjacent to the annular portion, the annular portion being vertically disposed, and the substrate The portion is adjacent to and substantially parallel to the active surface. The semiconductor device of claim 8, wherein the conductive via further comprises a second metal layer on the inner surface of the first metal. A semiconductor device comprising: a substrate; a conductive channel formed in the substrate, a first end of the conductive channel protruding from an inactive surface of the substrate; a circuit layer adjacent to the substrate An active surface is electrically connected to the second end of the conductive channel; a redistribution layer is disposed adjacent to the inactive surface of the substrate, the redistribution layer has a first portion and a second portion, the first portion Located on the first end and electrically connected to the first end, the second portion is positioned upward and away from the first portion; and a die adjacent to the inactive surface of the substrate and electrically connected to the re The second part of the distribution layer. The semiconductor device of claim 10, further comprising a dielectric layer between the inactive surface of the substrate and the second portion of the redistribution layer. The semiconductor device of claim 11, wherein the redistribution layer is located around a lateral surface of the first end of the conductive via. The semiconductor device of claim 10, further comprising a protective layer covering the protective layer The redistribution layer and the dielectric layer are covered, the protective layer having an opening to expose portions of the redistribution layer. The semiconductor device of claim 10, wherein the conductive via comprises a first metal layer, the first metal layer comprising an annular portion and a base portion adjacent to the annular portion, the annular portion being vertically disposed, and the substrate The portion is adjacent to and substantially parallel to the active surface. The semiconductor device of claim 14, wherein the conductive via further comprises a second metal layer on the inner surface of the first metal. The semiconductor device of claim 10, further comprising a plurality of sub-bump metal layers (UBMs) disposed adjacent to the active surface of the substrate and electrically connected to the circuit layer. A method of fabricating a semiconductor device, comprising: (a) providing a wafer having a substrate and a circuit layer, wherein the substrate has an active surface and an inactive surface, and the circuit layer is adjacent And (b) forming a plurality of under bump metallization layers (UBM) on the circuit layer; (c) attaching a carrier to the wafer, wherein the under bump metallurgy (UBM) plane And (d) forming a redistribution layer on the inactive surface; (e) attaching a die adjacent to the inactive surface, wherein the die is electrically connected to the redistribution layer; and (f) forming A gel is adjacent to the inactive surface to coat the die. The method of claim 17, wherein in the step (a), the circuit layer comprises a plurality of first pads (Pads), a plurality of second pads, a first protective layer and a first dielectric layer; The first dielectric layer is located on the active surface of the substrate; the first pads and the second pads are located on the first dielectric layer; the first protective layer covers the first pads and has a plurality of openings to expose the second pads; and in step (b) The under bump metallization (UBM) is formed in the openings of the first protective layer to contact the second pads. The method of claim 17, wherein the step (c) further comprises the steps of: (c1) forming a plurality of interconnecting metals in the substrate to electrically connect the circuit layer; and (c2) forming a redistribution layer adjacent to And the non-active surface, wherein the redistribution layer is electrically connected to the interconnect metal. The method of claim 19, wherein the step (c1) comprises the steps of: (c11) forming a plurality of cylindrical cavities from the inactive surface of the substrate, wherein the cylindrical cavities expose a portion of the circuit layer; (c12) forming the interconnecting metals in the cylindrical cavities; (c13) forming a plurality of circular recesses from the inactive surface of the substrate, wherein each of the circular recesses surrounds each of the plurality of circular recesses Interconnecting metal; and (c14) forming an insulating ring in each of the circular grooves.