TWI425763B - Operational amplifier system capable of automatically cancelling an offset and method capable of automatically cancelling an offset - Google Patents

Description

An operational amplifier system that automatically eliminates offset and a method for automatically eliminating offset

The invention relates to an operational amplifier system and a method thereof for automatically eliminating offset, in particular to a controller for controlling the opening and closing of a plurality of switches, so that the operational amplifier system can be automatically eliminated at any time to eliminate the offset mode. Offset op amp systems and methods therefor.

Referring to Figure 1, there is shown a prior art diagram of an operational amplifier system 100 that eliminates offset. The operational amplifier system 100 includes an operational amplifier 102, a comparator 104, a controller 106, a cancellation offset circuit 108, and switches 110, 112. As shown in FIG. 1, when the operational amplifier system 100 is in an offset cancellation mode, the switches 110, 112 are turned on, and the first input terminal INP and the second input terminal INN of the operational amplifier system 100 respectively input different voltages (VP). , VN). The comparator 104 is configured to compare the voltages (VOUTP, VOUTN) outputted by the first output terminal OUTP and the second output terminal OUTN of the operational amplifier 102, and accordingly generate a comparison result CR. The controller 106 outputs an m-bit control signal CS to the cancellation offset circuit 108 based on the comparison result CR. The cancellation offset circuit 108 generates an m-bit cancellation offset signal OCS to the operational amplifier 102 based on the control signal CS to cancel the offset of the operational amplifier 102. Thus, when the comparison result CR of the comparator 104 changes (from 1 to 0 or from 0 to 1), the cancellation offset circuit 108 locks the cancellation offset signal OCS. The offset circuit 108 can eliminate the offset of the operational amplifier 102 according to the offset signal OCS.

As shown in FIG. 1, when the operational amplifier system 100 is in the offset cancel mode, different voltages VP, VN must be input to the first input terminal INP and the second input terminal INN of the operational amplifier system 100, respectively. And each time the operational amplifier system 100 performs the offset cancellation mode, the m-bit control signal CS output by the controller 106 is increased by the minimum cancellation offset value 00...0 or by the maximum elimination offset value 11... 1 begins to decrease until the comparison result CR of the comparator 104 changes. However, since the operational amplifier 102 takes time to react to the offset voltage, more time is required for dynamic correction.

An embodiment of the present invention provides an operational amplifier system that automatically cancels offset. The operational amplifier system includes a controller, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an operational amplifier, a digital control circuit, and a cancellation offset circuit. The controller is configured to generate a control signal when the operational amplifier system is in an offset mode; the first switch has a first end coupled to the first input end of the operational amplifier system, and a second The second switch has a first end coupled to the second input end of the operational amplifier system, and a second end for receiving the control signal, And a third end; the third switch has a first end coupled to the third end of the first switch, a second end for receiving the control signal, and a third end coupled to the a third end of the second switch; the fourth switch has a first end, a second end for receiving the control signal, and a third end; the fifth switch has a first end coupled to the a first end of the fourth switch, a second end for receiving the control signal, and a third end coupled to the output end of the operational amplifier system; the operational amplifier having a first input coupled to a third end of the first switch, a second input end coupled to the second switch a third end, and an output end coupled to the first end of the fourth switch; the digital control circuit has an input end coupled to the third end of the fourth switch, and an output end for The signal output by the operational amplifier outputs an N-bit control signal, where N ≧ 1; the cancellation offset circuit is coupled between the digital control circuit and the operational amplifier for controlling the signal according to the N-bit a look-up table that cancels an offset inside the operational amplifier; wherein when the operational amplifier system is in the cancel offset mode, the first switch, the third switch, and the fourth switch are turned on according to the control signal, and the first The second switch and the fifth switch are turned off according to the control signal; when the operational amplifier system is in a normal operation mode, the first switch, the second switch, and the fifth switch are turned on, and the third switch and the fourth switch The switch is off.

Another embodiment of the present invention provides a method of automatically eliminating offset. The method includes: when an operational amplifier system is in an offset cancellation mode, a controller generates a control signal; a first switch, a third switch, and a fourth switch are turned on according to the control signal, and a second switch and a fifth switch is turned off according to the control signal; a constant current is input to a first input end of the operational amplifier; the operational amplifier generates a logic potential according to the DC voltage and an offset inside the operational amplifier; a digital control circuit is The logic potential performs a corresponding action.

The present invention provides an operational amplifier system and method thereof that automatically eliminates offset. The operational amplifier system and method utilizes a controller to control the opening and closing of a first switch, a second switch, a third switch, a fourth switch, and a fifth switch. Therefore, compared with the prior art, the present invention has the following advantages: First, when the operational amplifier system is in an offset cancellation mode, the present invention only needs to input a DC voltage; second, an operational amplifier of the present invention can be used as a comparator, thereby saving the area of the amplifier system; third, the operational amplifier system can enter the cancellation offset mode upon startup, or the operational amplifier system can operate according to a pulse width modulation signal After a period of time, the operational amplifier system enters the cancellation offset mode when the pulse width modulation signal is at a logic low level, that is, the operational amplifier system can enter the cancellation offset at any time according to a user's needs. mode.

Please refer to FIG. 2. FIG. 2 is a schematic diagram showing an operational amplifier system 200 capable of automatically eliminating offset according to an embodiment of the present invention. The operational amplifier system 200 includes a controller 202, a first switch 204, a second switch 206, a third switch 208, a fourth switch 210, a fifth switch 212, an operational amplifier 214, and a digital control circuit 216. And an offset circuit 218. The controller 202 is configured to generate a control signal CS when the operational amplifier system 200 is in an offset cancellation mode. The first switch 204 has a first end coupled to the first input terminal INP of the operational amplifier system 200. The second end is configured to receive the control signal CS and the third end. The second switch 206 has a first end coupled to the second input end INN of the operational amplifier system 200, and a second end for receiving control The third switch 208 has a first end coupled to the third end of the first switch 204, and a second end for receiving the control signal CS and a third end coupled Connected to the third end of the second switch 206; the fourth switch 210 has a first end, a second end for receiving the control signal CS, and a third end; the fifth switch 212 has a first end, coupled Connected to the first end of the fourth switch 210, a second end for receiving the control signal CS, and a third end coupled to the output terminal OUT of the operational amplifier system 200, wherein the operational amplifier system 200 is used to eliminate the bias In the shift mode, the first switch 204, the third switch 208, and the fourth switch 210 are controlled according to The second switch 206 and the fifth switch 212 are turned off according to the control signal CS, or when the operational amplifier system 200 is in the cancel offset mode, the second switch 206, the third switch 208, and the fourth switch 210 are controlled according to the control signal. The CS is turned on, and the first switch 204 and the fifth switch 212 are turned off according to the control signal CS. When the operational amplifier system 200 is in a normal operation mode, the first switch 204, the second switch 206, and the fifth switch 212 are turned on, and the third switch 208 and the fourth switch 210 are turned off. In addition, the first switch 204, the third switch 208, and the fourth switch 210 may be P-type MOS transistors, and the second switch 206 and the fifth switch 212 are N-type MOS transistors; the first switch 204, the third switch 208 and the fourth switch 210 can be N-type MOS transistors, and the second switch 206 and the fifth switch 212 can be P-type MOS transistors; the first switch 204, the second The switch 206, the third switch 208, the fourth switch 210, and the fifth switch 212 can be transmission gates. The operational amplifier 214 has a first input end coupled to the third end of the first switch 204, a second input end coupled to the third end of the second switch 206, and an output end coupled to the fourth a first end of the switch 210; the digital control circuit 216 has an input coupled to the third end of the fourth switch 210, and an output for outputting an N-bit control signal according to the signal output by the operational amplifier 214 The N ≧ 1; the cancellation offset circuit 218 is coupled between the digital control circuit 216 and the operational amplifier 214 for removing the offset inside the operational amplifier 214 according to the N-bit control signal and a look-up table.

As shown in FIG. 2, the digital control circuit 216 includes a first latch 2162, an adder 2164, a subtractor 2166, and a second latch 2168. The first latch 2162 has an input end and an output end. The adder 2164 has a first input end coupled to the output of the operational amplifier 214 for receiving the signal output by the operational amplifier 214, and a second input. The terminal is coupled to the output end of the first latch 2162 for receiving the temporary storage value RV stored by the first latch 2162, and an output terminal, wherein the signal output from the operational amplifier 214 is a logic low When "0", the adder 2164 outputs a first corrected offset value FCOS according to the logic low potential "0" and the temporary storage value RV stored by the first latch 2162; the subtractor 2166 has a first input end, coupled An output terminal of the operational amplifier 214 is configured to receive the signal outputted by the operational amplifier 214, and a second input terminal is coupled to the output end of the first latching device 2162 for receiving the temporary storage of the first latching device 2162. The stored value RV, and an output terminal, wherein when the signal output by the operational amplifier 214 is a logic high potential "1", the subtractor 2166 stores the temporary storage value according to the logic high potential "1" and the first latch 2162. RV, outputting a second corrected offset value SCOS; second The shackle 2168 has an input coupled to the adder 2164 and the subtractor 2166 for receiving and storing the first corrected offset value FCOS and the second corrected offset value SCOS, and an output coupled to the The offset circuit 218 and the input end of the first latch 2162 are configured to output a first corrected offset value FCOS and a second corrected offset value SCOS to the cancel offset circuit 218 and the first latch 2162; The corrected offset value FCOS and the second corrected offset value SCOS are N-bit control signals, and the first latch 2162 updates the first frame according to the first corrected offset value FCOS and the second corrected offset value SCOS. The temporary value RV stored by the lock 2162.

Please refer to FIG. 3, which is a schematic diagram illustrating the cancellation offset circuit 218. As shown in FIG. 3, the cancellation offset circuit 218 includes a first cancellation offset circuit 2182 and a second cancellation offset circuit 2184. The first cancellation offset circuit 2182 includes first current sources 21822, 21824, 21826 and sixth switches 21842, 21844, 21846. The first current source 21822 has a first end for receiving a first voltage V1 and a second end. The first current source 21824 has a first end for receiving the first voltage V1 and a second end. The first current source 21826 has a first end for receiving the first voltage V1, and a second end, wherein the current flowing through the first current source 21822 is I, and the current flowing through the first current source 21824 2I, and the current flowing through the first current source 21826 is 4I. However, the present invention is not limited to the current flowing through the first current source 21822 being I, the current flowing through the first current source 21824 being 2I, and the current flowing through the first current source 21826 being 4I. The sixth switch 21842 has a first end coupled to the second end of the first current source 21822, and a second end for receiving a first control signal FCS generated according to the N-bit control signal and the look-up table. And a third end coupled to the operational amplifier 214; the sixth switch 21844 has a first end coupled to the second end of the first current source 21824, and a second end for receiving the control signal according to the N bit The first control signal FCS generated by the lookup table and the third terminal are coupled to the operational amplifier 214. The sixth switch 21846 has a first end coupled to the second end of the first current source 21826. The second end is configured to receive the first control signal FCS generated according to the N-bit control signal and the look-up table, and a third end coupled to the operational amplifier 214.

As shown in FIG. 3, the second cancellation offset circuit 2184 includes second current sources 21841, 21843, 21845 and seventh switches 21862, 21864, 21866. The second current source 21841 has a first end for receiving the first voltage V1, and a second end; the second current source 21843 has a first end for receiving the first voltage V1, and a second end; The second current source 21845 has a first end for receiving the first voltage V1 and a second end, wherein the current flowing through the second current source 21841 is I, and the current flowing through the second current source 21843 is 2I, and the current flowing through the second current source 21845 is 4I. However, the present invention is not limited to the current flowing through the second current source 21841 being I, the current flowing through the second current source 21843 being 2I, and the current flowing through the second current source 21845 being 4I. The seventh switch 21862 has a first end coupled to the second end of the second current source 21841, and a second end for receiving a second control signal SCS generated according to the N-bit control signal and the look-up table. And a third end coupled to the operational amplifier 214; the seventh switch 21864 has a first end coupled to the second end of the second current source 21843, and a second end for receiving the control signal according to the N bit The second control signal SCS generated by the lookup table and the third terminal are coupled to the operational amplifier 214. The seventh switch 21866 has a first end coupled to the second end of the second current source 21845. The second end is configured to receive the second control signal SCS generated by the N-bit control signal and the look-up table, and a third end coupled to the operational amplifier 214.

Please refer to FIG. 4A and FIG. 4B. FIG. 4A is a schematic diagram illustrating the operation of the operational amplifier system 200 in a normal operation mode, and FIG. 4B is a schematic diagram illustrating the operation of the operational amplifier system 200 in the offset cancellation mode. As shown in FIG. 4A, when the operational amplifier system 200 operates in the normal operation mode, the first switch 204, the second switch 206, and the fifth switch 212 are turned on, and the third switch 208 and the fourth switch 210 are turned off. Therefore, the first input terminal INP and the second input terminal INN of the operational amplifier system 200 receive the signals VP and VN, respectively, and the output terminal OUT of the operational amplifier system 200 outputs the signal VOUT.

As shown in FIG. 4B, when the operational amplifier system 200 operates in the cancel offset mode, the first switch 204, the third switch 208, and the fourth switch 210 are turned on according to the control signal CS, and the second switch 206 and the fifth switch 212. According to the control signal CS is turned off. The first input INP of the operational amplifier system 200 receives the DC voltage V2. In addition, if the second switch 206 is turned on according to the control signal CS, and the first switch 204 is turned off according to the control signal CS, the DC voltage V2 is received by the second input terminal INN of the operational amplifier system 200. Because the third switch 208 is turned on, the first input terminal and the second input terminal of the operational amplifier 214 receive the DC voltage V2 at the same time, and the operational amplifier 214 generates a logic according to the offset of the DC voltage V2 and the internal of the operational amplifier 214. The potential (logic high potential "1" or logic low potential "0"), that is, the operational amplifier 214 is now used as a comparator. When the operational amplifier 214 generates a logic low potential "0" according to the DC voltage V2 and the internal offset of the operational amplifier 214, the adder 2164 in the digital control circuit 216 is based on the logic low potential "0" and the number in the digital control circuit 216. The temporary storage value RV stored by the shackle 2162 outputs a first corrected offset value FCOS, that is, the adder 2164 adds one of the temporary storage values RV stored by the first shackle 2162 to generate and output a first correction. Offset value FCOS. When the operational amplifier 214 generates a logic high potential "1" according to the DC voltage V2 and the offset inside the operational amplifier 214, the subtractor 2166 in the digital control circuit 216 is based on the logic high potential "1" and the number in the digital control circuit 216. The temporary storage value RV stored by the shackle 2162 outputs a second corrected offset value SCOS, that is, the subtractor 2166 subtracts the temporary storage value RV stored by the first shackle 2162 by one to generate and output a second correction. Offset value SCOS.

As shown in FIG. 4B, the second latch 2168 receives and stores the first corrected offset value FCOS and the second corrected offset value SCOS, and outputs the first corrected offset value FCOS and the second corrected offset value SCOS to The first latch 2162 and the cancel offset circuit 218; the cancel offset circuit 218 removes the offset inside the operational amplifier 214 according to the first corrected offset value FCOS, the second corrected offset value SCOS, and the lookup table; The locker 2162 updates the temporary storage value RV stored by the first latch 2162 according to the first corrected offset value FCOS and the second corrected offset value SCOS. Additionally, as soon as the operational amplifier system 200 is powered up, the operational amplifier system 200 can enter an offset cancellation mode. At this time, the temporary storage value RV stored by the first latch 2162 is the minimum value 00...00 or the maximum value 11...11 of the N-bit control signal.

Referring to FIG. 4C, FIG. 4C is a diagram showing that the operational amplifier system 200 starts to operate after a period of time according to a pulse width modulation signal PWM, and the operational amplifier system 200 enters the elimination when the pulse width modulation signal PWM is logic low. Schematic diagram of the offset mode. As shown in FIG. 4C, when the pulse width modulation signal PWM is at a logic low level, the controller 202 generates a control signal CS. The operational amplifier system 200 can perform the cancellation of the offset inside the operational amplifier 214 while the control signal CS is at a logic high level. At this time, the temporary storage value RV stored by the first shackle 2162 is the temporary storage value stored last time.

Please refer to FIG. 2, FIG. 3, FIG. 4D and FIG. 4E. FIG. 4D is a schematic diagram of a look-up table 400 illustrating the relationship between the 4-bit control signal, the first control signal FCS and the second control signal SCS. And FIG. 4E is a schematic diagram illustrating the elimination of the offset inside the operational amplifier 214. As shown in FIG. 4D, the 4-bit control signal has 16 sets of control signals, wherein each set of control signals corresponds to a first control signal FCS and a second control signal SCS. As shown in FIG. 4E, for example, the temporary storage value RV stored in the first latch 2162 is 0000, and the offset inside the operational amplifier 214 is a negative value, the operational amplifier 214 is based on the DC voltage V2 and the internal of the operational amplifier 214. The offset produces a logic low "0". Then, the adder 2164 increments the temporary value RV(0000) stored by the first latch 2162 to generate and output a first corrected offset value FCOS(0001). After a period T of one clock CLK, the cancellation offset circuit 218 changes the first cancellation offset circuit 2182 and the second cancellation offset circuit 2184 to the operational amplifier 214 according to the first correction offset value FCOS(0001) and the look-up table 400. The current is adjusted to adjust the offset inside the operational amplifier 214. That is, when the first correction offset value FCOS is 0001, the second control signal SCS is 000 and the first control signal FCS is 111. Therefore, the current flowing into the operational amplifier 214 by the first cancellation offset circuit 2182 is 7I, and the current flowing into the operational amplifier 214 by the second cancellation offset circuit 2184 is zero. If the operational amplifier 214 is still based on the DC voltage V2 and the offset inside the operational amplifier 214, a logic low potential "0" is still generated. The adder 2164 then increments the temporary value RV(0001) stored by the first latch 2162 to generate and output a first corrected offset value FCOS (0010). After the period T of the clock CLK, the cancellation offset circuit 218 changes the first cancellation offset circuit 2182 and the second cancellation offset circuit 2184 to the operational amplifier 214 according to the first correction offset value FCOS (0010) and the look-up table 400. The current is adjusted to adjust the offset inside the operational amplifier 214. Thus, until the operational amplifier 214 generates a logic high potential "1" based on the DC voltage V2 and the offset inside the operational amplifier 214. At this time, as shown in FIG. 4E, the first correction offset value FCOS is 0100, and the subtractor 2166 subtracts the temporary storage value RV (0100) stored by the first latch 2162 according to the logic high potential "1". First, to generate and output a second corrected offset value SCOS (0100). Then, the temporary storage value RV (4-bit control signal NCS) stored by the first latch 2162 continues to jump between 0100 and 0011, that is, the operational amplifier system 200 completes the elimination of the offset inside the operational amplifier 214. However, Fig. 4E is only for explaining the present invention, that is, the present invention is not limited to the example of Fig. 4E.

Please refer to FIG. 5. FIG. 5 is a schematic diagram showing an operational amplifier system 500 capable of automatically eliminating offset according to another embodiment of the present invention. The difference between operational amplifier system 500 and operational amplifier system 200 is that operational amplifier system 500 further includes a D-type flip-flop 2170. The D-type flip-flop 2170 is coupled between the digital control circuit 216 and the operational amplifier 214 for quickly causing the signal output from the operational amplifier 214 to reach a logic high potential "1" and a logic low potential "0". In addition, the remaining operating principles of the operational amplifier system 500 are the same as those of the operational amplifier system 200, and are not described herein again.

Please refer to FIG. 6. FIG. 6 is a flow chart showing a method for automatically eliminating offset according to another embodiment of the present invention. The method of FIG. 6 is illustrated by the operational amplifier system 200 of FIG. 2. The detailed steps are as follows: Step 600: Start; Step 602: When the operational amplifier system 200 is in the offset cancellation mode, the controller 202 generates the control signal CS; 604: The first switch 204, the third switch 208, and the fourth switch 210 are turned on according to the control signal CS, and the second switch 206 and the fifth switch 212 are turned off according to the control signal CS. Step 606: input the DC voltage V2 to the operational amplifier system 200. The first input terminal INP; step 608: the operational amplifier 214 generates a logic potential according to the DC voltage V2 and the offset inside the operational amplifier 214; if the operational amplifier 214 generates a logic high potential "1", proceed to step 610; The amplifier 214 generates a logic low potential "0" and proceeds to step 618. Step 610: The subtractor 2166 in the digital control circuit 216 stores the temporary storage according to the logic high potential "1" and the first latch 2162 in the digital control circuit 216. Store the value RV, output a second corrected offset value SCOS; step 612: the second latch 2168 receives and stores the second corrected offset value SCOS, and outputs the second Correcting the offset value SCOS to the first latch 2162 and the cancellation offset circuit 218; Step 614: Eliminating the offset circuit 218 to cancel the offset inside the operational amplifier 214 according to the second corrected offset value SCOS and the look-up table 400; 616: The first latch 2162 updates the temporary storage value RV stored by the first latch 2162 according to the second corrected offset value SCOS, and jumps back to step 608; Step 618: The adder 2164 in the digital control circuit 216 is based on the logic. The low potential "0" and the temporary storage value RV stored by the first latch 2162 in the digital control circuit 216 output the first corrected offset value FCOS; Step 620: The second latch 2168 receives and stores the first correction offset Shifting the FCOS, and outputting the first corrected offset value FCOS to the first latcher 2162 and the canceling offset circuit 218; Step 622: The canceling offset circuit 218 cancels the operation according to the first corrected offset value FCOS and the lookup table 400 The offset inside the amplifier 214; step 624: the first latch 2162 updates the temporary value RV stored by the first latch 2162 according to the first corrected offset value FCOS, and jumps back to step 608; in step 606, because The third switch 208 is turned on, so the operational amplifier 2 The first input terminal and the second input terminal 14 receive the DC voltage V2 at the same time. In step 608, the operational amplifier 214 generates a logic potential (logic high potential "1" or logic low potential "0") according to the offset of the DC voltage V2 and the operational amplifier 214, that is, the operational amplifier 214 is configured at this time. For a comparator. In step 610, the subtractor 2166 subtracts the temporary value RV stored by the first latch 2162 by one to generate and output a second corrected offset value SCOS. In step 614, the cancellation offset circuit 218 changes the current flowing into the operational amplifier 214 by the first cancellation offset circuit 2182 and the second cancellation offset circuit 2184 according to the second correction offset value SCOS and the look-up table 400 to adjust the operational amplifier. 214 internal offset. In step 618, the adder 2164 increments the temporary value RV stored by the first latch 2162 to generate and output a first corrected offset value FCOS. In step 622, the cancellation offset circuit 218 changes the current flowing into the operational amplifier 214 by the first cancellation offset circuit 2182 and the second cancellation offset circuit 2184 according to the first correction offset value FCOS and the look-up table 400 to adjust the operational amplifier. 214 internal offset.

In summary, the present invention provides an automatically cancelable offset operational amplifier system and method thereof for controlling the opening, closing, and closing of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch by using a controller. . Therefore, compared with the prior art, the present invention has the following advantages: First, when the operational amplifier system is in the offset mode, the present invention only needs to input a DC voltage; second, the operational amplifier of the present invention can be used as a comparator. Therefore, the area of the operational amplifier system can be saved; third, the operational amplifier system can enter the elimination offset mode when the power is turned on, or the operational amplifier system starts to operate for a period of time according to the pulse width modulation signal, and the operational amplifier system is pulsed. When the width modulation signal is logic low, it enters the elimination offset mode, that is, the operational amplifier system can enter the elimination offset mode at any time according to the needs of a user.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200, 500. . . Operational amplifier system

102, 214. . . Operational Amplifier

104. . . Comparators

106, 202. . . Controller

108, 218. . . Elimination of offset circuit

110, 112. . . switch

204. . . First switch

206. . . Second switch

208. . . Third switch

210. . . Fourth switch

212. . . Fifth switch

216. . . Digital control circuit

400. . . Lookup table

2162. . . First lock

2164. . . Adder

2166. . . Subtractor

2168. . . Second lock

2170. . . D-type flip-flop

2182. . . First cancellation offset circuit

2184. . . Second cancellation offset circuit

21822, 21824, 21826. . . First current source

21842, 21844, 21846. . . Sixth switch

21841, 21843, 21845. . . Second current source

21862, 21864, 21866. . . Seventh switch

"0". . . Logical low potential

"1". . . Logic high potential

CLK. . . Clock

CR. . . Comparing results

CS. . . Control signal

FCOS. . . First correction offset value

FCS. . . First control signal

I, 2I, 4I. . . Current

INN. . . Second input

INP. . . First input

OCS. . . Eliminate offset signals

OUTN. . . Second output

OUTP. . . First output

OUT. . . Output

PWM. . . Pulse width modulation signal

RV. . . Temporary value

SCS. . . Second control signal

SCOS. . . Second correction offset value

T. . . cycle

V1. . . First voltage

V2. . . DC voltage

VP, VN, VOUT. . . Signal

600 to 624. . . step

Figure 1 is a schematic diagram of an operational amplifier system with offset cancellation as described in the prior art.

2 is a schematic diagram of an operational amplifier system capable of automatically eliminating offsets, in accordance with an embodiment of the present invention.

Figure 3 is a schematic diagram illustrating the elimination of the offset circuit.

Figure 4A is a diagram illustrating the operation of the operational amplifier system in a normal mode of operation.

Figure 4B is a diagram illustrating the operation of the operational amplifier system in an offset cancellation mode.

Figure 4C is a schematic diagram showing the operation of the operational amplifier system after the pulse width modulation signal is started for a period of time, and the operational amplifier system enters the cancellation offset mode when the pulse width modulation signal is at a logic low level.

4D is a schematic diagram of a look-up table illustrating the relationship between the 4-bit control signal, the first control signal, and the second control signal.

Fig. 4E is a schematic diagram illustrating the elimination of the offset inside the operational amplifier.

Figure 5 is a schematic diagram of an operational amplifier system capable of automatically eliminating offsets in accordance with another embodiment of the present invention.

Figure 6 is a flow chart illustrating a method of automatically eliminating offsets in accordance with another embodiment of the present invention.

200. . . Operational amplifier system

202. . . Controller

204. . . First switch

206. . . Second switch

208. . . Third switch

210. . . Fourth switch

212. . . Fifth switch

214. . . Operational Amplifier

216. . . Digital control circuit

218. . . Elimination of offset circuit

2162. . . First lock

2164. . . Adder

2166. . . Subtractor

2168. . . Second lock

"0". . . Logical low potential

"1". . . Logic high potential

CS. . . Control signal

FCOS. . . First correction offset value

INN. . . Second input

INP. . . First input

OUT. . . Output

RV. . . Temporary value

SCOS. . . Second correction offset value

Claims (15)

An operational amplifier system capable of automatically eliminating offsets, comprising: a controller for generating a control signal when the operational amplifier system is in an offset cancellation mode; and a first switch having a first end coupled a first end of the operational amplifier system, a second end for receiving the control signal, and a third end; a second switch having a first end coupled to the second of the operational amplifier system An input end, a second end for receiving the control signal, and a third end; a third switch having a first end coupled to the third end of the first switch and a second end Receiving the control signal, and a third end coupled to the third end of the second switch; a fourth switch having a first end and a second end for receiving the control signal, and a first The third switch has a first end coupled to the first end of the fourth switch, a second end for receiving the control signal, and a third end coupled to the operational amplifier An output of the system; an operational amplifier having a first input coupled a third input end of the first switch, a second input end coupled to the third end of the second switch, and an output end coupled to the first end of the fourth switch; a digital control circuit, An input end coupled to the third end of the fourth switch, and an output end for outputting an N-bit control signal according to the signal output by the operational amplifier, wherein N≧1; An offset circuit coupled between the digital control circuit and the operational amplifier for canceling an internal offset of the operational amplifier according to the N-bit control signal and a look-up table; wherein when the operational amplifier system is When the offset mode is eliminated, the first switch, the third switch, and the fourth switch are turned on according to the control signal, and the second switch and the fifth switch are turned off according to the control signal; when the operational amplifier system is in a In the normal operation mode, the first switch, the second switch, and the fifth switch are turned on, and the third switch and the fourth switch are turned off. The operational amplifier system of claim 1, wherein the digital control circuit comprises: a first latch having an input and an output; and an adder having a first input coupled to the An output of the operational amplifier is configured to receive the signal output by the operational amplifier, and a second input end is coupled to the output end of the first latch to receive the temporary storage value stored by the first latch. And an output end, wherein when the signal output by the operational amplifier is a logic low level, the adder outputs a first corrected offset value according to the logic low potential and the temporary storage value stored by the first latch a subtractor having a first input coupled to the output of the operational amplifier for receiving a signal output by the operational amplifier, and a second input coupled to the output of the first latch Receiving a temporary storage value stored by the first latch, and an output end, wherein when the signal output by the operational amplifier is a logic high level, the subtractor is based on the logic high potential and the first Temporary value stored by the locker , outputting a second corrected offset value; and a second latch has an input coupled to the adder and the subtractor for receiving and storing the first corrected offset value and the second corrected offset value, and an output terminal coupled The output of the canceling offset circuit and the first latch is configured to output the first correction offset value and the second correction offset value to the cancellation offset circuit and the first latch; The first correction offset value and the second correction offset value are the N-bit control signals, and the first latch is based on the first correction offset value and the second correction offset value. Update the temporary value stored by the first shackle. The operational amplifier system of claim 2, wherein the adder outputs the first corrected offset value according to the logic low potential and the temporary storage value stored by the first latch, for the adder to The temporary storage value stored by the shackle is incremented by one to generate and output the first corrected offset value. The operational amplifier system of claim 2, wherein the subtractor outputs the second corrected offset value according to the logic high potential and the temporary storage value stored by the first latch, the subtractor The temporary storage value stored by the shackle is decremented by one to generate and output the second corrected offset value. The operational amplifier system of claim 1, further comprising: a D-type flip-flop coupled between the digital control circuit and the operational amplifier to rapidly output a signal of the operational amplifier to a logic high level With a logic low potential. The operational amplifier system of claim 1, wherein the cancellation offset circuit comprises: a first cancellation offset circuit, comprising at least one first cancellation offset unit, wherein each first cancellation offset unit comprises: a first a current source having a first terminal for receiving a first voltage and a second terminal; and a sixth switch having a first end coupled to the second end of the first current source, The second end is configured to receive a first control signal generated according to the N-bit control signal and the look-up table, and a third end coupled to the operational amplifier; and a second cancellation offset circuit, including At least one second cancellation offset unit, wherein each second cancellation offset unit comprises: a second current source having a first end for receiving the first voltage, and a second end; and a seventh The switch has a first end coupled to the second end of the second current source, and a second end for receiving a second control signal generated according to the N-bit control signal and the look-up table, and A third end is coupled to the operational amplifier. The operational amplifier system of claim 1, wherein the first switch, the third switch, and the fourth open relationship are N-type MOS transistors, and the second switch and the fifth open relationship are P-type Gold oxide semi-transistor. The operational amplifier system of claim 1, wherein the first switch, the third switch, and the fourth open relationship are P-type MOS transistors, and the second switch and the fifth open relationship are N-type Gold oxide semi-transistor. The operational amplifier system of claim 1, wherein the first switch, the second switch, the third switch, the fourth switch, and the fifth open relationship are transmission gates. A method for automatically eliminating offset, wherein an operational amplifier system applied to the method includes a controller, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a An operational amplifier, a digital control circuit, and a cancellation offset circuit, wherein the first switch has a first end coupled to the first input end of the operational amplifier system, and the second switch has a first end The second switch is coupled to the second input end of the operational amplifier, the third switch is coupled between the first input end and the second input end of the operational amplifier, and the fourth switch is coupled to the output end of the operational amplifier, The fifth switch is coupled to the fourth switch and the output of the operational amplifier, the digital control circuit is coupled to the fourth switch, and the cancellation offset circuit is coupled between the digital control circuit and the operational amplifier. The method includes: when the operational amplifier system is in an offset cancellation mode, the controller generates a control signal; the first switch, the third switch, and the fourth switch are turned on according to the control signal And the second switch and the fifth switch is turned off according to the control signal; an input DC voltage to the first input terminal of the operational amplifier system; The operational amplifier generates a logic low potential according to the DC voltage and an offset inside the operational amplifier; and the adder in the digital control circuit stores the logic according to the logic low level and the first latch in the digital control circuit The temporary value is output and a first corrected offset value is output. The method of claim 10, wherein the adder in the digital control circuit outputs the first corrected offset value according to the logic low potential and a temporary storage value stored by the first latch in the digital control circuit, The adder adds the temporary value stored by the first latch to one to generate and output the first corrected offset value. The method of claim 10, further comprising: receiving, by the second latch, the first corrected offset value, and outputting the first corrected offset value to the first latch and a canceling offset a circuit; the cancellation offset circuit cancels an offset inside the operational amplifier according to the first correction offset value and a look-up table; and the first latch performs the first update according to the first correction offset value The temporary value stored by the locker. A method for automatically eliminating offset, wherein an operational amplifier system applied to the method includes a controller, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a An operational amplifier, a digital control circuit, and a cancellation offset circuit, wherein the first switch has a first end coupled to the first input end of the operational amplifier system, and the second switch has a first end The second switch is coupled to the second input end of the operational amplifier, the third switch is coupled between the first input end and the second input end of the operational amplifier, and the fourth switch is coupled to the output end of the operational amplifier, The fifth switch is coupled to the fourth switch and the output of the operational amplifier, the digital control circuit is coupled to the fourth switch, and the cancellation offset circuit is coupled between the digital control circuit and the operational amplifier. The method includes: when the operational amplifier system is in an offset cancellation mode, the controller generates a control signal; the first switch, the third switch, and the fourth switch are turned on according to the control signal, and the second switch And the fifth switch is turned off according to the control signal; inputting a DC voltage to the first input end of the operational amplifier system; the operational amplifier generates a logic high potential according to the DC voltage and an offset inside the operational amplifier; The adder in the digital control circuit outputs a second corrected offset value according to the logic high potential and the temporary storage value stored by the first latch in the digital control circuit. The method of claim 13, wherein the subtractor in the digital control circuit outputs the second corrected offset value according to the logic high potential and a temporary storage value stored by the first latch in the digital control circuit, The subtractor stores the temporary storage value stored by the first shackle by one to generate and output the second corrected offset value. The method of claim 13, further comprising: a second shackle receives and stores the second correction offset value, and outputs the second correction offset value to the first shackle and a cancellation offset circuit; the cancellation offset circuit is responsive to the second correction The offset value and a look-up table cancel the offset inside the operational amplifier; and the first latch replaces the temporary storage value stored by the first latch according to the second corrected offset value.