TW201249099A - Operational amplifier system capable of automatically cancelling an offset and method capable of automatically cancelling an offset - Google Patents

Abstract

An operational amplifier system includes a controller, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an operational amplifier, a digital control circuit, and an offset cancellation circuit. When the operational amplifier system is in an offset cancellation mode, the controller generates a control signal. The first switch, the third switch, and the fourth switch are turned on according to the control signal, and the second switch and the fifth switch are turned off according to the control signal. The operational amplifier outputs a signal according to a direct current voltage. The digital control circuit outputs an N-bit control signal according to the signal, where N ≥ 1. The offset cancellation circuit cancels an offset of the operational amplifier according to the N-bit control signal and a lookup table.

Description

201249099 VI. Description of the Invention: [Technical Fields of the Invention] The system and method thereof are related to an operational amplifier system capable of automatically eliminating offset and its side/s type of Lichi controller controlling the opening of a plurality of switches And turn off the operation of the operational amplifier (4) _ can be privately transferred from the (four) divide operation 2 [prior art] μ. Month = according to Figure 1 '! The figure is a schematic diagram of a prior art description of an offset reduction system 100. The operational amplifier system just includes an operational amplifier 02 than the brake 104, a controller 1〇6, a cancellation offset circuit (10), and a switch as shown in Fig. 1 when the operational amplifier system is in the -offset mode. When the switches 110, 112 are turned on, and the first input end of the operational amplifier system and the second input end face respectively input different electric galvanics (VP, VN). The comparator 1〇4 is used to compare the first output terminal 〇υτρ of the operational amplifier 102 with the NMOS VOUTP, V0 output of the second output terminal, and accordingly generate a comparison result cr. The control β 106 controls the can cs to the offset circuit 108 in accordance with her result CR. The canceling offset circuit (10) generates a claw bit erasing offset signal ocs to the operational amplifier 102 based on the control signal cs to cancel the offset of the operational amplifier 1〇2. Thus, when the comparison result CR of the comparator 104 changes (from 】 to 〇 or from 〇 to 1), the cancellation offset circuit (10) locks the offset thief cs. The offset circuit (10) can eliminate the offset of the operational amplifier 1〇2 according to the offset signal 0CS. 201249099 as the first! As shown in the figure, when the op amp system is in the offset mode, different voltages VP and VN must be input to the INP and the second input end of the op amp system. And each time the operational amplifier system (10) performs the cancellation, in the shift mode, the m-bit control signal cs output by the controller 1() 6 is increased by the minimum shift value (do.) or by the maximum elimination offset value U i . The comparison result CR of the direct comparator 1〇4 is changed. However, since the operational amplifier 1 shifts the voltage, it takes time 'therefore, the recording time is required for correction.' [Invention] The present invention provides an automatic An operational amplifier system that eliminates offset. The operational amplifier includes - controller, - - -, - second switch, - third switch, - fourth switch, - fifth switch, - operational amplifier, a digital control ^ a circuit and a cancellation offset circuit. The control (four) generates a control signal when the operational amplifier system eliminates the offset mode; the first switch has a first terminal coupled to the operational amplifier system An input end, a second end, for receiving the control ^ number 'and the third end; the second switch has a - first end 'secret of the operation put = the second input end of the system' - the second End, for receiving the control signal, and An first-end H-switch has a -th terminal, secretly the third end of the first switch, a U-th to receive the control signal, and - a third end, the second switch of the second switch Having a first end, a second end for receiving the control signal and a second end; the fifth switch having a first end coupled to the first end of the fourth switch, the second end For receiving the control signal, and a third end connected to the output of the 201249099 operational amplifier system; the operational amplifier has a - first input terminal, which is lightly connected to the third end of the first switch, - The second input end is formed at the third end 'and the output end of the second switch, and is secreted to the first end of the fourth switch; the digital control circuit has -, the input end, and the third end of the fourth switch And the output terminal is configured to output a signal according to the signal output by the operational amplifier, wherein the offset offset f is between the health circuit and the operational amplifier, and is used according to the N Bit control signal and - check to eliminate the offset of the operational amplifier (10) The first switch, the third switch, and the fourth switch are turned on according to the control signal, and the second switch and the fifth switch are turned off according to the control signal; when the operational amplifier system is in a ^ In the operational mode, the ith switch, the second switch and the fifth switch are turned on, and the third switch and the fourth switch are turned off. A further embodiment of the present invention provides a method for automatically eliminating offset. The method includes when the operational amplifier system is in the -offset offset mode, the controller generates a control subtraction, - the third switch, the third switch and the - fourth switch are turned on according to the control signal, and - the second switch and a fifth switch is turned off according to the control signal; the input current is applied to the -operation amplification terminal; the operational amplifier generates a logic potential according to the DC voltage and the offset of the operation amplification H; the digital control circuit is based on the logic potential 'Execute a corresponding action. The present invention provides an operational amplifier system and method thereof that automatically eliminates offset. The operational amplification n system and method is a paste-controller that controls the opening and closing of a first switch, a second 201249099 switch, a third switch, a fourth switch, and a fifth switch. Therefore, compared with the prior art, the present invention has the following advantages: First, when the operational amplifier system is in an offset cancellation mode, the present invention only needs to input a DC voltage; second, an operational amplifier of the present invention can be used as a comparator, thereby saving the area of the amplifier system. Second, the operational amplifier system can enter the cancellation offset mode upon startup, or the operational amplifier system can operate according to a pulse width modulation signal. After a period of time, the operational amplifier system enters the cancellation offset mode when the pulse width modulation signal is at a logic low level, that is, the operational amplifier system can enter the cancellation offset at any time according to a user's needs. mode. [Embodiment] FIG. 2 is a schematic diagram showing an operational amplifier system capable of automatically eliminating offsets according to an embodiment of the present invention. The operational amplifier system 2 includes a control H 202, - a switch 2〇4, a second switch 2Q6, a third switch 2〇8, a fourth switch 210, a fifth switch 212, an operational amplifier 214, a digital control circuit 216 and a cancellation offset circuit 218. The controller 2〇2 is configured to generate a control signal cs when the operational amplifier system 200 is in the -offset mode; the first switch has a -first end, which is preceded by the first input of the operational amplifier system 2 (10), a second end is configured to receive the control signal Cs, and a third end; the second switch 2〇6 has a first end, which is connected to the second input end of the operational amplifier system 2〇〇, and a second end For receiving the control signal cs, and the third terminal; the third switch 2〇8 has a first end, which is outputted to the third end of the first switch 204, and a second end for receiving the control signal cs, and Second; ^ 'lightly connected to the third end of the second switch 206; the fourth switch 21 〇 has a 201249099 first end, - second end for receiving the control signal (10), and - the third end; the fifth switch The 212 has a first end coupled to the first end of the fourth switch 21A, and a second end for receiving the control minus CS, and the third end is reduced from the output (10) of the Meixian County system, wherein When the operational amplifier system is in the elimination of the offset mode, the first switch 2〇4, the third switch 2〇8, and the fourth switch (10) are opened according to the control signal cs And the second switch 2G6 and the fifth_212 are controlled according to the control signal cs_, or when the operational amplifier system 2 is in the offset cancel mode, the second switch 2〇6, the third switch 2〇8, and the fourth switch 2H According to the control number CS_, and the first switch; the fifth switch 212 is closed according to the control signal CS_. When the operational amplifier system is thinner than a normal operation mode, the first switch 204, the second switch, and the fifth switch 212 are turned on, and the third switch 208 and the fourth switch 21 are turned off. In addition, the first switch 2〇4, the third switch 208, and the fourth switch 210 may be p-type MOS transistors, and the second switch 206 and the fifth switch 212 are N-type MOS transistors; The switch 2〇4, the third switch 208 and the fourth switch 210 can be N-type MOS transistors, and the second switch 206 and the fifth switch Ή2 can be P-type MOS semi-transistors; the first switch The second switch 206, the third switch 208, the fourth switch (10), and the fifth touch 212 can be transmission questions. The operational amplifier 214 has a first input end, the handle is connected to the third end of the first switch 204, and the second input end is woven on the second open end _ ❾ third end, and the output end is connected to the fourth end. The first end of the switch 210; the digital control circuit 216 has an input terminal connected to the third end of the fourth switch 210, and an output terminal for controlling the signal according to the output of the operational amplifier 214 'output-N bit control signal The cancellation offset circuit 218 is coupled between the digital control circuit 216 and the operational amplifier 214 for controlling the offset of the operational amplifier (10) according to the N-bit control signal and the look-up table. 201249099 As shown in FIG. 2, the digital control circuit 216 includes a first latch 2162, an adder 2164, a subtractor 鸠, and a second latch 2168. The first locker 2162 has an input terminal and an output terminal. The adder 2164 has a first input terminal coupled to the output terminal of the operational amplifier 214 for receiving the signal output by the operational amplifier 214. The end handle is connected to the output end of the first latch 2162 for receiving the temporary storage value Rv stored by the first latch 2162, and an output terminal, wherein the signal output from the operational amplifier 214 is - logic low The "adder" 2164 outputs a first corrected offset value FCOS according to the logic low potential 暂 and the temporary storage value RV stored by the first-locker 2162, and the subtracter 2166 has a -th input terminal, which is connected to The output terminal ' of the operational amplifier 214 is configured to receive the signal output by the operational amplifier 214, and a second input terminal is connected to the output end of the first-locker 2162 for receiving the temporary storage value stored by the first latching device 2162. RV, and - output, wherein when the signal outputted by the operational amplifier 214 is logic potential 1 "subtractor 2166 according to the logic high potential "丨, and the temporary storage value RV stored by the first latch 2162, output one Second correction offset value sc〇s; first-locker 2 The 168 has an input terminal, the adder 2164 and the subtractor 2166, for receiving and storing the first correction offset value FCqS and the second correction offset value sc〇s, and an output end coupled to the cancellation bias The shifting circuit 218 and the input end of the first latching device 2162 are configured to output a first corrected offset value FC〇s and a second corrected offset value sc〇s to the canceling offset circuit 218 and the first-locker 2162; The first correction offset value FC〇s and the second correction offset value scous are N-bit control signals, and the first-locker 2162 is based on the first correction offset value FC〇s and the second correction offset. The value sc〇s updates the temporary value rv stored by the first latch 2162. 201249099 Please refer to FIG. 3, which is a schematic diagram illustrating the cancellation offset circuit 218. As shown in FIG. The shift circuit 218 includes a first cancellation offset circuit 2182 and a second cancellation offset circuit 2184. The first cancellation offset circuit 2182 includes first current sources 21822, 21824, 21826 and sixth switches 21842, 21844, 21846. A current source 21822 has a first end for receiving a first voltage v and a second end, the first current source 2182 4 has a first end for receiving the first voltage vi, and a second end; the first current source 21826 has a first end for receiving the first voltage vi, and a second end ' flowing through the The current of a current source 21822 is I, the current flowing through the first current source 21824 is 21 ', and the current flowing through the first current source 21826 is 41 °, but the invention is not limited to flowing through the first current. The current of the source 21822 is I, the current flowing through the first current source 21824 is 21, and the current flowing through the first current source 21820 is 41. The sixth switch 21842 has a first end coupled to the second end of the first current source 21822, and a second end for receiving a first control signal FCS generated according to the N-bit control signal and the look-up table. And a third terminal coupled to the operational amplifier 214; the sixth switch 21844 has a first end coupled to the second end of the first current source 21824, and a second end for receiving the control signal according to the N bit The first control signal FCS' and the third terminal generated by the look-up table are connected to the operational amplifier 214. The sixth switch 21846 has a first end coupled to the second end of the first current source 21826. The second end is configured to receive the first control signal fCs generated according to the N-bit control signal and the look-up table, and a third end coupled to the operational amplifier 214. As shown in Fig. 3, the second cancellation offset circuit 2184 includes second current sources 21841, 201249099 21843, 21845 and seventh switches 21862, 21864, 21866. The second current source 21841 has a first end for receiving the first voltage νι, and a second end, the first current source 21843 has a first end for receiving the first voltage VI ' and a second end; The second current source 21845 has a first end for receiving the first voltage VI and a second end, wherein the current flowing through the second current source 21841 is I, and the current flowing through the second current source 21843 is 21, and the current flowing through the second current source 21845 is 41. However, the present invention is not limited to the current flowing through the second current source 21841 being I, the current flowing through the second current source 21843 being 21, and the current flowing through the second current source 21845 being 41. The seventh switch 21862 has a first end coupled to the second end of the second current source 21841, and a second end 'for receiving a second control signal SCS' generated according to the N-bit control signal and the look-up table. And a third end coupled to the operational amplifier 214; the seventh switch 21864 has a first end coupled to the second end of the second current source 21843, and a second end for receiving the control signal according to the N bit And the second control signal scs generated by the look-up table, and a third end coupled to the operational amplifier 214; the seventh switch 21866 has a first end 'furnace at the second end of the second current source 21845... the second end The second control signal scs generated according to the N-bit control signal and the look-up table is received, and a second end is coupled to the operational amplifier 214. — Please refer to 4A ® and 4B g. Figure 4A is a schematic diagram illustrating the operation of the operation panel 2〇0 in the normal operation mode, and Figure 4B is a schematic diagram illustrating the operation of the operation release system 200 in the elimination of the offset mode. . As shown in Fig. 4α, when the ampere amplifier system 200 is operating in the normal operation mode, the first switch 2: 2 (four) five er. 2Q8 and (4) off; Thus, the first input IN? As shown in FIG. 4B, when the operational amplifier system 200 operates in the cancel offset mode, the first switch 204, the third switch 208, and the fourth switch 210 are turned "on" according to the control signal cs, and the second switch 206 and the fifth switch 212. According to the control signal cs off. The first input INP of the nose amplifier system 200 receives the DC voltage V2. In addition, if the second switch 206 is turned on according to the control signal CS, and the first switch 204 is turned off according to the control signal CS, the straight input voltage V2 is received by the second input terminal _ of the operational amplifier system 2A. Because the third switch 208 is turned on, the first input terminal and the second input terminal of the operational amplifier 214 receive the DC voltage V2 at the same time, and the operational amplifier 214 generates a logic potential according to the offset of the DC voltage V2 and the internal of the operational amplifier 214. (Lai high potential or low "G"), that is, the operational amplifier 214 is used as a comparator. When the operational amplifier 214 generates a logic low potential "G" according to the DC voltage π and the offset inside the operational amplifier 214, the adder 2164 in the digital control circuit 216 is low in logic '', and in the digital control circuit. The temporary storage value RV stored by the first locker 2162 outputs a first corrected offset value FCOS', that is, the adder applies the temporary storage value w stored by the first pickup to the ☆ to generate and output the first correction. The offset value is Fc〇s. When the op amp is called according to straight! The internal offset of V2 and operational amplifier 214 generates a temporary value stored by the subtracter in the logic high potential capture digital control circuit 216 according to the logic high potential '丫, and the first latch 2162 in the number control circuit 216, The second 13 201249099 correction offset value SCOS is output, that is, the subtractor 2166 subtracts the temporary storage value RV stored by the first latch 2162 by one to generate and output a second corrected offset value sc〇s, such as 4B. As shown, the second latch 2168 receives and stores the first corrected offset value FC0S and the second corrected offset value SC0S, and outputs a first corrected offset value fc〇s and a second corrected offset SCOS to the first The latch 2162 and the cancel offset circuit 218; the cancel offset circuit 218 cancels the offset inside the operational amplifier 214 according to the first corrected offset value FC〇s, the second corrected offset value SC0S, and the lookup table; The locker updates the temporary storage value RV stored by the first pickup 2162 according to the first correction offset value FC0S and the second correction offset value Sc〇s. In addition, the operational amplifier system 200 can enter the cancel offset mode as soon as the operational amplifier system is turned on. At this time, the temporary storage value RV stored by the first latch 2162 is the minimum value 〇〇 或 or the maximum value 11...11 of the N-bit control signal. 'Please refer to Figure 4C'. Figure 4C shows the operation of the op amp system based on a pulse width modulation signal PWM for a period of time. The op amp system is surveyed when the pulse width modulation signal PWM is logic low. Schematic diagram of the shift mode. As shown in Fig. 4C, the pulse width modulation signal pwM is logical: when the bit is set, the controller 202 generates the control signal cs. The op amp system can control the signal cs to be a logic high _, and perform the cancellation of the bit error in the operational amplifier 214. At this time, the temporary storage value RV stored by the first-locker 2162 is the temporary storage value of the previous time. 201249099 Please refer to FIG. 2, FIG. 3, FIG. 4D and FIG. 4E. FIG. 4D is a schematic diagram of a look-up table 400 for explaining the relationship between the 4-bit control signal, the first control signal FCS and the second control signal milk. And FIG. 4E is a schematic diagram illustrating the elimination of the offset inside the operational amplifier 214. As shown in Fig. 4D, the 4-bit control signal has 16 sets of control signals', and each of the sets of control signals is applied to the -th control signal FCS and the second control signal SCS. As shown in FIG. 4E, for example, the temporary value RV stored in the first-locker 2162 is 0000, and the offset inside the operational amplifier 214 is a negative value, the operational amplifier 214 is based on the DC voltage V2 and the inside of the operational amplifier 214. The offset produces a logic low "G". Then, the adder 2164 adds - the temporary value RV(0000) stored by the first latch 2162 to generate and output a first corrected offset value FC〇s (_u. After a period τ of a clock CLK The cancellation offset circuit 218 changes the first cancellation offset circuit 2182 and the second cancellation offset circuit 2184 to the operational amplifier 214 (four) stream according to the first correction offset value FCOS (OOO1) and the look-up table 400 to adjust the operational amplifier 214. The internal offset, that is, when the first correction offset value is only 〇〇〇ι, the second control signal SCS is 〇〇〇 and the first control signal FCS is lu. Therefore, the first cancellation bias The current flowing into the operational amplifier 214 by the shift circuit 2182 is π, and the current flowing into the operational amplifier 214 by the second canceling offset circuit 2184 is zero. If the operational amplifier 214 is still generated according to the DC voltage V2 and the offset inside the operational amplifier 214, The logic low potential is “0.” The adder 2164 adds a temporary value RV(oooi) stored by the first-locker to generate a first corrected offset value FC〇s(10)(9). The period of the clock CLK is passed. After τ, the cancellation offset circuit 218 is based on the first correction bias The value FCOS (OOIO) and the look-up table 4〇〇 change the current flowing into the operational amplifier 214 by the first cancellation offset circuit 2182 and the second cancellation offset circuit 2184 to adjust the offset inside the operational amplifier 214 15 201249099. Thus, The operational amplifier 214 generates a logic high potential Ί" according to the DC voltage V2 and the offset inside the operational amplifier 214. At this time, as shown in FIG. 4E, the first correction offset value FC0S is a plane, and the subtractor 2166 is based on logic. The zeta potential 1 subtracts the temporary storage value RV (〇1〇〇) stored by the first latch 2162 to generate and output a second corrected offset value sc〇s(()1(K)). The first locker Μα stores the temporary Wei RV (4 minus (four) camphor) will continue to jump between the circle and _ 'that is, the operational amplifier system · $ into the elimination of the internal offset of the operational amplifier 214 4E The present invention is not limited to the example of the first invention. Referring to FIG. 5, FIG. 5 illustrates an operational amplifier system capable of automatically eliminating offsets according to another embodiment of the present invention. Schematic of 5(8). Operational Amplifier System · and Operational Amplifier System 200 The operational amplifier system 5 (8) further includes a d-reactor 2170. The D-type flip-flop 2170 is connected between the digital control circuit 216 and the operational amplifier 214 to quickly bring the signal output from the operational amplifier 214 to a logic potential. "Γ and logic low potential "〇, '. In addition, the remaining operating principles of the operational amplifier system leakage are the same as the operational amplifier system 2 (10), and will not be described here. Please refer to Figure 6, Figure 6 is the present invention Another embodiment illustrates a flow chart of a method for automatically eliminating offsets. The method of FIG. 6 is illustrated by the operational amplifier system 200 of FIG. 2. The detailed steps are as follows: Step 600: Start; 201249099. Step 602: Step 604: Step 606: Step 608: Step 610: Step 612: Step 614: Step 616: Step 618: When the operational amplifier system 200 is in the offset cancellation mode, the controller 202 generates the control signal CS; the first switch 204, the third switch 208, and the fourth switch 21 are said to be "on" and "first" according to the control 5fl. The switch 206 and the fifth switch 212 are turned off according to the control signal CS; the DC voltage V2 is input to the first input terminal INP of the operational amplifier system 2A; the operational amplifier 214 generates a logic according to the DC voltage V2 and the offset inside the operational amplifier 214. Potential; if the operational amplifier 214 generates a logic high potential "Γ, proceed to step (4); if the operational amplifier 214 generates a logic low potential "〇", proceed to step 618; the subtractor 2166 in the digital control circuit 216 is based on the logic high potential 1 and The temporary storage value RV stored by the first latch 2162 in the digital control circuit 216 outputs a second corrected offset value sC〇s; the second shackle 11 2168 receives and stores the second corrected offset value SCOS' and the input (four) two correction offset § (10) to the first latch 2162 and the cancellation offset circuit 218; the offset circuit 2 eliminates the second corrected offset value sc〇 s and lookup table · 'eliminate the internal offset of the operational amplifier 214; the first pickup benefit 2162 according to the second corrected offset value SCOS, update the temporary storage value Rv stored by the first lock 2162, jump back to step 6 〇 8; The adder 2164 in the digital control circuit 216 outputs the first corrected offset value FC〇s according to the logical low potential 17 201249099 “〇” and the temporary storage value RV stored in the first pickup 216 in the digital control circuit 216; The second pick-up receives and stores the first-corrected offset value FCOS, and outputs the first corrected offset value Fc〇s to the first latch 2162 and the cancel-off offset circuit 218; Step 622: The cancel-off offset circuit 218 is The first correction offset value FC〇s and the look-up table are performed to eliminate the offset inside the operational amplifier 214. Step 624: The first pick-up device moves to update the first latch 2162 according to the first corrected offset value. The stored temporary value Rv, jump back to step _; in step 606, because the third switch 2 The 〇8 system is turned on, so the first input terminal and the second input terminal of the operational amplifier 214 receive the DC dragon% at the same time. In step 6〇8, the operational amplifier 214 is based on the DC voltage % and the operation amplification _ internal offset. Generate a logic potential (logic high, or logic low), that is, the operational amplifier 214 is used as L in step _ subtraction 2166^^^, 2162^^ ^ . In the step, the canceling offset circuit 218 changes the current flowing into the operational amplifier 214 by the first canceling offset circuit and the offset circuit according to the first: offset value SCOS and the lookup table 4A to adjust the operation. Put = two internal offsets. In the step, the adder 2164 = the storage temporary value RV plus -, the call read (four) - the correction offset value fc 〇 s. In FIG. 22, the cancellation offset circuit 218 adjusts the current flowing into the operational amplifier 214 according to the first correction offset value and the correction of the kth/division offset circuit 2 i 8 2 and the second cancellation offset circuit 2 (8) 201249099. The offset inside amplifier 214. In summary, the present invention provides an automatically cancelable offset operational amplifier system and method thereof for controlling a first switch, a second switch, a third switch, a fourth switch, and a fifth and a . Therefore, compared with the prior art, the present invention has the following advantages: 帛, when the operation data, the secret silk bias type, the invention only needs to input a DC cake; the second, the operation amplification ϋ can be used as a comparison 'Therefore, it can save the area of the op amp system; third, the op amp system can be used to eliminate the offset mode, or the op amp system can operate according to the pulse width. When the pulse width modulation signal is logic low, the input operation amplifier system can be used to eliminate the offset mode at any time according to the needs of the user. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. [Simplified description of the drawings] The first P is a prior art, and the following is an illustration of a shiftable amplifying system. The second embodiment of the present invention is a description of an embodiment of the present invention. Schematic diagram. Figure 3 is a schematic diagram illustrating the elimination of the offset circuit. Figure 4A is a diagram illustrating the operation of the operational amplifier system in a normal mode of operation. 201249099 Figure 4C shows a schematic diagram of the operation of the amplifier system in the offset mode. The op amp system starts operating according to the pulse width modulation signal. Potential V: ’? The amplifier system is in the schematic diagram of the pulse-shifting signal system, which is logic low, etc. 4:= Schematic diagram of a look-up table of the relationship between the 4-bit control signal, the first control signal and the second control signal. The fourth diagram is a schematic diagram illustrating the elimination of the offset inside the operational amplifier. Figure 5 is a schematic illustration of an operational amplifier system that automatically eliminates offsets, in accordance with another embodiment of the present invention. Figure 6 is a flow diagram of a method for automatically eliminating offsets in accordance with another embodiment of the present invention. [Main component symbol description] 100, 200, 500 operational amplifier system 102 '214 operational amplifier 104 comparator 106, 202 controller 108, 218 elimination offset circuit 110, 112 switch 204 first switch 206 second switch 208 third switch 210 Fourth switch 201249099 212 Fifth switch 216 Digital control circuit 400 Lookup table 2162 First locker 2164 Adder 2166 Reducer 2168 Second locker 2170 Type D flip-flop 2182 First cancel offset circuit 2184 Second Elimination offset circuit 21822, 21824, 21826 first current source 21842, 21844, 21846 sixth switch 21841, 21843, 21845 second current source 21862, 21864, 21866 seventh switch "ο" logic low potential "1" logic high potential CLK Clock CR Comparison Result CS Control Signal FCOS First Correction Offset Value FCS First Control Signal I, 21, 41 Current INN Second Input 21 201249099

INP

OCS

OUTN

OUTP

OUT

PWM

RV

SCS

SCOS

T

VI V2 VP, VN, VOUT 600 to 624 The first input eliminates the offset signal, the second output, the first output, the output, the pulse width modulation signal, the temporary value, the second control signal, the second correction offset, the period, the first voltage. DC voltage signal step C* ^8 22

Claims (1)

201249099 VII. The scope of application for patents: 1. The species can be self-contained. The operational amplifier cancellation system includes: a controller for generating a control signal when the operational amplifier system is in an offset cancellation mode; and a second switch input terminal and a third switch second The first end has a first end connected to the first second end of the operational amplifier system for receiving the control signal, and a third end; having a first end coupled to the operational amplifier system The second second end is configured to receive the control signal and a third end; the first end is coupled to the third end of the first switch, and the second end is configured to receive the control signal and the first a third end, connected to the third end of the second switch; a fourth switch having a - first end, a second end for receiving the control signal, and a third end; a fifth switch 'having a first end, a second end, a second end 'to receive the control base, and a third end connected to the output of the operational amplifier system; an operational amplifier having a a first input end coupled to the third of the first switch a second input end coupled to the third end of the second switch, and an output end 'coupled to the first end of the fourth switch; a digital control circuit having an input coupled to a third end of the fourth switch, and an output end for outputting an N-bit control signal according to the signal output by the operational amplifier, wherein N21; and 23 201249099 - the cancellation offset circuit are coupled to the digital control The circuit and the operational amplifier are configured to cancel the offset inside the operational amplifier according to the bit control signal and a look-up table; wherein the first switch, the third when the operational amplifier system is in the offset cancellation mode The switch and the fourth switch are turned on according to the control signal, and the second switch and the fifth switch are based on the (four) signal; when the operational amplifier system is in the normal operation mode, the first switch, the second switch, and The fifth opening and the third switch and the fourth switch are closed. 2. The operational amplifier system of claim 1, wherein the digital (four) circuit comprises: - the first-locker has an input, and an output; the first input is - the output of the operational amplifier , The temporary value, and the end of the towel as the zoom-in gambling adder, has a first input coupled to the receiver for receiving the shipment. The previous shackle from the 丄mi ···. 24 201249099 The first use has an input coupled to the adder and the subtractor, receives the first-corrected offset value and the second corrected offset value, and: the output terminal is lightly connected to the canceling bias The shifting circuit and the input of the first latch are configured to output the first correction offset value and the second correction offset value to the δ 扁 flat offset circuit and the first latch; The offset value and the second correction offset value are the duty control/tiger and the first-to-pick lock correction error and the second positive offset value are updated, and the first lock is stored. Temporary value. : The operation of the long term 2, the Afl system, wherein the adding 输出 outputs the first corrected offset value according to the logical & and the temporary storage value stored by the first latch, the adder will The temporary value stored by the first latch is added to generate and output the first corrected offset value. The operational amplifier system of claim 2, wherein the subtractor outputs the second corrected offset value according to the logic potential and the temporary storage value stored by the first-locker, the subtractor The first latch is stored to generate and output the second correction offset value. 5. The operational amplifier system of claim 1, further comprising: a D-type positive and negative H, between the __ digital control circuit and the operational amplifier, to enable the output of the operational amplifier to quickly reach a logic high The potential is low with a logic. The operational amplifier system of claim 1, wherein the cancellation offset circuit comprises: a first cancellation offset circuit comprising at least one first cancellation offset unit, wherein each first cancellation offset unit The first current source has a first end for receiving a first voltage and a second end, and a sixth switch having a first end coupled to the first current source a second end, a second end, configured to receive a first control signal generated by the N-bit control signal and the look-up table, and a third end coupled to the operational amplifier; and a second cancellation bias The second circuit includes a second current source having a first terminal for receiving the first voltage and a second terminal; And a seventh switch having a first end coupled to the second end of the second current source, and a second end configured to receive a second generated according to the N-bit control signal and the look-up table a control signal, and a third end coupled to the operation Amplifier. 7. The operational amplifier system of claim 1, wherein the first switch, the third switch, and the fourth open relationship are N-type MOS transistors, and the second switch and the fifth open relationship are P-type gold oxide semi-electrode. The circuit amplifier system of claim 1, wherein the first compensation, the third switch, and the fifth open relationship are p-type MOS transistors, and the second switch and the fifth The open relationship is an N-type metal oxide semi-transistor. The operational amplifier system of claim 1, wherein the first switch, the second switch, the fourth switch, and the fifth switch are transmission gates. 10. A method for automatically eliminating offsets, comprising: a field operational amplifier system: a controller generates a control signal when an offset mode is eliminated; an ith switch, a third switch, and a fourth _ according to the control The signal is turned on, and the first switch and the fifth switch are turned off according to the control signal; the input: the DC voltage is applied to the first input end of the operational amplifier system; the operational amplifier is generated according to the DC voltage and the offset inside the operational amplifier A logic potential; and a digital controller to record the operation, the implementation of the action. Π If you want the gamma square (four) towel to be amplified and the internal offset of the operational amplifier, when the straight-line voltage is generated, the digital control circuit _ adder controls the logic according to the low potential and the digital The temporary value stored in the locker of the circuit is 'rounded out' - the corrected offset value. 12. The method of claim u, wherein the digital (four) circuit_adder temporarily stores the first-corrected offset value according to the logic low level of 27 201249099 and the first-locker stored in the digital control circuit. The temporary value stored in the addition_first-locker is added to generate and output the first correction offset value. 13. The method of claim u, further comprising: a fourth lock receiving and storing the first, positive offset value, and outputting the first corrected offset value to the first latch and the canceling offset a shifting circuit; the canceling circuit cancels an offset inside the operational amplifier according to the first-corrected offset value and the -Lang; and updates the first latch storage "Hai pickup according to the first correction The temporary value of the offset value. The method of claim 10, wherein t the operational amplifier generates a high potential according to the DC voltage and the internal offset of Wei Wei H, the subtractor in the digital control circuit is based on the logic high f The bit and the temporary value stored by the first-locker in the digital control circuit, and the output - the second corrected offset value. 15. The method of claim 14, wherein the subtractor in the digital control circuit outputs the second corrected offset value according to the logic high potential and the digital (4) circuit_the first stored value of the temporary storage value. The subtractor subtracts the temporary value stored by the first latch to generate and input a second corrected offset value. 16. The method of claim 14 further comprising: 28 201249099 a first, the latch receives _ stored the second corrected offset value, and outputs the second positive offset value to the first latch An offset circuit is eliminated; ^ the circuit cancels the internal offset of the call according to the second corrected offset value and a lookup table; and updates the first latch according to the second corrected offset value Save eight, schema: 29