JP2010050590A - Comparator circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a comparator circuit reducing influence of an offset voltage generated by the difference of a threshold voltage of an MOS transistor, and high in comparison accuracy. <P>SOLUTION: In a calibration mode in which each switch is turned on, output voltages on a positive side and a negative side in an output part 5 are stored in a first capacitor Ca and a second capacitor Cb, respectively. When each switch is switched to an off-state, and this comparator circuit moves to a comparison mode, the respective voltages stored in the capacitors Ca and Cb are applied to gates of a first MOS transistor M6 and a second MOS transistor M7, and preparation of a latch operation using a compensation voltage as a reference is completed. A current latch circuit 2 determines whether to output HIGH or LOW by amplifying the difference between an input voltage and a reference voltage. In the output part 5, a voltage difference in accordance with HIGH or LOW is generated, and a current in response thereto flows. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a comparator circuit, and more particularly to a current latch circuit that reduces an influence of an offset voltage generated by a variation in threshold voltage due to a manufacturing deviation of a MOS transistor.

The comparator circuit is widely used in applications such as A-D converters, portable devices, digital cameras, etc., and compares the voltage according to the input sound or light intensity with the reference voltage to determine the magnitude, This circuit outputs a logical value of “1” or “0”.
In such applications, it is necessary to increase the determination speed and to increase the accuracy of the comparator circuit that can determine even a slight potential difference.

The comparator circuit is mainly configured by combining MOS transistors and capacitors. The MOS transistor has a property of flowing a current when given a predetermined voltage, and the voltage at this time is set as a threshold voltage.
By the way, the relationship between current and voltage in a MOS transistor has a property that depends on the ratio of channel length and channel width. MOS transistors are produced with a considerable amount of unintended dimensional deviation during manufacturing. Such a manufacturing deviation of the MOS transistor causes variations in the respective threshold voltages.

The variation in the threshold voltage of the MOS transistor generates an offset voltage in the comparator circuit. The offset voltage in the comparator circuit has a problem of degrading accuracy when comparing the input voltage with the reference voltage.
In other words, a slight difference in threshold voltage at the input of the comparator circuit is amplified at the output unit, so that there is a problem that the comparison accuracy deteriorates. Therefore, there is a need for a comparator circuit that is less susceptible to element variations.

Therefore, in order to improve the accuracy deterioration of the comparator circuit due to the offset voltage, a differential comparator having an offset cancel function including a switch and a capacitive element is known (see Patent Document 1).
The differential comparator described in Patent Document 1 closes a switch when inputting a photoelectric conversion signal, and accumulates the voltage of the photoelectric conversion signal based on the threshold voltage of the MOS transistor in the capacitor element and the signal capacitor element. Thus, the signal comparison is performed by canceling the threshold voltage, parasitic capacitance, and the like.
JP 2006-20171 A

By the way, in the calibration mode in the comparator circuit, the offset current can be adjusted to zero. Therefore, if the signal to be compared is changed from voltage to current, there is a possibility that the influence of the offset voltage can be reduced and comparison can be made.
However, since the differential comparator described in Patent Document 1 is not provided with a circuit configuration for processing by a current signal, comparison by current cannot be performed.

  An object of the present invention is to provide a comparator circuit with high comparison accuracy by outputting a voltage comparison result input in order to reduce the influence of an offset voltage as a current difference.

  A comparator circuit according to the present invention includes a differential amplifier circuit including an input unit that inputs a voltage, a reference voltage input unit that inputs a reference voltage, an output unit that outputs a voltage and a current, and a gate terminal of each other A first transistor and a second transistor having drain terminals connected to each other, a first capacitor for storing a positive voltage of the output unit, and a second capacitor for storing a negative voltage of the output unit A capacitor and a switch for switching between a calibration mode and a comparison mode, wherein the gate of the first transistor is connected to the drain of the second transistor via the second capacitor, The gate is connected to the drain of the first transistor through the first capacitor, and one end of the switch is Is connected to a fixed voltage, the other end of the switch is characterized in that the current latch circuit connected to the gates of the first transistor and the second transistor comprises (Claim 1).

  Therefore, in the comparator circuit of the present invention, the first capacitor and the second capacitor store the offset voltage in the output unit, and the voltages stored in the gates of the first transistor and the second transistor are applied, A correction voltage is performed.

  Here, storage of the offset voltage by the first capacitor and the second capacitor is performed by supplying a fixed voltage to the gates of the first and second transistors in the calibration mode in which the switch is on, and voltage correction is performed. In the comparison mode in which the switch is off, the voltage stored in the first capacitor or the second capacitor is supplied to the gates of the respective transistors (claim 2).

  In this manner, by storing the voltage applied to the gates of the first transistor and the second transistor, the offset voltage can be stored and the correction voltage can be performed by the capacitor.

  Furthermore, the differential amplifier circuit of the comparator circuit of the present invention is characterized by having an output current offset removal function for removing the offset current in the output section.

  The output current offset function may be configured so that the offset current is removed in the calibration mode.

  As described above, according to the present invention, since the signal to be compared is converted from voltage to current and the influence of the offset voltage is reduced, the comparison accuracy of the comparator circuit can be improved. In addition, this comparator circuit is a circuit that responds only to a small current difference by providing a capacitor in the latch circuit, that is, a simple circuit configuration that converts a voltage signal into a current signal, and thus is excellent in circuit integration. , High functionality can be achieved.

Hereinafter, a comparator circuit of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing a configuration of a comparator circuit of the present invention.
This comparator circuit includes a differential amplifier circuit 1 that compares and outputs input signals, and a current latch circuit 2 that holds an output state.

The differential amplifier circuit 1 includes an input unit 3 for inputting a voltage to be compared (hereinafter referred to as V _{in +} voltage input at the input unit 3), the reference voltage input unit 4 for inputting a reference voltage (hereinafter, the reference voltage V _in −), and the output unit 5 that outputs the comparison result (hereinafter, the positive side voltage and current in the output unit 5 are V _out +, I _out +, and the negative side voltage and current are V _out −, I _out- ), and MOS transistors M1, M2, M3, M4, and M5, switches SW1 and SW2, and a capacitor C1.
Each switch can be a CMOS (Complementary MOS) or the like, and the input unit 3 can be an NMOS (N-channel MOS) or the like.

The MOS transistor M5 supplies a voltage to this comparator circuit, the gate is connected to a bias voltage (Vbias), and the drain is connected to the sources of the MOS transistors M1 and M2.
In the MOS transistor M1, the input unit 3 is connected to the gate, and the plus side output unit 5 and the source of the MOS transistor M3 are connected to the drain.
In the MOS transistor M2, the reference voltage input unit 4 is connected to the gate, and the negative output unit 5 and the source of the MOS transistor M4 are connected to the drain.

Both ends of the capacitor C1 are connected to the gates of the MOS transistors M3 and M4, and store the voltage difference between the MOS transistors M3 and M4. Further, one end of the switch SW1 is connected between the MOS transistor M3 and the capacitor C1, and similarly, one end of the switch SW2 is connected between the MOS transistor M4 and the capacitor C1.
The other end of the switch SW1 is connected to the source of the MOS transistor M3.
The other end of the switch SW2 is connected to the source of the MOS transistor M4.

  In contrast, the current latch circuit 2 includes a first capacitor Ca and a second capacitor Cb, a first MOS transistor M6, a second MOS transistor M7, a third MOS transistor M8, and switches SW3 and SW4. ing.

The first capacitor Ca stores the output voltage on the plus side of the differential amplifier circuit 1 and has one end connected to the plus side of the output unit 5 and the drain of the first MOS transistor M6. The end is connected to the gate of the second MOS transistor M7.
The second capacitor Cb stores the negative output voltage of the differential amplifier circuit 1 and is connected to the drain of the second MOS transistor M7, and the other end is connected to the gate of the first MOS transistor M6. Yes.
The wiring from the first capacitor Ca to the gate of the second MOS transistor M7 and the wiring from the second capacitor Cb to the gate of the first MOS transistor M6 are connected to each other.

As described above, the drain of the first MOS transistor M6 is connected to the first capacitor Ca and the positive side of the output unit 5, and the source is connected to the drain of the third MOS transistor M8.
As described above, the drain of the second MOS transistor M7 is connected to the second capacitor Cb and the negative side of the output unit 5, and the source is connected to the drain of the third MOS transistor M8.
The third MOS transistor M8 supplies the constant voltage connected to the source to the current latch circuit 2 based on the latch clock signal connected to the gate.
The switch SW3 is connected to the gate of the first MOS transistor M6, and the other end is connected to the bias voltage (Vbias).
The switch SW4 is connected to the gate of the second MOS transistor M7, and the other end is connected to the bias voltage (Vbias).
The comparison between the mode of this comparator circuit and each switch is a comparison mode in which the switches SW1 to SW4 are switched on (energized) to shift to the calibration mode and are switched off (non-energized) to compare the input voltages. Migrate to

This comparator circuit, by storing the voltage applied to the input portion 3 in the first capacitor Ca and a second capacitor Cb, whatever the input voltage V _{in +,} only a minute current difference It is a circuit that responds.
In other words, this comparator circuit is provided with a transconductance circuit that outputs the voltage comparison result as a current difference as the differential amplifier circuit 1 and uses the voltage storage function of each capacitor for comparison without being affected by the offset voltage. Accuracy can be improved.

Although the configuration of the comparator circuit is as described above, the operation will be described.
The operation of this comparator circuit is roughly divided into three stages. The first stage is to store the offset voltage by the capacitor, the second stage is to compare the inputted input voltage with the reference voltage, and the third stage is to make an output judgment of HIGH or LOW.

First, the storage of the offset voltage by the first stage capacitor will be described.
In the calibration mode, a bias voltage (Vbias) is supplied to the gates of the MOS transistors M6 and M7 of the current latch circuit 2.
At this time, when the switches SW3 and SW4 are turned on simultaneously or slightly earlier than the switches SW1 and SW2, a leak current flows between the source and drain of the MOS transistors M6 and M7. As a result, the current at the output section 5 of the differential amplifier circuit 1 is a value obtained by equally dividing the leakage current into two.
_{I out + = I out - =} I leak / 2 (1)

That is, in the differential amplifier circuit 1, a current obtained by adding half of the leakage current to the current flowing between the drain and source in the MOS transistor M3 flows between the drain and source in the MOS transistor M1. Similarly, a current obtained by adding half of the leakage current to the current flowing between the drain and source in the MOS transistor M4 flows between the drain and source in the MOS transistor M2.
I _DS1 = I _DS3 + I _leak / 2 (2)
I _DS2 = I _DS4 + I _leak / 2 (3)
(Here, I _DSn represents the drain-source current in the MOS transistor Mn.)

Therefore, since the output current on the plus side in the differential amplifier circuit 1 is expressed by I _DS1 −I _DS3 , I _out + = I _leak / 2
It is.
Similarly, the negative output current is expressed as I _DS2 −I _DS4 .
I _out- = I _leak / 2
It is.

Thus, in the calibration mode, the offset current based on the threshold voltage of the MOS transistor can be made zero (output current offset removal function).
When the output currents in the output unit 5 are the same, the output voltage _Vout differs between the positive side and the negative side due to the influence of the offset voltage.
V _out + ≠ V _out- (6)
The first capacitor Ca and the second capacitor Cb of the current latch circuit 2 store the positive-side output voltage V _out + and the negative-side output voltage V _out − at this time, respectively.

Next, a comparison between the voltage signal input to the comparator circuit and the reference voltage will be described.
The comparator circuit shifts from the calibration mode to the comparison mode by transmitting an off signal to each of the switches SW1 to SW4 and switching from on to off.
First, when the switches SW3 and SW4 are turned off, the voltages stored in the capacitors Ca and Cb are applied to the gates of the MOS transistors M6 and M7. At this time, the positive output voltage V _out + stored earlier is applied to the gate of the first MOS transistor M7, and the negative output voltage V _out − is applied to the gate of the second MOS transistor M6.

  In this way, the negative voltage of the output unit 5 is applied to the gate of the first MOS transistor M6, while the positive voltage of the output unit 5 is applied to the gate of the second MOS transistor M7. Thus, the latch operation based on the correction voltage can be prepared.

In the comparison mode in which all the switches are off, a voltage to be compared is applied to the input voltage V _in + of the input unit 3, and the gate voltage of the MOS transistor M1 changes. At the same time, the relationship of the expression (1) is not established, and the value of the output current in the output unit 5 changes.

  The change in the output current occurs based on the voltage change in the output unit 5 caused by the change in the drain potential of the first MOS transistor M6 and the second MOS transistor M7 and the gate potential that intersects each other. Here, the current output from the current latch circuit 2 to the differential amplifier circuit 1 is a current whose offset voltage is corrected.

Next, a HIGH or LOW output in the current latch circuit 2 will be described.
The current latch circuit 2 determines the output of HIGH or LOW by amplifying the voltage difference between the input voltage and the reference voltage by positive feedback by the transistors M6 and M7 connected to each other for the output voltage in the comparison mode.
The determination of HIGH or LOW at this time is when the negative voltage is higher than the positive voltage (V _out + <V _out −), and the positive voltage is higher than the negative voltage ( Let V _out +> V _out −) be LOW.
When a voltage is supplied to the source terminals of the MOS transistors M6 and M7 by the latch clock signal connected to the gate of the third MOS transistor M8, the amplified voltage is output to the positive output voltage V according to HIGH or LOW. _out +, the negative side of the output voltage _{V out -} to appear.

FIG. 2 is a time chart showing the operation of the switches of the comparator circuit and the operation of the current latch circuit 2 described above.
This time chart shows the operation of the switch at the upper level and the operation of the latch clock signal at the lower level. The unevenness of each signal indicates ON at the rising edge and OFF at the falling edge.

Each switch switches from OFF to ON when a calibration mode signal is received 1.0 μs after the start of measurement. As described above, when the switch is turned on in the calibration mode, the offset voltage is stored in the capacitors Ca and Cb.
When the storage of the offset voltage in each capacitor is completed after 2.0 μs from the start of measurement, each switch is switched from on to off and shifts to the comparison mode.
Thereafter, in the comparison mode up to 3.0 μs, conversion from a voltage signal to a current signal is performed. As already described, an input voltage is applied to the input unit 3 after 2.5 μs. When the comparison mode is completed, the current latch circuit 2 outputs a HIGH or LOW signal based on the latch clock signal.

The operation of this comparator circuit is executed by the above operation. Next, the comparison accuracy in this comparator circuit, that is, the determination accuracy of LOW and HIGH of the current latch circuit 2 will be described.
The accuracy of this comparator circuit was verified by simulation. Simulation, the 100 [mV] was added as an offset voltage to the input voltage _{V in} +, determining the minimum of the input voltage _{V in} + the value of the determined maximum input voltage _{V in} + value and HIGH determining LOW.
Specifically, the voltage is increased from the low potential side and measured, and the current latch circuit 2 obtains the maximum voltage for determining LOW, and on the other hand, the voltage is decreased from the high potential side and measured. 2 determined the minimum voltage for determining HIGH.
The simulation was performed by applying 2.5 [V] to the reference voltage V _in −.

First, the determination of LOW by the current latch circuit 2 will be described.
The maximum input voltage for determining LOW of the current latch circuit 2 by simulation was 2.5050 [V].
FIG. 3 is a diagram showing the relationship between the input waveform and the output waveform at this voltage. FIG. 3A shows an input voltage waveform at the input voltage V _in + = 2.050 [V]. FIG. 3B shows an output voltage waveform at the input voltage V _in + = 2.050 [V].

The input voltage V _in + of the input unit 3 increases from 2.5000 [V] to 2.5050 [V] in 2.5 μs in FIG. This increase _in voltage indicates that the comparison voltage is applied to the input voltage V _in + of the input unit 3 at 2.0 μs.
In FIG. 3B, there is a difference between the positive and negative output voltages before 2.0 μs. This voltage difference is the offset voltage, and the positive and negative voltages are stored in the capacitors Ca and Cb, respectively.
Further, after 3.0 μs when the latch clock signal is generated, the plus side output voltage is larger than the minus side output power, and the difference is about 1.3 [V].
The difference between the input voltage V _in + of the input unit 3 and the reference voltage V _in − of the reference voltage input unit 4 was 5.0 [mV], but the difference between the positive and negative output voltages in the output unit 5 Is 1.3000 [V], it can be seen that the voltage is amplified and output by the positive feedback of the current latch circuit 2.

Subsequently, the minimum input voltage with which the current latch circuit 2 determines HIGH is 2.5095 [V].
FIG. 4 is a diagram showing the relationship between the input waveform and the output waveform at this voltage. FIG. 4A shows an input voltage waveform at the input voltage V _in + = 2.5095 [V]. FIG. 4B shows an output voltage waveform at the input voltage V _in + = 2.05095 [V].

For the same reason as the measurement on the low potential side, in FIG. 4A, the input voltage V _in + increases from 2.5000 [V] to 2.50995 [V] after 2.5 μs.
Further, in FIG. 4B, the difference is 9.5 [mV] at the time of input, but is amplified to 3.5000 [V] at the time of output.
Further, unlike the low potential side, the voltage at the output unit 5 is output with the negative side output V _out − larger than the positive side output V _out +.

Subsequently, the output current at the maximum voltage at which the current latch circuit 2 determines LOW and the minimum voltage at which HIGH is determined will be described.
FIG. 5A shows an output current waveform at the input voltage V _in + = 2.050 [V]. FIG. 5B shows an output current waveform at the input voltage V _in + = 2.5095 [V].

In both FIGS. 5A and 5B, the latch clock signal is received at 3.0 μs. Before that, it can be confirmed that the offset current difference I _out + −I _out − is zero.
After receiving the latch clock signal, current flows in the positive output current I _out + in the low potential side measurement, and current flows in the negative output current I _out − in the high potential side measurement. I can confirm.

3 and 4, the comparator circuit outputs LOW when the input voltage is 2.5050 [V] or less, and outputs HIGH when the input voltage is 2.05095 [V] or more. Therefore, the determination range is expressed by the following equation.
V _in + <2.5050, 2.5095 <V _in +
This comparator cannot determine HIGH or LOW for the range from 2.5095 [V] to 2.505 [V]. In the range of 4.5 [mV], since the difference between the input voltage and the reference voltage is a small value, it cannot be determined by amplifying this with a finite gain.

  Thus, this comparator circuit has a non-determinable range of 4.5 [mV] with respect to the applied offset voltage 100 [mV]. Therefore, even when the threshold voltages of the MOS transistors used for the comparator are greatly different, the comparison accuracy can be improved.

It is a circuit diagram which shows the structure of this comparator circuit. It is a time chart which shows the operation | movement of the switch of this comparator circuit, and the operation | movement of a latch. FIG. 3A shows an input voltage waveform at the input voltage V _in + = 2.050 [V]. FIG. 3B shows an output voltage waveform at the input voltage V _in + = 2.050 [V]. FIG. 4A shows an input voltage waveform at the input voltage V _in + = 2.5095 [V]. FIG. 4B shows an output voltage waveform at the input voltage V _in + = 2.5095 [V]. FIG. 5A shows an output current waveform at the input voltage V _in + = 2.050 [V]. FIG. 5B shows an output current waveform at the input voltage V _in + = 2.5095 [V].

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Differential amplifier circuit, 2 ... Current latch circuit, 3 ... Input part, 4 ... Reference voltage input part, 5 ... Output part, M1-M5 ... MOS transistor, M6 ... first transistor, M7 ... second transistor, M8 ... third transistor, C1 ... capacitor, Ca ... first capacitor, Cb ... second capacitor, SW1-SW4 ... switch

Claims (3)

A differential amplifier circuit comprising: an input unit for inputting voltage; a reference voltage input unit for inputting reference voltage; and an output unit for outputting voltage and current;
A first transistor and a second transistor, each having a gate terminal and a drain terminal connected to each other, a first capacitor for storing a positive voltage of the output unit, and a negative voltage of the output unit. A second capacitor for storing, and a switch for switching between a calibration mode and a comparison mode, wherein the gate of the first transistor is connected to the drain of the second transistor via the second capacitor; The gate of the second transistor is connected to the drain of the first transistor via the first capacitor, and one end of the switch is connected to a fixed voltage, and the other end of the switch is connected to the first transistor. Current latch circuits connected to respective gates of one transistor and the second transistor;
A comparator circuit comprising: In the calibration mode, the switch is turned on to supply a fixed voltage to the gates of the first and second transistors, and to the first capacitor and the second capacitor, the positive side of the output unit And memorize the negative voltage,
In the comparison mode, the voltage stored from the second capacitor is supplied to the gate of the first transistor by turning off the switch, and the voltage stored from the first capacitor is supplied to the second capacitor. The comparator circuit according to claim 1, wherein the comparator circuit is supplied to a gate of the transistor.   The comparator circuit according to claim 1, wherein the differential amplifier circuit has an output current offset removal function for removing an offset current in the output unit.

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