JP5169419B2 - Differential amplifier circuit and power supply circuit using the same - Google Patents

Description

  The present invention relates to a differential amplifier circuit suitable for a power supply circuit used in a semiconductor integrated circuit, and a power supply circuit using the differential amplifier circuit.

  A power supply circuit used for a semiconductor integrated circuit is required to have a low noise with little variation in output voltage value due to environmental temperature and element variation. In recent years, the use of CMOS technology has been accompanied by an active reduction in power supply voltage, and a power supply circuit driven at a low voltage has been demanded accordingly.

  FIG. 7 shows a circuit diagram of a power supply circuit having a configuration called a bandgap regulator, which is one of the configurations widely used as a power supply circuit of a semiconductor integrated circuit. As shown in FIG. 7, the conventional power supply circuit 20 includes pnp bipolar transistors Q 1 and Q 2, resistors R 1, R 2 and R 3, and a differential amplifier circuit 200. In addition, GND represents a GND voltage, Vref represents a reference voltage output terminal, IN + represents a non-inverting input terminal of the differential amplifier circuit 200, and IN− represents an inverting input terminal of the differential amplifier circuit 200. By setting the reference voltage output terminal Vref to about 1.25 V, a reference voltage having no temperature dependency can be obtained, and the circuit is very strong against changes in environmental temperature.

  The power supply circuit 20 shown in FIG. 7 has an advantage that a reference voltage can be easily generated from a relatively simple circuit configuration. However, in an actual semiconductor integrated circuit, the input voltages of the input terminals IN + and IN− of the differential amplifier circuit 200 do not completely match due to variations in characteristics of active elements. Usually, an input voltage difference between two input terminals is called an “offset voltage”. For this reason, the reference voltage output from the reference voltage output terminal Vref of the power supply circuit 20 is affected by the offset voltage of the differential amplifier circuit 200 constituting the power supply circuit 20. That is, the offset voltage of the differential amplifier circuit 200 deteriorates the accuracy of the reference voltage to be output.

  The cause of the characteristic variation of the active element is, for example, the film thickness variation of the gate insulating film of the MOS transistor, the impurity concentration variation of the source and drain, or the element size variation. These manufacturing variations depend on the manufacturing process of the MOS transistor and are unavoidable problems.

  Thus, as a method of canceling the offset voltage, a differential amplifier circuit having a chopper circuit introduced has been proposed (for example, Patent Document 1). A chopper type differential amplifier circuit 200a shown in FIG. 8 constitutes an output arithmetic circuit, pMOS transistors P1 and P2 constituting an input conversion circuit, pMOS transistors P3 and P4 constituting a constant current circuit, and a current source I. nMOS transistors N1 and N2, a capacitor Coff, and switches SW1 to SW3. In addition, VDD represents a power supply voltage, GND represents a GND voltage, IN + represents a non-inverting input terminal, IN− represents an inverting input terminal, and OUT represents an output terminal.

In the differential amplifier circuit 200a of FIG. 8, the switch SW1 and the switch SW3 are configured to be turned on / off at the same time, the switch SW2 is turned off while the switches SW1 and SW3 are turned on, and the switch SW1 and SW3 are turned off. It is configured to turn on. In the period in which the switches SW1 and SW3 are turned on (the switch SW2 is turned off), the offset voltage is detected and stored in the capacitor Coff, while in the period in which the switch SW2 is turned on (the switches SW1 and 3 are turned off). Outputs a reference voltage in which the offset voltage is canceled using the offset voltage detected in the offset detection period. For this reason, the error of the reference voltage resulting from the offset voltage is reduced.
JP 2002-202748 A

  As described above, in the differential amplifier circuit 200a of Patent Document 1 shown in FIG. 8, the offset detection period that is a period for detecting the offset voltage and the voltage output period that is the period for actually generating the reference voltage. And will be switched alternately. For this reason, the output of the differential amplifier circuit 200a operates discretely. Therefore, when the differential amplifier circuit 200a of Patent Document 1 is used for a power supply circuit, the output reference voltage oscillates and a ripple occurs with the sum of the offset detection period and the voltage output period as one cycle. That is, the conventional differential amplifier circuit 200a has a problem that noise increases.

  In view of the above problems, an object of the present invention is to provide a differential amplifier circuit with low offset and low noise, and a power supply circuit using the differential amplifier circuit.

  In order to achieve the above object, a differential amplifier circuit according to the present invention is an input for converting first and second voltage inputs, which are differential voltage inputs having a predetermined potential difference, into first and second current outputs. An operation is performed between the conversion means and the third current output corresponding to the first current output and the second current output, and a potential difference between the first voltage input and the second voltage input is calculated. Output calculating means for obtaining a corresponding fourth current output; equipotential means capable of setting the first voltage input and the second voltage input to the same potential; and When the voltage input of the second voltage input and the second voltage input have the same potential, the potential generated when the output calculation means calculates between the second current output and the third current output. Potential holding means for holding, and the output calculating means holds the potential holding means. A differential amplifier circuit that compensates for deviations in the calculation performed by the output calculation means based on the output potential, and outputs the fourth current output input from the output calculation means to the outside of the differential amplification circuit. Output buffer means, and current output storage means for storing the fourth current output input from the output calculation means, wherein the output buffer means has the same potential means as the first voltage input. When the second voltage input has the same potential, the fourth current output stored in the current output storage means is output to the outside of the differential amplifier circuit.

  In the differential amplifier circuit described above, the same potential means sets the first voltage input and the second voltage input to the same potential, and the output calculation means calculates between the second current output and the third current output. In the case of performing, the output buffer means outputs the fourth current output stored in the current output storage means, so that the same potential means sets the first voltage input and the second voltage input to the same potential. The fourth current output can be output stably before and after. Therefore, a low-noise differential amplifier circuit with little ripple can be realized.

  The voltage input of the output buffer means includes the voltage output of the output calculation means and the voltage input of the output buffer means before and after the same potential means sets the first voltage input and the second voltage input to the same potential. Are preferably set to be equipotential.

  In this case, the potential difference between the voltage output of the output calculation means and the voltage input of the output buffer means is substantially before and after the same potential means makes the first voltage input and the second voltage input the same potential. Therefore, when the same potential means sets the first voltage input and the second voltage input to the same potential, the output calculation means calculates between the second current output and the third current output. The potential generated sometimes can be stabilized. For this reason, even when the power supply voltage for driving the differential amplifier circuit is lowered, the potential does not fluctuate. As a result, the deviation of the calculation performed by the output calculation means based on the potential is not caused. Can be accurately compensated.

  A power supply circuit according to the present invention includes the differential amplifier circuit described above and a reference voltage generation unit that generates a reference voltage based on the fourth current output.

  Since the above-described power supply circuit uses the above-described differential amplifier circuit, it is possible to realize a power supply circuit in which output voltage value variation due to device variation is small, a low-noise voltage can be supplied, and low-voltage activation is possible.

  As described above, the differential amplifier circuit according to the present invention includes the output buffer means for outputting the fourth current output input from the output arithmetic means to the outside of the differential amplifier circuit, and the output arithmetic means. Current output storage means for storing the input fourth current output, and the output buffer means has the same potential means that the first voltage input and the second voltage input have the same potential. In this case, since the fourth current output stored in the current output storage means is output to the outside of the differential amplifier circuit, the same potential means makes the first voltage input and the second voltage input the same. The fourth current output can be output stably before and after the potential. Therefore, a low-noise differential amplifier circuit with little ripple can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same part, and what attached the same code | symbol in drawing may abbreviate | omit description.

(Embodiment 1)
1 is a circuit diagram showing a configuration of a differential amplifier circuit according to a first embodiment of the present invention. A differential amplifier circuit 100 according to the present embodiment is a chopper type differential amplifier circuit in which a chopper circuit is introduced. As shown in FIG. 1, an input conversion circuit 101, a constant current circuit 102, and an output arithmetic circuit. 103, an output buffer circuit 104, and switches SW1 to SW4. In addition, VDD represents a power supply voltage, GND represents a GND voltage, IN + represents a non-inverting input terminal, IN− represents an inverting input terminal, and OUT represents an output terminal.

  The input conversion circuit 101 includes pMOS transistors P1 and P2. The pMOS transistors P1 and P2 form an input differential pair. The gate terminal of the pMOS transistor P1 is connected to the inverting input terminal IN−, and the gate terminal of the pMOS transistor P2 is connected to the non-inverting input terminal IN +.

  The constant current circuit 102 includes pMOS transistors P3 and P4 and a current source I, and the pMOS transistors P3 and P4 constitute a current mirror circuit. The gate terminal and the drain terminal of the pMOS transistor P3 are short-circuited, and the pMOS transistor P3 detects the current applied from the current source I and outputs a gate voltage corresponding to the current. The gate terminal of the pMOS transistor P3 is connected to the gate terminal of the pMOS transistor P4. When the pMOS transistor P3 outputs the gate voltage to the gate terminal of the pMOS transistor P4, the drain terminal of the pMOS transistor P4 has the element of the pMOS transistor P4. A current proportional to the size ratio is copied.

  The output arithmetic circuit 103 includes nMOS transistors N1 and N2 and a capacitor Coff (potential holding means). The nMOS transistors N1 and N2 form a current mirror circuit, similarly to the pMOS transistors P3 and P4 of the constant current circuit 102. When an input voltage is input to the gate terminals of the pMOS transistors P1 and P2 of the input conversion circuit 101, the first current I1 flows through the pMOS transistor P1, and the second current I2 flows through the pMOS transistor P2. Here, in the output arithmetic circuit 103, the nMOS transistor N1 detects the first current I1 flowing through the pMOS transistor P1, and copies the detected current to the nMOS transistor N2. Then, a fourth current I4 corresponding to the difference between the second current I2 flowing through the pMOS transistor P2 and the third current I3 copied to the nMOS transistor N2 is output. The output voltage is a potential difference between the source terminal and the drain terminal of the nMOS transistor N2. The effects resulting from the arrangement of the capacitor Coff will be described later.

  The output buffer circuit 104 has a pMOS transistor P5, an nMOS transistor N3, and a capacitor Cb (current output storage means). The pMOS transistor P5 forms a current mirror circuit with the pMOS transistor P3 of the constant current circuit 102. The gate terminal of the pMOS transistor P3 is connected to the gate terminal of the pMOS transistor P5. When the pMOS transistor P3 outputs the gate voltage to the gate terminal of the pMOS transistor P5, the drain terminal of the pMOS transistor P5 is connected to the element of the pMOS transistor P5. A current proportional to the size ratio is copied. The output buffer circuit 104 temporarily holds the output voltage from the output arithmetic circuit 103. Specifically, the output buffer circuit 104 can store the output voltage from the output arithmetic circuit 103 in the capacitor Cb.

  The switch SW1 (equal potential means) is between the gate terminal of the pMOS transistor P1 and the gate terminal of the pMOS transistor P2, the switch SW2 is between the inverting input terminal and the gate terminal of the pMOS transistor P1, and the switch SW3 is the nMOS transistor N2. Between the gate terminal and the drain terminal, the switch SW4 is disposed between the output of the output arithmetic circuit 103 and the input of the output buffer circuit 104, respectively. The switches SW1 to SW4 may be configured from, for example, nMOS transistors or pMOS transistors.

  The switches SW1 and SW3 are paired with the switches SW2 and SW4. When the switches SW1 and SW3 are on, the switches SW2 and SW4 are off (hereinafter, referred to as “offset detection period”). When the switches SW1 and SW3 are off, the switches SW2 and SW4 are on (hereinafter defined as “voltage output period”). The differential amplifier circuit 100 according to the present embodiment performs different operations in the above two periods, that is, the offset detection period and the voltage output period. Hereinafter, this point will be described.

  In the differential amplifier circuit 100 according to the present embodiment, the offset detection period and the voltage detection period repeatedly arrive at a predetermined cycle. The repetition period is controlled by a clock for controlling the switches SW1 to SW4.

  Next, the operation of the differential amplifier circuit 100 in the offset detection period and the voltage detection period will be described.

  First, the offset detection period will be described.

  In the offset detection period, the switches SW1 and SW3 are turned on and the switches SW2 and SW4 are turned off. In this case, the gate terminals of the pMOS transistors P1 and P2 and the gate terminal and the drain terminal of the nMOS transistor N2 are respectively connected, while the gate terminal and the input terminal IN− of the pMOS transistor P1 are connected, and the output arithmetic circuit. The output of 103 and the input of the output buffer circuit 104 are disconnected.

  In the above connection state, the gate terminal of the pMOS transistor P1 and the gate terminal of the pMOS transistor P2 are at the same potential via the switch SW1 in the on state, so that the two pMOS transistors P1 and P2 operate in the saturation characteristic region. As long as they are ideally, the same current flows.

  However, as described above, when the characteristics of the two pMOS transistors P1 and P2 vary, the currents flowing through the pMOS transistors P1 and P2 are different from each other.

  On the other hand, when the switch SW3 is turned on, the gate terminal and the drain terminal of the nMOS transistor N2 are short-circuited, and the nMOS transistor N2 becomes a diode-connected MOS transistor like the nMOS transistor N1. Therefore, if the currents flowing through the pMOS transistors P1 and P2 are the same, the currents output to the drain terminals of the two nMOS transistors N1 and N2 are the same unless there is a characteristic variation between the two nMOS transistors N1 and N2. It will be converted to the gate voltage.

  However, as described above, if the two pMOS transistors P1 and P2 have characteristic variations, the currents flowing through the pMOS transistors P1 and P2 are different from each other. As a result, each of the nMOS transistors N1 and N2 converted from the pMOS transistors P1 and P2 The gate voltage becomes a different value. Further, when there are variations in characteristics of the nMOS transistors N1 and N2, the gate terminals of the nMOS transistors N1 and N2 are different from each other even if the currents flowing through the pMOS transistors P1 and P2 are the same. The gate voltage is output.

  That is, the offset voltage resulting from the characteristic variation of the pair of pMOS transistors P1 and P2 constituting the input conversion circuit 101 and the characteristic variation of the nMOS transistors N1 and N2 constituting the output arithmetic circuit 103 is the gate voltage of the nMOS transistors N1 and N2. It will appear as a potential difference. A capacitance Coff is arranged between the gate terminals of the nMOS transistors N1 and N2 constituting the output arithmetic circuit 103 of the present embodiment, and the potential difference between the gate voltages of the nMOS transistors N1 and N2 is applied to both ends of the capacitance Coff. And memorized.

  Next, the voltage output period will be described.

  In the voltage output period, the switches SW2 and SW4 are turned on and the switches SW1 and SW3 are turned off. In this case, the gate terminals of the pMOS transistors P1 and P2 and the gate terminal and the drain terminal of the nMOS transistor N2 are disconnected, respectively, while the gate terminal and the input terminal IN− of the pMOS transistor P1 are connected, and the output arithmetic circuit. The output of 103 and the input of the output buffer circuit 104 are connected to each other.

  In the above connection state, the gate terminal of the pMOS transistor P1 is connected to the inverting input terminal IN-, the gate terminal of the pMOS transistor P2 is connected to the non-inverting input terminal IN +, and the pMOS transistors P1 and P2 are connected to the input differential pair. Configure again. Further, the gate terminal and the drain terminal of the nMOS transistor N2 are disconnected, and the nMOS transistors N1 and N2 constitute a current mirror circuit again. Hereinafter, the operation of the differential amplifier circuit 100 in the voltage output period will be described.

  First, when a minute difference signal of two input voltages is input to the gate terminals of the pMOS transistors P1 and P2 of the input conversion circuit 101 via the input terminal IN− and the input terminal IN +, respectively, A first current I1 flowing from the VDD side to the GND side flows through P1, and a second current I2 flowing from the VDD side to the GND side flows through the pMOS transistor P2.

  On the other hand, in the output arithmetic circuit 103 that detects the first current I1 that flows through the pMOS transistor P1 of the input conversion circuit 101, the nMOS transistor N1 detects the first current I1 that flows through the pMOS transistor P1, and the detected current is nMOS. Copying to the transistor N2 and outputting to the GND line, the third current I3 is passed through the nMOS transistor N2. Then, a fourth current I4 corresponding to the difference between the second current I2 flowing through the pMOS transistor P2 and the third current I3 copied to the nMOS transistor N2 is output. The output voltage is a potential difference between the source terminal and the drain terminal of the nMOS transistor N2.

  Here, as described above, the offset voltage is already stored in the capacitor Coff of the output arithmetic circuit 103 in the offset detection period. Therefore, when the input terminals IN + and IN− have the same potential, that is, when the differential voltage is zero, the gate voltage of the nMOS transistor N2 is corrected by the potential difference of the capacitance Coff set in the offset detection period, and the pMOS transistor The third current I3 obtained by copying the first current I1 flowing through P1 to the nMOS transistor N2 by the nMOS transistor N1 is equal to the second current I2 flowing through the pMOS transistor P2. That is, the output current from the output arithmetic circuit 103 becomes zero, and the offset voltage becomes zero. Therefore, if the potential difference between the input terminals IN + and IN− is ΔVin, a voltage corresponding to ΔVin is output to the output buffer circuit 104 without being affected by the offset voltage.

  The output buffer circuit 104 outputs the voltage output from the output arithmetic circuit 103 to the output terminal, and stores the output voltage from the output arithmetic circuit 103 in the capacitor Cb. The potential difference corresponding to the output voltage of the output arithmetic circuit 103 stored in the capacitor Cb in the voltage output period is output from the output terminal as the output voltage from the output arithmetic circuit 103 in the offset detection period to be subsequently executed. By doing so, in the offset detection period, the output buffer circuit 104 can continue to output a voltage to the output terminal instead of the output arithmetic circuit 103 disconnected from the output buffer circuit 104 in order to detect the offset voltage. it can.

  As described above, in the actual operation, the offset detection period and the voltage output period are repeated at a predetermined cycle based on the clock signal, so that the output from the output arithmetic circuit 103 is discrete. However, in the offset detection period, the output voltage of the output arithmetic circuit 103 in the immediately preceding voltage output period is held by the potential difference stored in the capacitor Cb of the output buffer circuit 104. An output with little ripple can be obtained. That is, the differential amplifier circuit 100 according to the present embodiment is very effective when used as a DC amplifier.

  Next, the stability of the output voltage of the differential amplifier circuit 100 according to the present embodiment will be described. FIG. 2 is a configuration diagram of a general voltage follower using the differential amplifier circuit 100 according to the present embodiment. In this voltage follower, the output terminal of the differential amplifier circuit 100 is feedback-connected to the inverting input terminal, and the voltage follower is generally used as a buffer that outputs the input voltage with the same magnification.

  FIG. 3 shows the output waveform of the voltage follower of FIG. 2 using the differential amplifier circuit 100 according to the present embodiment and the output waveform of the voltage follower using the conventional differential amplifier circuit 200a of FIG. Show. As is apparent from FIG. 3, it can be seen that the case where the differential amplifier circuit 100 according to the present embodiment is used has less ripple and outputs a stable voltage.

  The differential amplifier circuit 100 according to the present embodiment uses a general circuit configuration of a transconductance amplifier. However, the circuit configurations of other differential amplifier circuits have the same effects as the present embodiment.

  In the differential amplifier circuit 100 according to the present embodiment, the input conversion circuit 101 is configured using pMOS transistors P1 and P2, and the output arithmetic circuit 103 is configured using nMOS transistors N1 and N2. The present invention is not limited to this configuration. For example, the input conversion circuit 101 may be configured using an nMOS transistor pair, and the output arithmetic circuit 103 may be configured using a pMOS transistor pair. In this case, the circuit configuration of the differential amplifier circuit 100 is such that all the transistors including the transistors constituting the input conversion circuit 101 and the output arithmetic circuit 103 are switched between n-type and p-type and connected to VDD and GND. The structure is reversed.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. FIG. 4 is a circuit diagram showing a configuration of the differential amplifier circuit according to the second embodiment of the present invention. The differential amplifier circuit 100a according to the present embodiment has a configuration in which a pMOS transistor P6 is inserted between the nMOS transistor N3 and the pMOS transistor P5 that constitute the output buffer circuit 104 of the differential amplifier circuit 100 of the first embodiment. It has become. The difference between the differential amplifier circuit 100a according to the present embodiment and the differential amplifier circuit 100 according to the first embodiment is only the insertion of the pMOS transistor P6. Accordingly, the other configurations are basically the same, and therefore description thereof will not be repeated here. Below, the effect resulting from the insertion of the pMOS transistor P6 will be described.

  First, a problem in the case where the pMOS transistor does not exist, that is, the problem in the differential amplifier circuit 100 according to the first embodiment will be described.

  In the differential amplifier circuit 100 according to the first embodiment, as described above, the offset voltage detection period and the voltage output period are alternately repeated. For this reason, the connection destination of the drain terminal of the nMOS transistor N2 constituting the output arithmetic circuit 103 changes between the gate terminal of the nMOS transistor N2 and the gate terminal of the nMOS transistor N3 every time the two periods are switched. To do. For this reason, if the gate voltages of the nMOS transistor N2 and the nMOS transistor N3 are different, the drain voltage of the nMOS transistor N2 fluctuates every time the two periods are switched. The fluctuation of the drain voltage of the nMOS transistor N2 means the fluctuation of the gate voltage of the nMOS transistor N2 converted from the voltage, and this causes the fluctuation of the voltage applied to the capacitor Coff. As a result, the voltage applied to the capacitor Coff fluctuates for each switching period of the above two periods, the offset voltage stored in the capacitor Coff is not stable, and thus correct offset compensation becomes difficult. That is, an offset voltage is generated in the differential amplifier circuit 100.

  In order to solve the above problem, it is necessary to make the gate voltage of the nMOS transistor N2 and the gate voltage of the nMOS transistor N3 as equal as possible. In the differential amplifier circuit 100 of the first embodiment, if VDD is sufficiently large, the current flowing through the nMOS transistor N2 is supplied from the pMOS transistor P4, and the current flowing through the nMOS transistor N3 is supplied from the pMOS transistor P5. Can be regarded as a bias current. Therefore, the gate voltages of the nMOS transistor N2 and the nMOS transistor N3 are determined by the bias currents supplied from the pMOS transistors P4 and P5, respectively, the bias currents of the pMOS transistors P4 and P5, the nMOS transistor N2 and the nMOS transistor N3, By making the ratios of the gate areas equal to each other, the gate voltages of the nMOS transistor N2 and the nMOS transistor N3 can be made substantially the same.

  However, as the power supply voltage decreases, it is expected that the current flowing through the nMOS transistor N2 cannot be regarded as the bias current supplied from the pMOS transistor P4. That is, the bias current of each of the pMOS transistors P4 and P5 decreases as the power supply voltage decreases, but the pMOS transistor P2 constituting the input conversion circuit 101 is arranged in the current path flowing from the pMOS transistor P4 to the nMOS transistor N2. ing. On the other hand, the pMOS transistor corresponding to the pMOS transistor P2 does not exist on the current path flowing from the pMOS transistor P5 toward the nMOS transistor N3. Therefore, a decrease in the current value due to the pMOS transistor P2 becomes obvious as the bias current of the pMOS transistor P4 decreases. For this reason, even if the bias currents of the pMOS transistors P4 and P5 are equal, the nMOS transistors N2 and N3 The bias current flowing into each of them will be different. That is, a difference occurs between the gate voltages of the nMOS transistors N2 and N3.

  On the other hand, in order to solve the above problem, the differential amplifier circuit 100a according to the second embodiment of the present invention is arranged between the nMOS transistor N3 and the pMOS transistor P5 in the output buffer circuit 104 according to the first embodiment. An output buffer circuit 104a in which a pMOS transistor P6 is inserted is provided in place of the output buffer circuit 104 of the first embodiment. The pMOS transistor P6 corresponds to the pMOS transistor P2, and is arranged on a current path flowing from the pMOS transistor P5 toward the nMOS transistor N3.

  Since the gate terminal of the pMOS transistor P6 is connected to the gate terminal of the pMOS transistor P2, even when the power supply voltage decreases, the current flowing into the nMOS transistors N2 and N3 is affected by the pMOS transistors P2 and P6. Decrease in the same way. Therefore, the gate voltages of the nMOS transistors N2 and N3 are kept almost constant.

  FIG. 5 shows an output waveform of the voltage follower of FIG. 2 using the differential amplifier circuit 100 according to the first embodiment, and a voltage using the differential amplifier circuit 100a according to the second embodiment of FIG. The output waveform of the follower is shown respectively. The power supply voltage was 1.9V.

  As shown in FIG. 5A, when the differential amplifier circuit 100 according to the first embodiment is used, the gate voltage of the nMOS transistor N2 fluctuates, whereas in the second embodiment, It can be seen that when such a differential amplifier circuit 100a is used, there is almost no fluctuation.

  Further, as shown in FIG. 5B, when the differential amplifier circuit 100 according to the first embodiment is used, an output voltage deviated from the input voltage 1V is output, whereas the present embodiment It can be seen that when the differential amplifier circuit 100a according to mode 2 is used, an output of approximately 1 V is output.

  In the second embodiment of the present invention, the case where the power supply voltage is 1.9 V has been described as an example. However, since the decrease in the bias current is likely to occur when the power supply voltage is 2 V or less, the second embodiment of the present invention. The differential amplifier circuit 100a is useful when driven at 2V or less.

  In addition, the differential amplifier circuit 100a according to the second embodiment of the present invention uses a general transconductance amplifier circuit configuration as in the first embodiment. The configuration has the same effect as the present embodiment.

  Further, in the differential amplifier circuit 100a according to the second embodiment of the present invention, the pMOS transistor P6 is newly inserted, but a resistor having a predetermined resistance value may be inserted instead of the pMOS transistor P6. I do not care. In this case, the resistance value of the inserted resistor may be set in accordance with the current value decreased by the pMOS transistor P2.

  Further, in the differential amplifier circuit 100a according to the second embodiment of the present invention, the input conversion circuit 101 is configured using pMOS transistors P1 and P2, and the output arithmetic circuit 103 is configured using nMOS transistors N1 and N2. However, the present invention is not limited to this configuration. For example, the input conversion circuit 101 may be configured using an nMOS transistor pair, and the output arithmetic circuit 103 may be configured using a pMOS transistor pair. In this case, the circuit configuration of the differential amplifier circuit 100 is such that all the transistors including the transistors constituting the input conversion circuit 101 and the output arithmetic circuit 103 are switched between n-type and p-type and connected to VDD and GND. The structure is reversed.

(Embodiment 3)
Next, a third embodiment of the present invention will be described. The present embodiment relates to a power supply circuit using the differential amplifier circuit according to the first and second embodiments. FIG. 6 is a diagram showing a configuration of a power supply circuit using the differential amplifier circuit according to the first and second embodiments of the present invention.

  The power supply circuit according to the present embodiment includes pnp bipolar transistors Q1, Q2 (reference voltage generation means), resistors R1, R2, R3 (reference voltage generation means), and the differential according to the first or second embodiment. The amplifier circuit 100 is composed of 100 and 100a. In addition, GND is a GND voltage, Vref is a reference voltage output terminal, IN + is a non-inverting input terminal of the differential amplifier circuits 100 and 100a, and IN− is an inverting input terminal of the differential amplifier circuits 100 and 100a.

  In the power supply circuit according to the present embodiment, a voltage output from the reference voltage output terminal is obtained by detecting the difference between the voltage between the base terminals and the emitter terminals of the diode-connected pnp bipolar transistors Q1 and Q2. By setting the voltage to about 1.25 V, a reference voltage having no temperature dependence can be obtained, and this is a commonly used circuit format. As described above, the most dominant factor for the variation in the reference voltage is the offset voltage of the differential amplifier circuit. When this offset voltage is Voff and the output voltage when the offset is zero is Vref, the offset voltage Voff is The output voltage Vref ′ in a certain case is expressed by the following equation.

Vref ′ = Vref− (1+ (R2 / R3)) × Voff
As apparent from the above equation, the offset voltage Voff is multiplied by (1 + R2 / R3) and appears in the output voltage.

  In the power supply circuit according to the third embodiment of the present invention, since the offset voltage is very small by using the differential amplifier circuits 100 and 100a according to the first and second embodiments, an output voltage with little variation can be obtained. Can be obtained. Moreover, since the ripple is very small, the noise performance is also excellent.

  In addition, when the differential amplifier circuit 100a according to the second embodiment is used, a good output voltage can be obtained even by driving at a low voltage of 2V or less.

  The power supply circuit of this embodiment is generally an example of a circuit configuration of a bandgap regulator, but if it is a power supply circuit using a differential amplifier circuit, it has the same effect as this embodiment. .

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and can be obtained by appropriately combining technical means disclosed in different embodiments. Embodiments are also included in the technical scope of the present invention.

  Since the differential amplifier circuit and the power supply circuit using the same according to the present invention can stably generate the reference voltage even when operated using the low power supply voltage, the reference voltage of the analog circuit for the low power supply voltage can be obtained. Applicable to the generated power supply circuit.

1 is a circuit diagram showing a configuration of a differential amplifier circuit according to a first exemplary embodiment of the present invention; It is a block diagram of the voltage follower concerning Embodiment 1 of this invention. It is a graph which shows the output waveform of the voltage follower concerning Embodiment 1 of this invention. FIG. 3 is a circuit diagram showing a configuration of a differential amplifier circuit according to a second exemplary embodiment of the present invention. It is a graph which shows the output waveform of the voltage follower concerning Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the power supply circuit concerning Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the power supply circuit using the conventional band gap regulator. It is a circuit diagram which shows the structure of the conventional differential amplifier circuit.

Explanation of symbols

20 power supply circuit 100, 100a, 200, 200a differential amplifier circuit 101 input conversion circuit (input conversion means)
102 constant current circuit 103 output arithmetic circuit (output arithmetic means)
104, 104a Output buffer circuit (output buffer means)
IN- Inverting input terminal (first voltage input)
IN + Non-inverting input terminal (second voltage input)
I1 First current (first current input)
I2 Second current (second current input)
I3 Third current (third current input)
I4 Fourth current (fourth current input)
SW1 switch (equal potential means)
SW2, SW3, SW4 Switch Coff capacitance (potential holding means)
Cb capacity (current output storage means)
R1, R2, R3 resistance (reference voltage generating means)
Q1, Q2 npn bipolar transistor (reference voltage generating means)
P1, P2, P3, P4, P5, P6 pMOS transistors N1, N2, N3 nMOS transistors I current source

Claims (3)

Input conversion means for converting the first and second voltage inputs, which are differential voltage inputs having a predetermined potential difference, into first and second current outputs;
A calculation is performed between a third current output corresponding to the first current output and the second current output, and a fourth corresponding to a potential difference between the first voltage input and the second voltage input. Output calculation means for obtaining a current output of
Equipotential means capable of making the first voltage input and the second voltage input the same potential;
When the same potential means sets the first voltage input and the second voltage input to the same potential, the output calculation means calculates between the second current output and the third current output. Potential holding means for holding the potential generated when
The output calculation means is a differential amplifier circuit that compensates for a deviation in calculation performed by the output calculation means based on the potential held in the potential holding means,
Output buffer means for outputting the fourth current output input from the output calculation means to the outside of the differential amplifier circuit;
Current output storage means for storing the fourth current output input from the output calculation means,
The output buffer means outputs the fourth current output stored in the current output storage means when the same potential means sets the first voltage input and the second voltage input to the same potential. A differential amplifier circuit that outputs the signal to the outside of the differential amplifier circuit.   The voltage input of the output buffer means includes the voltage output of the output calculation means and the voltage input of the output buffer means before and after the same potential means sets the first voltage input and the second voltage input to the same potential. The differential amplifier circuit according to claim 1, wherein the differential amplifier circuit is set to be equipotential. The differential amplifier circuit according to claim 1 or 2,
A power supply circuit comprising: reference voltage generating means for generating a reference voltage based on the fourth current output.

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