KR100603179B1 - A Digital Pulse Width Control Loop Circuit Without Phase change - Google Patents

Abstract

The present invention relates to a pulse width control loop circuit that maintains a constant phase information of an input signal in a pulse width control process and corrects using a digital method.

A digital pulse width control loop circuit according to the present invention includes a clock generator for generating a clock signal while adjusting a pulse width of an input clock signal ck_A; A clock driver positioned between a clock signal ck_C output from the clock generator and an output driving clock clk_out to drive a large capacitor load to an output; A pulse width comparator configured to measure and compare pulse width information of the input clock signal ck_A and the output driving clock signal clk_out, convert the pulse width information into a digital code, and output pulse width information; And a clock delay block outputting a clock signal ck_B delayed by a predetermined time from the input clock signal ck_A so that the pulse widths of the input clock signal ck_A and the output driving clock signal clk_out are the same. The clock delay block is controlled by a digital code of the pulse width comparator.

According to the present invention, the phase information of the output drive signal does not change with respect to the input signal in the process of correcting the pulse width, and the pulse width control loop is digitally controlled to easily solve the loop stability problem, and the pulse even in a power saving state. The width information can be stored.

Description

A digital pulse width control loop circuit without phase change

1 is a block diagram showing the configuration of a conventional pulse width control loop circuit.

2A is a block diagram showing the configuration of the digital pulse width control loop circuit according to the present invention, and FIG. 2B is a timing diagram of the digital pulse width control loop circuit.

3 illustrates one embodiment of a pulse width comparator.

4A illustrates one embodiment of a single-to-differential converter circuit.

4B illustrates one embodiment of a current integrator circuit.

4C shows a timing diagram of the current integrator circuit.

5 illustrates one embodiment of a clock delay block.

6A is a computer simulation result showing the waveform of an output signal at the time of inputting a signal having a pulse width of 1 GHz and 60% when the switch of the pulse width comparator operates in mode A. FIG.

 FIG. 6B illustrates a computer simulation graph of the pulse width change of the output signal according to the pulse width change of the input signal when the switch of the pulse width comparator is operated in mode A. FIG.

7A is a computer simulation result showing the waveform of an output signal at the time of inputting a signal having a pulse width of 1 GHz and 60% when the switch of the pulse width comparator operates in mode B. FIG.

 FIG. 7B shows a computer simulation graph of the pulse width change of the output signal according to the pulse width change of the input signal when the switch of the pulse width comparator operates in mode B. FIG.

The present invention relates to a pulse width control loop circuit. In particular, in the pulse width control process, the phase information of the input signal is kept constant and digitally corrected so that the entire loop characteristic is stable and the pulse width correction information is maintained even in a power saving state. A digital pulse width control loop circuit proposed for storage.

For applications such as AS-Memory (high-speed digital systems consisting of ASICs and memories) that utilize pulse width modulation (PWM) techniques, motor control, power switching, motor control, and power saving, The width is information with special meaning.

In addition, pulse signals used as clocks, especially in high-speed applications such as double data rate (DDR) SDRAM and analog-to-digital converters (ADCs), have a 50% duty cycle because both rising and falling edges are used. Must maintain the pulse width. On the other hand, in the above applications, when the pulse signal drives the circuit inside or outside the signal semiconductor chip, the pulse signal width is distorted due to the mismatch of the pull-up and pull-down circuits present in the pulse signal driving circuit. It leads to loss of information.

A typical analog pulse width control loop circuit conventionally used to solve the above problem is shown in FIG. 1.

1 is a block diagram illustrating a conventional pulse width control loop circuit, in which a pulse (clock) generator 110, a comparator 120, a loop filter 130, and a clock driving circuit are constituted by a pseudo-inverter. 140.

The pulse generator 110 outputs an output pulse signal in which the pulse width of the clock input signal CK_in is appropriately adjusted by the analog control voltage Vctrl generated by the comparator 120 and the loop filter 130. The output pulse signal drives a load of a large capacitor by the clock driving circuit 140.

The comparator 120 includes charge pumps 121 and 122, capacitors C1 and C2, and a differential amplifier 123. The comparator 120 detects a pulse width of each of the input signal CK_in and the output driving signal CK_out. According to this function, the analog control voltage Vctrl is generated through the comparator 120 and the loop filter 130 in proportion to the difference between the pulse widths of the input signal CK_in and the output drive signal CK_out, and the generated analog control voltage Vctrl is generated. The pulse generator 110 is controlled to form a negative feedback loop so that the pulse widths of the input signal CK_in and the output driving signal CK_out are kept the same.

In addition, since a clock driving circuit for driving a large capacitor load is present in the negative feedback loop, the distortion of the pulse width by the clock driving circuit is corrected.

 However, the analog pulse width control loop circuit shown in FIG. 1 has three disadvantages.

The first is that the phase information of the output driving signal CK_out changes with respect to the input signal CK_in during the pulse width correction process.

When this type of pulse width control loop circuit operates with a phase locked loop (PLL) / delay locked loop (DLL) circuit, the phase change of the signal by the pulse width control loop circuit can interfere with the phase locking of the PLL / DLL. It may cause malfunction of PLL / DLL.

The second disadvantage is that the circuit parameter values of the charge pumps 121 and 122, the capacitors C1 and C2 and the differential amplifier 123 constituting the comparator 120 affect the stability of the entire negative feedback loop.

That is, the pulse width control loop circuit may oscillate according to the voltage gains Ao, C1, and C2 of the comparator 120 of FIG. 1. To improve oscillation stability, the gain (Ao) of the differential amplifier must first be reduced, which results in lower pulse width accuracy. Therefore, it becomes more difficult to design a pulse width control loop circuit having a stable loop characteristic.

The third disadvantage is that after the pulse width correction, the control voltage information of the pulse generator 110 is not maintained in the power saving state.

This is because the conventional analog pulse width control loop circuit stores the analog control voltage in the capacitor, so that the analog control voltage stored in the capacitor changes in the power saving state. Therefore, it is difficult to use an analog pulse width control loop circuit in a system having a power saving state.

The technical problem to be achieved by the present invention is to correct the pulse width so that the pulse width of the input clock and the output driving clock is the same without changing the phase information of the input clock, and correlates the pulse width of the input clock when switching modes using a simple switch It is to provide a digital pulse width control loop circuit for controlling the pulse width for an output drive clock having a width of 1/2 of the input clock cycle (50% duty cycle).

Digital pulse width control loop circuit according to the present invention for solving the above technical problem is a clock generator for generating a clock signal while adjusting the pulse width of the input clock signal (ck_A); A clock driver positioned between a clock signal ck_C output from the clock generator and an output driving clock clk_out to drive a large capacitor load to an output; A pulse width comparator configured to measure and compare pulse width information of the input clock signal ck_A and the output driving clock signal clk_out, convert the pulse width information into a digital code, and output pulse width information; And a clock delay block outputting a clock signal ck_B delayed by a predetermined time from the input clock signal ck_A so that the pulse widths of the input clock signal ck_A and the output driving clock signal clk_out are the same. The clock delay block is controlled by a digital code of the pulse width comparator.

The pulse width comparator may further include a single-to-differential converter for converting a single clock, an input clock and an output driving clock, into a differential clock; A current integrator for supplying a clock divided by two of the input clock and integrating the input clock and the output driving clock for one period (1 / fin = T) of the input clock, respectively; A comparator for outputting an up / down signal by comparing pulse widths of two clocks with the two integral values; And a counter & register for generating the digital code by the up / down signal to control the clock delay block with the digital code so that the pulse width of the input clock and the output driving clock are the same. It is done.

In addition, the pulse width comparator has two modes, A and B, depending on the connection state of the internal switch, and in mode A, the pulse width control loop operates so that the pulse width of the input clock and the pulse width of the output clock are the same. B operates a pulse width control loop so that the output clock maintains a pulse width of 50% regardless of the pulse width of the input clock.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A is a block diagram showing the configuration of the digital pulse width control loop circuit according to the present invention, and FIG. 2B is a timing diagram of the digital pulse width control loop circuit.

2A includes a clock generator 210, a pulse width comparator 220, a clock delay block 230, and a clock driver 240.

The clock generator 210 includes a rising edge generator and a falling edge generator, and its function is to generate a clock signal while adjusting the pulse width of the input clock.

After a fixed delay time td1 at the rising edge of the input clock ck_A, the output ck_C of the clock generator 210 becomes high (1). In addition, after a fixed delay time td2 at the rising edge of the signal ck_B, ck_C becomes low (0). Where signal ck_B is the delayed replica clock of signal ck_A.

Therefore, the rising and falling edge of ck_C is determined only by the rising edge of the input clock ck_A. The delay time between the signal ck_A and the signal ck_B is adjusted to the pulse width tpw of the input clock ck_A so that the pulse widths of the input clock and the output driving clock are the same. This clock delay is achieved by a clock delay block 230 that is adjusted by the digital output of the pulse width comparator 220.

The pulse width comparator 220 measures pulse width information of the input clock ck_A and the output driving clock clk_out, compares them, and converts the pulse width information into a digital code to output pulse width information.

In addition, the pulse width information is stored in a register of the pulse width comparator 220. A clock driver 240 located between ck_C and the output drive clock clk_out was used to drive a large capacitor load at the output.

The delay time between the input clock ck_A and the output driving clock clk_out is determined by the fixed delay time td1 and the clock driver 240 between the input clock ck_A and the output ck_C at the clock generator 210. Is the sum of the fixed delay time td3. This causes the output drive clock to have a rising edge with a constant delay time td1 + td3 relative to the input clock.

In addition, since the clock driver 240 is in the feedback loop, the distortion of the pulse width generated by the clock driver circuit is corrected. Since ck_C maintains the phase information of the input clock with a constant delay time td1 for ck_A, the clock driving circuit may be replaced by a phase locked loop (PLL) or a delay locked loop (DLL).

FIG. 3 illustrates one embodiment of a pulse width comparator comprising two single-to-differential converters 310,311, two current integrators 320 and 321, a comparator 330 and a counter & register 340. FIG.

Current integrators 320 and 321 used to detect the pulse width accept a differential clock as input. Therefore, since the input clock and the output driving clock are single clocks, the input clock and the output driving clock must be converted into differential clocks by the single-to-differential converters 310 and 311 and input to the current integrators 320 and 321, respectively.

In FIG. 3, switches 327 and 328 are operated in mode A for basic pulse width control. In mode A, the pulse width control loop operates so that the pulse width of the input clock is equal to the pulse width of the output clock.

Two current integrators 320 and 321 supply clocks divided by two of the input clocks to integrate the input clock and the output driving clock for one period (1 / fin = T) of the input clock, respectively. The pulse widths of the two clocks are compared by comparing the two integrated values through the comparator 330. If the two integrals output the same value, the pulse widths of the input clock and output drive clock are the same.

Since the outputs of the two current integrators 320 and 321 must all be compared, a four-input comparator is used. The output of the comparator 330 generates an up / down signal to generate a digital code at the counter & register 340.

The counter & register 340 controls the clock delay block with a digital code so that the pulse widths of the input clock and the output driving clock are the same, and a 2-bit binary code and a fine ( fine) Generates a 5-bit binary code for correction.

On the other hand, the correction information of the pulse width is stored as a digital code in the counter & register 340 register to store the correction information even in a power saving state.

In the present invention, a clock fin / 8 divided by an input clock is used as a clock for operating the comparator 330 and the counter & register 340. This is determined by considering the delay time of the output driving circuit for the stability of the entire pulse width loop.

For an output driving clock having a width (50% duty cycle) 1/2 of the input clock cycle regardless of the pulse width of the input clock, the switch is changed to mode B as shown in FIG. In this case, the pulse width of the output driving clock is detected without maintaining the 50% pulse width. That is, the delay time of the clock delay block is about one half of the input clock period, and the negative feedback loop is performed such that the section of high (1) and the section of low (0) of the output driving clock are the same.

FIG. 4A shows the single-to-differential converter of FIG. 3, and FIG. 4B shows the detailed circuit of the current integrator of FIG. 3, where vb denotes a bias voltage and an inverted signal of silver.

4C shows a timing diagram of a single-to-differential converter and current integrator.

 Since the current integrators 320 and 321 need to input differential clocks, a single clock must be converted into a differential clock (A, / A) using a single-to-differential converter (310,311). For this purpose, the single-to-differential converters 310 and 311 are shown in Fig. 4a as an example consisting of two and three simple inverter chains each in the ratio of device sizes of 1: 3 and 3: 3: 3.

The current integrators 320 and 321 operate in two modes in synchronization with two divided clocks of the clock input to the pulse width control loop circuit.

In the first equalize mode, in Figure 4b, mn0 and mn1 are turned on and mn2 and mn3 are turned off by the operating characteristics turned on at the high voltage of the NMOS and turned off at the low voltage, so that the two output nodes Vop and Vom of the current integrator are inside the current integrator. Unaffected by voltage changes, Va and Vb are discharged to ground level to eliminate the effects of the previous state.

In the second integrated mode, as shown in FIG. 4C, fin / 2 has a low voltage value. In the current integrator circuit of FIG. 4B, mn0 and mn1 are turned off, and mn2 and mn3 are turned on. The operation of turning off at high voltage and turning on low voltage of PMOS causes mp3 and mp4 to turn on for the pulse width of differential input clocks A and / A. As shown in Fig. 4C, mp4 is turned on by the input clock A while the input clock is at L level, and mp3 is turned on by / A while the input clock is at the H level. Therefore, current supplied from the current source mp0 accumulates in Va and Vb for a time corresponding to the pulse widths of A and / A, and the current integrator outputs an integral value proportional to the pulse width difference of the input clock. mp1, mp2, mp5 and mp6 are added transistors to compensate for the charge inflow that occurs during mp3 and mp4 switching operations by input clocks A and / A.

If the pulse width of the input clock is half of the period (50% duty cycle), the differential output (Vop-Vom) of the current integrator 320 is zero and the pulse width of the input clock is half of the period (50% duty cycle). In case of deviation from the duty cycle, the differential outputs of the current integrators 320 and 321 output a value proportional to the degree of deviation. Through this process, relative values of the pulse width of the input clock can be detected using the current integrators 320 and 321.

5 illustrates one embodiment of a clock delay block.

Clock delay blocks are coarse delay lines controlled by 2-bit binary code and fine delay lines controlled by 5-bit binary code to improve operation and accuracy over a wide range. It is composed of

One unit of the coarse delay line consists of a nand gate with a delay of approximately 100ps. The coarse delay line consists of all four stages of Nand gate logic, resulting in a total delay of 400ps. The fine delay line is a 5-bit binary code, and the delay time of about 150ps is divided into 64 (2 ⁵ ) equals by the control input and is finely controlled.

FIG. 6A is a result of computer simulation of the waveform of an output driving clock for an input clock having a pulse width of 1 GHz and 60% when the pulse width comparator is operated in mode A for the circuit of the present invention shown in FIG. 2. It shows a clock with a pulse width of 60.3%.

FIG. 6B is a computer simulation result of the transition of the pulse width of the output clock according to the change of the pulse width of the input clock when the pulse width comparator is operated in mode A for the circuit of the present invention shown in FIG. 2. As shown in this result, the digital pulse width control loop circuit of the present invention can drive a clock having a pulse width of 25% to 75% for an input clock of 1 GHz, and the width of the output clock pulse relative to the input clock pulse. The error is less than 0.4%.

FIG. 7A illustrates a computer simulation of the waveform of an output driving clock with respect to an input clock having a pulse width of 1 GHz and 60% when the pulse width comparator is operated in mode B for the circuit of the present invention. This shows that a clock with a pulse width of 50.3% is independent of the pulse width of the clock.

0.3% 의 동일한 펄스 폭을 가지는 클럭이 출력됨을 보여준다.FIG. 7B is a simulation result of a computer simulation of the transition of the pulse width of the output clock according to the change in the pulse width of the input clock when the pulse width comparator is operated in the mode B for the circuit of FIG. 2. As shown in this result, the digital pulse width control loop circuit of the present invention is 50 GHz for an input clock having a pulse width of 1 GHz, 25% to 75%.

It shows that the clock with the same pulse width of 0.3% is output.

In the present invention, the phase information of the output driving signal does not change with respect to the input signal during the pulse width correction process. This feature makes it possible for applications in System On Chip (SOC) applications that use a pulse width control loop circuit and a PLL / DLL circuit. By controlling the pulse width digitally, the stability problems that arise in analog systems are easily solved. This is possible by adjusting the frequency of the operation clock of the counter & register 340 in the pulse width comparator 220 according to the magnitude of the delay time of the output driving circuit. In addition, the pulse width control loop circuit is operated by a digital method to store the pulse width information even in the power saving state after the pulse width correction.

As described above, the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, and those skilled in the art may understand that various modifications and equivalent other embodiments are possible therefrom. will be. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention, the phase information of the output driving signal does not change with respect to the input signal during the pulse width correction process. This feature can be used in application of SOC (System On Chip) using pulse width control loop circuit and PLL / DLL circuit.

In addition, by controlling the pulse width digitally, it is easy to solve the stability problem that occurs in the analog method to simplify the design.

Further, by operating the pulse width control loop circuit digitally, the pulse width information can be stored even in the power saving state after the pulse width correction.

Claims (10)

In the pulse width control loop circuit in which the phase information of the input signal is kept constant in the pulse width control process and corrected by using a digital method, A clock generator for generating a clock signal while adjusting a pulse width of the input clock signal ck_A; A clock driver positioned between a clock signal ck_C output from the clock generator and an output driving clock clk_out to drive a large capacitor load to an output; A pulse width comparator configured to measure and compare pulse width information of the input clock signal ck_A and the output driving clock signal clk_out, convert the pulse width information into a digital code, and output pulse width information; And And a clock delay block outputting a clock signal ck_B delayed by a predetermined time from the input clock signal ck_A so that the pulse widths of the input clock signal ck_A and the output driving clock signal clk_out are the same. And the clock delay block is controlled by a digital code of the pulse width comparator. The pulse width comparator of claim 1, wherein the pulse width comparator A single-to-differential converter for converting a single clock, an input clock and an output driving clock, into a differential clock; A current integrator for supplying a clock divided by two of the input clock and integrating the input clock and the output driving clock for one period (1 / fin = T) of the input clock, respectively; A comparator for outputting an up / down signal by comparing pulse widths of two clocks with the two integral values; And And a counter & register for generating the digital code by the up / down signal to control the clock delay block with the digital code so that the pulse width of the input clock and the output driving clock are the same. Digital pulse width control loop circuit. The method of claim 2, wherein the single-to-differential automatic converter A digital pulse width control loop circuit comprising two and three inverter chains each in a ratio of 1: 3 and 3: 3: 3 device sizes. 3. The current integrator of claim 2 wherein It is operated in equalize mode and integrate mode in synchronization with the clock divided by the clock input to the pulse width control loop circuit. In the equalize mode, the output node of the current integrator is discharged to ground level to remove the influence of the previous state. In the integrate mode, an integral proportional to the difference in pulse widths between the differential input clocks. A digital pulse width control loop circuit characterized in that it outputs a value. The method of claim 2, wherein the counter & register A digital pulse width control loop circuit for generating a 2-bit binary code for coarse correction and a multi-bit binary code for fine correction. The method of claim 5, wherein the counter & register (register) A digital pulse width control loop circuit which stores pulse width information as a digital code. The method of claim 1, wherein the clock delay block It is composed of coarse delay line controlled by 2-bit binary code and fine delay line controlled by 5-bit binary code to improve operation and accuracy in a wide area. Digital pulse width control loop circuit. The method of claim 7, wherein The unit of the coarse delay line (coarse delay line) is a pulse width control loop circuit of the digital method characterized in that the NAND gate is composed of an even number of NAND gates in total. The method of claim 7, wherein And wherein the fine delay line is configured to be controlled by a plurality of bits of binary code. The method according to claim 1 or 2, The pulse width comparator has a plurality of operation modes, in one operation mode such that the pulse width of the input clock is equal to the pulse width of the output clock, and in the other operation mode, the output is independent of the pulse width of the input clock. A digital pulse width control loop circuit, wherein the clock maintains a pulse width of 50%.

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