JP3384543B2 - Cascade A / D converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cascade A / D converter, and more particularly to a cascade A / D converter capable of improving a propagation delay time.

[0002]

2. Description of the Related Art As a conventional cascade A / D converter, there is a cascade A / D converter described in Japanese Patent Application No. 08-322709 filed by the present applicant. FIG. 6 is a configuration block diagram showing an example of a conventional cascade A / D converter described in Japanese Patent Application No. 08-322709.

In FIG. 6, 1a, 1b, 1c, 5a, 5
b, 5c, 5d, 5e and 5f are comparators, 2a, 2b,
2c and 2d are latch circuits, 3a and 3b are D / A converters, 4a and 4b are subtractors, 6, 7, 8 and 13 are AND circuits (hereinafter referred to as AND circuits), and 9 and 11 are exclusive. Logical OR circuits (hereinafter referred to as EOR circuits), 10 and 12 are logical OR circuits (hereinafter referred to as OR circuits), 10
0 is an analog input signal and 101 is a digital output signal.

Further, 5a, 5b and 6 are window comparators 50a, 5c, 5d and 7 are window comparators.
Comparators 50b, 5e, 5f and 8 constitute a window comparator 50c, and 10, 12 and 13 constitute an error correction circuit 51.

The analog input signal 100 is input to the non-inverting input terminals of the comparators 1a and 5a, the inverting input terminal of the comparator 5b, and the addition input terminal of the subtractor 4a. The output of the comparator 1a is the latch circuit 2a, the D / A converter 3a, and the EOR circuit 9
Of the D / A converter 3a, and the output of the D / A converter 3a is connected to the subtraction input terminal of the subtractor 4a.

The outputs of the comparators 5a and 5b are connected to the input terminals of the AND circuit 6, respectively, and the output of the AND circuit 6 is one input terminal of the OR circuit 10 and the negative logic input terminals of the AND circuits 7 and 13. It is connected to one negative logic input terminal of the AND circuit 8.

The output of the subtractor 4a is the non-inverting input terminals of the comparators 1b and 5c, the inverting input terminal of the comparator 5d, and the subtractor 4
It is connected to the addition input terminal of b. The output of the comparator 1b is D
/ A converter 3b, the other input terminal of the EOR circuit 9, EO
It is connected to one input terminal of the R circuit 11, and the output of the D / A converter 3b is connected to the subtraction input terminal of the subtractor 4b.

The outputs of the comparators 5c and 5d are connected to the other two positive logic input terminals of the AND circuit 7, and the output of the AND circuit 7 is one input terminal of the OR circuit 12 and the other of the AND circuit 8. Connected to the negative logic input terminal of. Further, the output of the EOR circuit 9 is connected to the other input terminal of the OR circuit 10, and the output of the OR circuit 10 is connected to the latch circuit 2b.

The output of the subtractor 4b is connected to the non-inverting input terminals of the comparators 1c and 5e and the inverting input terminal of the comparator 5f. The output of the comparator 1c is connected to the other input terminal of the EOR circuit 11, and the output of the EOR circuit 11 is connected to the other input terminal of the OR circuit 12. The output of the OR circuit 12 is A
It is connected to the positive logic input terminal of the ND circuit 13, and the output of the AND circuit 13 is connected to the latch circuit 2c.

The outputs of the comparators 5e and 5f are connected to the other two positive logic input terminals of the AND circuit 8, and the output of the AND circuit 8 is connected to the latch circuit 2d. Further, the outputs of the latch circuits 2a to 2d are output as the digital output signal 101.

The inverting input terminals of the comparators 1a to 1c are grounded, and the non-inverting input terminals of the comparators 5b, 5d and 5f receive a voltage of "+ ΔV" and the inverting input terminals of the comparators 5a, 5c and 5e. A voltage of "-ΔV" is applied to each. However, “ΔV = FS / 16”.

The operation of the embodiment shown in FIG. 6 will be described with reference to FIG. FIG. 7 shows “−FS / 2” to “+ FS /
It is a characteristic curve figure which shows each output or each input with respect to the analog input signal 100 of "2".

In FIG. 7, (a), (b) and (c) are outputs of the comparators 1a, 1b and 1c, and (d), (e) and (f) are outputs of the window comparators 50a, 50b and 50c. , (G) and (h) are EOR circuits 9 and 1
The output of 1 and (i), (j), (k) and (l) indicate the inputs of the latch circuits 2a, 2b, 2c and 2d, respectively.

Further, the embodiment shown in FIG. 6 exemplifies a cascade A / D converter which outputs an alternating binary code (hereinafter referred to as Gray code).

Window comparators 50a and 50b
And 50c output "high level" when the input signal is near "0" and the output of the previous window comparator is "low level".

Therefore, the window comparator 50a
Is an analog input signal 100 as shown in FIG.
Outputs "high level" near "0".

As can be seen from FIG. 7B, the window comparator 50b has the analog input signal 100 of "".
There is a possibility of outputting "high level" in the vicinity of "0" and "± FS / 4", but when the analog input signal 100 is in the vicinity of "0", the output of the window comparator 50a in the previous stage is "high level". Therefore, as shown in (e) of FIG. 7, only the vicinity of "± FS / 4" becomes "high level".

Similarly, the window comparator 50c has a "high level" at seven places as can be seen from (c) in FIG.
However, since the "high level" portion of the window comparators 50a and 50b in the previous stage is excluded, the state becomes as shown in (f) in FIG.

The outputs of the EOR circuits 9 and 11 output the gray code of the intermediate bit of the digital output signal 101. In FIG. 7, "a", "b", "c" and "d".
It can be seen that spike-like noise is generated as shown in FIG. This is the "high level" of the output of the comparators 1a-1c.
It is caused by the gradual change from "low level" to "low level" or "high level".

Here, the error correction circuit 51 corrects the portion where the spike-like noise is generated by the output of the window comparator, so that the spike-like noise as shown in (j) and (k) of FIG. Remove the noise.

That is, the spike noises "a" and "c" in FIG. 7 are output from the window comparator 50a, while the spike noises "b" and "d" in FIG. It can be removed by masking each with the output of 50b.

The output of the window comparator 50c at the final stage ((f) in FIG. 7) can be directly output as the LSB of the digital output signal 100, as shown in (l) in FIG. The number of circuits can be reduced.

The window width of the window comparator may be set equal to "2LSB (ΔV = FS / 16)" only in the window comparator 50c at the final stage, and the window widths of the other window comparators are the same as those in the spike-like shape. If it is enough to mask noise, it does not need to be set strictly.

As a result, it becomes possible to operate all stages in one clock by detecting the code change of the cascade A / D converter with the window comparator and removing the noise generated at the code change point. , High speed operation.

However, in the conventional example shown in FIG. 6, the overall amplification degree of the signal path passing through the comparators, D / A converters, subtracters, etc. of the respective stages becomes extremely large at the code change,
In some cases, settling deteriorated, noise was generated, and it was difficult to ensure stability.

For example, FIG. 8 is a characteristic curve diagram showing input / output characteristics and the like of the comparators 1a to 1c. It is assumed that the analog input signal is a pulse signal that fluctuates near the threshold value of the comparator while ringing as shown by "a" in FIG.

The input / output characteristics of the comparator are shown in FIG.
Since the characteristics are as shown in "b", when an analog input signal as shown in "a" in FIG. 8 is applied, an output signal as shown in "c" in FIG. 8 is output.

The output signal indicated by "C" in FIG.
The ringing appears in the part "2", and this ringing continues to be amplified by passing through the D / A converter, the subtracter and the other comparators in the subsequent stage. Actually, the ringing exists until the analog input changes. As a result, noise may be generated or stable operation may be hindered.

In this case, it is improved by providing the comparator with a hysteresis characteristic. For example, FIG. 9 is a characteristic curve showing an input / output characteristic of a comparator having a hysteresis characteristic, and an analog input signal in FIG.
Assume a pulse signal similar to "a".

"I" in FIG. 9 is the input / output characteristic of the comparator having a hysteresis characteristic. Even if a pulse signal as shown in "B" in FIG. 9 is applied, the hysteresis characteristic causes a dead zone near the threshold. Therefore, the output signal is "C" in Fig. 9.
As shown in, the input ringing becomes a absorbed signal.

As a result, the settling characteristic is improved by providing the comparator with the hysteresis characteristic. Also,
If the width of this dead zone is made smaller than the window width of the window comparator, it does not affect the DC accuracy of A / D conversion.

[0032]

However, when the comparator is provided with a hysteresis characteristic, the input voltage which is the switching point of the output code is deviated, so that widening the hysteresis width deteriorates the A / D conversion accuracy. To do. On the contrary, if the hysteresis width is narrowed, the A / D conversion accuracy is good, but the settling characteristic is deteriorated, and noise is generated or the operation becomes unstable. Further, there is a problem that the propagation delay time of the comparator increases by adding a circuit having a hysteresis characteristic to the comparator. Therefore, the problem to be solved by the present invention is to realize a cascade A / D converter capable of improving the A / D conversion accuracy and the propagation delay time while maintaining the settling characteristic.

[0033]

In order to achieve the above object, the invention according to claim 1 of the present invention provides a comparator for converting an analog input signal into a digital signal and an output of this comparator. A latch circuit for holding, a D / A converter for converting the output of the comparator into an analog signal again, and a subtracter for subtracting the output of the D / A converter from the analog input signal are connected in cascade. In the cascade A / D converter configured as described above, a plurality of window comparators that detect a change in the code of the plurality of stages of comparators, and noise generated at the change point of the code based on the outputs of the window comparators are removed. an error correction circuit, and a transition state detector which detects the transition state of the comparator of said plurality of stages, places this transition state detector detects the transition state
Output a constant value of analog output when
In the case of, convert the digital input signal to an analog signal
The provision of the D / A converter for outputting as a signal makes it possible to improve the propagation delay time while maintaining the settling characteristic.

According to a second aspect of the present invention, in the cascade A / D converter according to the first aspect of the present invention, the transition state detector is constituted by a window comparator so that the propagation is performed while maintaining a settling characteristic. It becomes possible to improve the delay time.

According to a third aspect of the present invention, in the cascade A / D converter according to the first aspect of the invention, the D / A
The converter includes a differential circuit that outputs an analog signal based on the output of the comparator, and a current switch circuit that controls the operation of the differential circuit based on the output of the transition state detector. It is possible to improve the propagation delay time while maintaining.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit diagram showing a first stage portion of an embodiment of a cascade A / D converter according to the present invention. Since the basic structure is almost the same as the conventional example shown in FIG. 6, only different points will be described.

In FIG. 1, 4a, 5a, 5b, 6, 50
Reference numerals a and 100 are the same as those in FIG. 6, 14 is a normal comparator having no hysteresis characteristic, 15 is a D / A converter having an output switch function, 16 and 17 are comparators, and 18 is a NAND. Circuit. Further, reference numerals 16, 17 and 18 denote window comparators, which form a transition state detector 52.

The analog input signal 100 is input to the non-inverting input terminals of the comparators 14 and 5a, the inverting input terminal of the comparator 5b, and the addition input terminal of the subtractor 4a. The output of the comparator 14 is the latch circuit 2a (not shown) and the D / A converter 15.
Input terminal, one input terminal of the EOR circuit 9 (not shown), the inverting input terminal of the comparator 16 and the non-inverting input terminal of the comparator 17, and the output of the D / A converter 15 is a subtractor. 4a is connected to the subtraction input terminal.

The outputs of the comparators 5a and 5b are connected to the input terminals of the AND circuit 6, respectively, and the outputs of the comparators 16 and 17 are connected to the input terminals of the NAND circuit 18, respectively. Further, the output of the NAND circuit 18 is connected to the control input terminal of the D / A converter 15.

The inverting input terminal of the comparator 14 is grounded, the non-inverting input terminal of the comparator 5b is "+ ΔV", and the inverting input terminal of the comparator 5a is "-ΔV". Is applied. Further, the voltage of “+ Δv” is applied to the non-inverting input terminal of the comparator 16, and the voltage of “−Δv” is applied to the inverting input terminal of the comparator 17. However, “ΔV> Δv”.

The operation of the embodiment shown in FIG. 1 will now be described with reference to FIG.
This will be described with reference to FIGS. 3 and 4. 2 is a characteristic curve diagram showing the input / output characteristics of the comparator 14, FIG. 3 is a table for comparing delay times, and FIG. 4 is a table for explaining the operation of the transition state detector 52. However, since the basic operation is the same as that of the conventional example shown in FIG. 6, its explanation is omitted.

Further, the D / A converter 15 outputs an analog output when the control input terminal is "high level", and stops the output of the analog signal when the control input terminal is "low level". When the output of is stopped, specifically, the analog output starts from the voltage value immediately before the output is stopped.
It transitions to 0V "and stabilizes.

From FIG. 2, since the comparator 14 does not have the hysteresis characteristic, the A / D conversion accuracy is improved without causing the deviation of the switching of the output code. Further, since the comparator 14 does not have the hysteresis characteristic, the delay time of the circuit portion having the hysteresis characteristic shown in "A" of "DT01" in FIG. 3 which is the delay time of the conventional example is eliminated. In the embodiment shown in FIG. 3, the delay time becomes short as shown by "DT02" in FIG. In particular, the delay with respect to the analog circuit in the subsequent stage is reduced.

On the other hand, from FIG. 4, in the transition state detector 52, the output “Vo14” of the comparator 14 is “−Δv <Vo14 <+ Δ.
In the case of "v", the output becomes "low level" and "V
When o14 <−Δv ”or“ Vo14> + Δv ”, the output becomes“ high level ”.

That is, the output of the comparator 14 is "-Δv".
In the case of taking an intermediate value between "+" and "+ Δv" (transition state), the transition state detector 52 operates to disconnect the output of the D / A converter 15 as described above. Therefore, even when an analog input signal as shown in FIG. 8 is input to the comparator 14, the output of the comparison circuit 14 in the transition state shown in “e” in FIG. 8 is converted into an analog signal and output. Therefore, only the signal obtained by converting the signal in which the input ringing is absorbed into the analog signal is output from the D / A converter 15.

When the control input terminal of the D / A converter 15 becomes "low level", the analog output transits from the voltage value immediately before the output is stopped to "0V" and becomes stable, so that the transition state is recovered. In this case, the analog output of the D / A converter 15 makes a transition from "0V" to a predetermined analog value, so that the transition time is shortened.

As a result, the normal comparator 14 is used, and the transition state detector 52 for detecting the transition state of the output of the comparator 14 is provided. When the output of the comparator 14 is in the transition state, D
By separating the output of the / A converter, it is possible to improve the switching accuracy of the output code and the propagation delay time while maintaining the settling characteristic.

Further, the D / A converter 15 may have a configuration in which its output is "ON" or "OFF" by the "high level" and "low level" control signals from the transition detector 52. For example, FIG. 5 is a circuit diagram showing an example of such a D / A converter. In FIG. 5, 19 and 20 are resistors, 21, 22, 23 and 24 are transistors, and 25
Is a constant current source, 200 is a digital signal, 201 is a control signal, and 202 and 203 are differential analog signals.

Also, the resistors 19 and 20 and the transistor 2
1 and 22 form a differential circuit, and the transistors 23 and 24 and the constant current source 25 form a current switch circuit.

The digital signal 200 is supplied to the transistor 21.
The control signal 201 is connected to the base of
3 connected to the base. On the other hand, the threshold voltages “Vth1” and “Vth” are applied to the bases of the transistors 22 and 24, respectively.
2 "are connected to each other. Incidentally, the threshold voltage has an arbitrary voltage value between" high level "and" low level ".

The emitter of the transistor 21 is connected to the emitter of the transistor 22 and the collector of the transistor 23, and the emitter of the transistor 23 is the transistor 2
4 and an end of the constant current source 25.

The collectors of the transistors 21 and 22 are connected to one ends of the resistors 19 and 20, and the differential analog signals 202 and 203 are output from the connection points. Further, the other ends of the resistors 19 and 20, the transistor 2
The collectors of 4 are respectively connected to a positive voltage source, and the other end of the constant current source 25 is connected to a negative voltage source.

The operation of the D / A converter shown in FIG. 5 will be described. When the control signal 201 is "high level", the threshold voltage is higher than "Vth2", so the transistor 23 is "ON" and the transistor 24 is "OFF".
become.

When the digital signal 200 is "high level", the transistor 21 is "ON" and the transistor 22 is "OFF". Therefore, a current flows through the resistor 19 and a voltage drop occurs, and the potential corresponding to this voltage drop is output as the analog signal 202. Since no current flows through the resistor 20, the potential of the positive voltage source remains the same as the analog signal 20.
It is output as 3.

On the other hand, here, the digital signal 200 is "
If it is "low level", the transistor 21 will be "OFF" and the transistor 22 will be "ON".
Since no current flows through the analog signal 202, the potential of the positive voltage source is output as it is as the analog signal 202, and a current flows through the resistor 20 to cause a voltage drop.
It is output as 3. Therefore, if one of the analog signals is used as a reference, the digital signal 200 outputs positive and negative potentials corresponding to the voltage drop.

However, when the control signal 201 is "low level", it becomes smaller than the threshold voltage "Vth2", so that the transistor 23 is turned "OFF" and the transistor 24 is turned off.
Turns on. Therefore, the transistors 21 and 2
2 also becomes "OFF", and no current flows through the resistors 19 and 20, so the potential of the positive voltage source remains the analog signal 20.
Since it is output as 2 and 203, the difference is "0V"
become. In other words, it means that the D / A converter 15 is controlled by the control signal 201 and the output is stopped.

The voltages "+ Δv" and "-" applied to the respective comparators 16 and 17 constituting the transition state detector 52.
Regarding Δv ”, by setting“ ΔV> Δv ”with respect to the voltage“ ΔV ”applied to the window comparator 50a, the operation of the window comparator 50a is not affected.

[0058]

As is apparent from the above description,
The present invention has the following effects. According to the first to third aspects of the present invention, a normal comparator is used and a transition state detector for detecting the transition state of the output of the comparator is provided, and the D / A is used when the output of the comparator is in the transition state. By separating the output of the converter, it is possible to realize a cascade A / D converter that can improve the A / D conversion accuracy and the propagation delay time while maintaining the settling characteristic.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first stage portion of an embodiment of a cascade A / D converter according to the present invention.

FIG. 2 is a characteristic curve diagram showing input / output characteristics of a comparator.

FIG. 3 is a table comparing delay times.

FIG. 4 is a table illustrating the operation of the transition state detector.

FIG. 5 is a circuit diagram showing an example of a D / A converter.

FIG. 6 is a configuration block diagram showing an example of a conventional cascade A / D converter.

FIG. 7 is a characteristic curve diagram showing each output or each input with respect to an analog input signal.

FIG. 8 is a characteristic curve diagram showing input / output characteristics of a comparator.

FIG. 9 is an input / output characteristic of a comparator having a hysteresis characteristic.

[Explanation of symbols]

1a, 1b, 1c, 5a, 5b, 5c, 5d, 5e, 5
f, 14, 16, 17 Comparators 2a, 2b, 2c, 2d Latch circuits 3a, 3b, 15 D / A converters 4a, 4b Subtractors 6, 7, 8, 13 AND circuits 9, 11 EOR circuits 10, 12 OR circuit 18 NAND circuit 19, 20 Resistors 21, 22, 23, 24 Transistor 25 Constant current sources 50a, 50b, 50c Window comparator 51 Error correction circuit 52 Transition state detector 100 Analog input signal 101 Digital output signal 200 Digital signal 201 Control signal 202, 203 Analog signal

Continuation of the front page (56) References JP-A-6-252759 (JP, A) JP-A-9-238077 (JP, A) Actual Kaihei 6-77344 (JP, U) (58) Fields investigated (Int .Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (3)

(57) [Claims] 1. A comparator for converting an analog input signal into a digital signal, a latch circuit for holding the output of the comparator, and a D for converting the output of the comparator into an analog signal again.
A / A converter and a subtractor that subtracts the output of the D / A converter from the analog input signal in a cascade connection in a plurality of stages. A plurality of window comparators that detect code changes, an error correction circuit that removes noise generated at code change points based on the output of the window comparators, and a transition state that detects the transition states of the comparators at the plurality of stages. Detector and a constant value if this transition state detector detects a transition state
Output analog output of
A cascade A / D converter comprising the D / A converter for converting a digital input signal into an analog signal and outputting the analog signal . 2. The cascade A / D converter according to claim 1, wherein the transition state detector is composed of a window comparator. 3. A differential circuit in which the D / A converter outputs an analog signal based on the output of the comparator, and a current switch which controls the operation of the differential circuit based on the output of the transition state detector. The cascade A / D converter according to claim 1, wherein the cascade A / D converter comprises a circuit.