JPH11261419A - Cascade a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve D/A conversion and to enhance a propagation delay time while maintaining a settling characteristic by detecting a transition state of outputs of plural comparators and disconnecting an output of a D/A converter in the case of the transition state. SOLUTION: A D/A converter 15 provides an analog output when a control input terminal is at a high level and the D/A converter 15 stops its analog output when the input terminal is at a low level, then the D/A converter is set stable through transition from a just preceding voltage to 0 V. A comparator 14 has no hysteresis characteristic and A/D conversion accuracy is enhanced without causing a deviation in output code changeover and a delay time is shortened. When an output of the comparator 14 is in a transition state, a transition state detector 52 is operated to disconnect an output of the D/A converter 15. An output of the comparator 14 in the transition state is not converted into an analog signal, and only the analog conversion signal of a signal absorbing input ringing is outputted from the D/A converter 15. Furthermore, since an analog output of the D/A converter 15 recovered from the transition state transits from 0 to a prescribed analog value, the transition time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cascade A / D converter, and more particularly to a cascade A / D converter capable of improving a propagation delay time.

[0002]

2. Description of the Related Art As a conventional cascade A / D converter, there is a cascade A / D converter as described in Japanese Patent Application No. 08-322709 filed by the present applicant. FIG. 6 is a block diagram showing an example of a conventional cascade A / D converter described in Japanese Patent Application No. 08-322709.

In FIG. 6, 1a, 1b, 1c, 5a, 5
b, 5c, 5d, 5e and 5f are comparators, 2a, 2b,
2c and 2d are latch circuits, 3a and 3b are D / A converters, 4a and 4b are subtractors, 6, 7, 8 and 13 are AND circuits (hereinafter referred to as AND circuits), and 9 and 11 are exclusive. Logical OR circuits (hereinafter, referred to as EOR circuits), 10 and 12 are logical OR circuits (hereinafter, referred to as OR circuits), 10
0 is an analog input signal and 101 is a digital output signal.

Further, 5a, 5b and 6 are window comparators 50a, and 5c, 5d and 7 are window comparators.
Comparator 50b, 5e, 5f and 8 constitute window comparator 50c, and 10, 12 and 13 constitute error correction circuit 51, respectively.

The analog input signal 100 is input to the non-inverting input terminals of the comparators 1a and 5a, the inverting input terminal of the comparator 5b, and the addition input terminal of the subtractor 4a. The output of the comparator 1a is a latch circuit 2a, a D / A converter 3a, an EOR circuit 9
And the output of the D / A converter 3a is connected to the subtraction input terminal of the subtractor 4a.

The outputs of the comparators 5a and 5b are respectively connected to the input terminals of an AND circuit 6, and the output of the AND circuit 6 is one input terminal of the OR circuit 10, the negative logic input terminals of the AND circuits 7 and 13, Connected to one negative logic input terminal of AND circuit 8.

The output of the subtractor 4a is the non-inverting input terminal of the comparators 1b and 5c, the inverting input terminal of the comparator 5d,
b is connected to the addition input terminal. The output of the comparator 1b is D
/ A converter 3b, the other input terminal of EOR circuit 9, EO
The output of the D / A converter 3b is connected to one input terminal of the R circuit 11 and the subtraction input terminal of the subtractor 4b.

The outputs of the comparators 5c and 5d are respectively connected to the other two positive logic input terminals of the AND circuit 7, and the output of the AND circuit 7 is connected to one input terminal of the OR circuit 12 and the other of the AND circuit 8. Is connected to the negative logic input terminal. Further, the output of the EOR circuit 9 is connected to the other input terminal of the OR circuit 10, and the output of the OR circuit 10 is connected to the latch circuit 2b.

The output of the subtractor 4b is connected to the non-inverting input terminals of the comparators 1c and 5e and the inverting input terminal of the comparator 5f. The output of the comparator 1c is connected to the other input terminal of the EOR circuit 11, and the output of the EOR circuit 11 is connected to the other input terminal of the OR circuit 12. The output of the OR circuit 12 is A
The ND circuit 13 is connected to the positive logic input terminal, and the output of the AND circuit 13 is connected to the latch circuit 2c.

The outputs of the comparators 5e and 5f are connected to the other two positive logic input terminals of the AND circuit 8, and the output of the AND circuit 8 is connected to the latch circuit 2d. Further, outputs of the latch circuits 2a to 2d are output as digital output signals 101.

The inverting input terminals of the comparators 1a to 1c are grounded, the non-inverting input terminals of the comparators 5b, 5d and 5f receive the voltage of "+ ΔV", and the inverting input terminals of the comparators 5a, 5c and 5e. Is applied with a voltage of “−ΔV”. However, “ΔV = FS / 16”.

The operation of the embodiment shown in FIG. 6 will be described with reference to FIG. FIG. 7 shows the range from “−FS / 2” to “+ FS /
FIG. 6 is a characteristic curve diagram showing each output or each input with respect to the analog input signal 100 of “2”.

In FIG. 7, (a), (b) and (c) show the outputs of the comparators 1a, 1b and 1c, and (d), (e) and (f) show the outputs of the window comparators 50a, 50b and 50c. , (G) and (h) are EOR circuits 9 and 1
Outputs 1 (i), (j), (k), and (l) indicate inputs of the latch circuits 2a, 2b, 2c, and 2d, respectively.

The embodiment shown in FIG. 6 exemplifies a cascade A / D converter that outputs an alternating binary code (hereinafter, referred to as Gray Code).

Window comparators 50a and 50b
And 50c output "high level" when the input signal is near "0" and the output of the preceding window comparator is "low level".

Therefore, the window comparator 50a
Is the analog input signal 100 as shown in FIG.
Outputs a “high level” near “0”.

As can be seen from FIG. 7B, the window comparator 50b sets the analog input signal 100 to "".
There is a possibility of outputting “high level” near “0” and “± FS / 4”, but when the analog input signal 100 is near “0”, the output of the preceding window comparator 50a is “high level”. Therefore, only the vicinity of “± FS / 4” becomes “high level” as shown in FIG.

Similarly, as shown in FIG. 7C, the window comparator 50c has "high level" at seven locations.
However, since the high-level portions of the window comparators 50a and 50b at the preceding stage are excluded, the state becomes as shown in FIG. 7 (f).

The outputs of the EOR circuits 9 and 11 output gray codes of intermediate bits in the digital output signal 101. In FIG. 7, "A", "B", "C" and "D" are shown.
It can be seen that spike-like noise is generated as shown in FIG. This is the "high level" of the outputs of the comparators 1a-1c.
This is because the change from “low level” to “low level” or “low level” to “high level” is slow.

Here, the error correction circuit 51 corrects the portion where the spike-like noise is generated by the output of the window comparator, thereby obtaining the spike-like noise as shown in FIGS. 7 (j) and 7 (k). To eliminate noise.

That is, the spike-like noises "a" and "c" in FIG. 7 are output from the window comparator 50a, while the spike-like noises "b" and "d" in FIG. It can be removed by masking with the output of 50b.

The output of the final stage window comparator 50c ((f) in FIG. 7) can be directly output as the LSB of the digital output signal 100 as shown in (l) in FIG. Circuit can be reduced.

The window width of the window comparator may be set to be equal to "2 LSB (.DELTA.V = FS / 16)" only for the final stage window comparator 50c. If it is sufficient to mask noise, it is not necessary to set strictly.

As a result, the change in the code of the cascade A / D converter is detected by the window comparator, and the noise generated at the code change point is removed, whereby all stages can be operated with one clock. , High speed operation.

However, in the conventional example shown in FIG. 6, the overall amplification of the signal path passing through the comparator, D / A converter, subtractor, etc. of each stage becomes extremely large at the transition of the code.
In some cases, settling deteriorated, noise occurred, and it was difficult to ensure stability.

For example, FIG. 8 is a characteristic curve diagram showing input / output characteristics of the comparators 1a to 1c and the like. As the analog input signal, a pulse signal which fluctuates near the threshold value of the comparator while ringing as shown by "A" in FIG. 8 is assumed.

The input / output characteristics of the comparator are shown in FIG.
Since the characteristic is as shown in FIG. 8B, when an analog input signal as shown in FIG. 8A is applied, an output signal as shown in FIG. 8C is output.

The output signal indicated by "c" in FIG.
Ringing appears in the portion "d", and this ringing continues to be amplified by passing through a subsequent D / A converter, a subtractor, another comparator, etc. In fact, ringing exists until the analog input changes. As a result, there is a possibility that noise may be generated or a stable operation may be hindered.

In this case, it is improved by giving the comparator a hysteresis characteristic. For example, FIG. 9 is a characteristic curve showing input / output characteristics of a comparator having hysteresis characteristics.
It is assumed that the pulse signal is the same as in the case of "a".

In FIG. 9, "a" indicates the input / output characteristics of the comparator having the hysteresis characteristic. Even when a pulse signal as shown in "b" in FIG. 9 is applied, the vicinity of the threshold becomes dead zone due to the hysteresis characteristic. Therefore, the output signal is "C" in FIG.
As shown in (2), the input ringing is absorbed.

As a result, the settling characteristic is improved by giving the comparator a hysteresis characteristic. Also,
If the width of the dead zone is made smaller than the window width of the window comparator, there is no effect on the DC accuracy of the A / D conversion.

[0032]

However, when the comparator is provided with a hysteresis characteristic, the input voltage at which the output code switches is shifted, so that if the width of the hysteresis is widened, the A / D conversion accuracy deteriorates. I do. Conversely, when the width of the hysteresis is reduced, the A / D conversion accuracy is good, but the settling characteristics are deteriorated, noise is generated, and the operation becomes unstable. Furthermore, there is a problem that the propagation delay time of the comparator is increased by adding a circuit having a hysteresis characteristic to the comparator. Therefore, an object of the present invention is to realize a cascade A / D converter capable of improving A / D conversion accuracy and improving propagation delay time while maintaining settling characteristics.

[0033]

In order to achieve the above object, according to the first aspect of the present invention, a comparator for converting an analog input signal into a digital signal and an output of the comparator are provided. A latch circuit for holding, a D / A converter for converting the output of the comparator into an analog signal again, and a subtractor for subtracting the output of the D / A converter from the analog input signal are cascaded in a plurality of stages. And a plurality of window comparators for detecting a code change of the plurality of stages of comparators, and removing a noise generated at a code change point based on an output of the window comparator. An error correction circuit; a transition state detector for detecting transition states of the plurality of comparators; and the D / A converter for controlling an output based on an output of the transition state detector. By providing a vessel, it is possible to improve the propagation delay time while maintaining the settling characteristics.

According to a second aspect of the present invention, in the cascade A / D converter according to the first aspect of the present invention, the transition state detector is constituted by a window comparator so as to propagate the signal while maintaining the settling characteristic. The delay time can be improved.

According to a third aspect of the present invention, in the cascade A / D converter according to the first aspect of the present invention, the D / A
By setting the converter to include a differential circuit that outputs an analog signal based on the output of the comparator, and a current switch circuit that controls the operation of the differential circuit based on the output of the transition state detector, settling characteristics are obtained. , While improving the propagation delay time.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a first stage of an embodiment of a cascade A / D converter according to the present invention. Since the basic configuration is almost the same as the conventional example shown in FIG. 6, only the differences will be described.

In FIG. 1, 4a, 5a, 5b, 6, 50
Reference numerals a and 100 denote the same reference numerals as in FIG. 6, reference numeral 14 denotes a normal comparator having no hysteresis characteristic, 15 denotes a D / A converter having an output switch function, 16 and 17 denote comparators, and 18 denotes a NAND. Circuit. Reference numerals 16, 17 and 18 are window comparators, which constitute the transition state detector 52.

The analog input signal 100 is input to the non-inverting input terminals of the comparators 14 and 5a, the inverting input terminal of the comparator 5b, and the addition input terminal of the subtractor 4a. The output of the comparator 14 is a latch circuit 2a (not shown), a D / A converter 15
, One input terminal of the EOR circuit 9 (not shown), the inverting input terminal of the comparator 16, and the non-inverting input terminal of the comparator 17, and the output of the D / A converter 15 is a subtractor. 4a is connected to the subtraction input terminal.

The outputs of the comparators 5a and 5b are connected to input terminals of an AND circuit 6, and the outputs of the comparators 16 and 17 are connected to input terminals of a NAND circuit 18, respectively. Further, the output of the NAND circuit 18 is connected to the control input terminal of the D / A converter 15.

The inverting input terminal of the comparator 14 is grounded, the non-inverting input terminal of the comparator 5b receives a voltage of "+ .DELTA.V", and the inverting input terminal of the comparator 5a receives a voltage of "-.DELTA.V". Applied. Further, the voltage of “+ Δv” is applied to the non-inverting input terminal of the comparator 16, and the voltage of “−Δv” is applied to the inverting input terminal of the comparator 17. However, “ΔV> Δv”.

The operation of the embodiment shown in FIG. 1 will now be described with reference to FIG.
This will be described with reference to FIGS. 2 is a characteristic curve diagram showing input / output characteristics of the comparator 14, FIG. 3 is a table for comparing delay times, and FIG. 4 is a table for explaining the operation of the transition state detector 52. However, the basic operation is the same as that of the conventional example shown in FIG.

The D / A converter 15 outputs an analog output when the control input terminal is at a high level, and stops outputting an analog signal when the control input terminal is at a low level. When the output stops, the analog output starts from the voltage value immediately before the output stops.
The voltage changes to 0V "and stabilizes.

As shown in FIG. 2, since the comparator 14 does not have the hysteresis characteristic, the A / D conversion accuracy is improved without a shift in output code switching. Further, since the comparator 14 does not have the hysteresis characteristic, the delay time of the circuit portion having the hysteresis characteristic indicated by "A" in "DT01" in FIG. 3, which is the delay time of the conventional example, is eliminated. In the embodiment shown in FIG. 3, the delay time is shortened as indicated by "DT02" in FIG. In particular, the delay for the subsequent analog circuit is reduced.

On the other hand, from FIG. 4, the transition state detector 52 determines that the output "Vo14" of the comparator 14 is "-.DELTA.v <Vo14 <+. DELTA.
v ", its output goes to" low level "and" V
In the case of o14 <−Δv ”or“ Vo14> + Δv ”, the output becomes“ high level ”.

That is, the output of the comparator 14 is "-.DELTA.v".
When a transition value between "+ .DELTA.v" and "+ .DELTA.v" is taken (transition state), the transition state detector 52 operates to disconnect the output of the D / A converter 15 as described above. Therefore, even when an analog input signal as shown in FIG. 8 is input to the comparator 14, the output of the comparison circuit 14 in the transition state shown by "e" in FIG. Therefore, only the signal obtained by converting the signal in which the ringing of the input has been absorbed into an analog signal is output from the D / A converter 15.

When the control input terminal of the D / A converter 15 becomes "low level", the analog output transitions from the voltage value immediately before the output is stopped to "0 V" and becomes stable, so that the analog output recovers from the transition state. In this case, the analog output of the D / A converter 15 transitions from "0 V" to a predetermined analog value, so that the transition time is shortened.

As a result, a transition state detector 52 for detecting the transition state of the output of the comparator 14 is provided by using the ordinary comparator 14 and D is set when the output of the comparator 14 is in the transition state.
By separating the output of the / A converter, it is possible to improve the switching accuracy of the output code and to improve the propagation delay time while maintaining the settling characteristics.

The D / A converter 15 may have any configuration as long as its output is turned "ON" and "OFF" by "high level" and "low level" control signals from the transition detector 52. For example, FIG. 5 is a circuit diagram showing an example of such a D / A converter. In FIG. 5, 19 and 20 are resistors, 21, 22, 23 and 24 are transistors, 25
Is a constant current source, 200 is a digital signal, 201 is a control signal, and 202 and 203 are differential analog signals.

The resistors 19 and 20 and the transistor 2
1 and 22 constitute a differential circuit, and the transistors 23 and 24 and the constant current source 25 constitute a current switch circuit.

The digital signal 200 is output from the transistor 21
The control signal 201 is connected to the transistor 2
3 base. On the other hand, the threshold voltages “Vth1” and “Vth”
2 are respectively connected. Incidentally, the threshold voltage is an arbitrary voltage value between “high level” and “low level”.

The emitter of the transistor 21 is connected to the emitter of the transistor 22 and the collector of the transistor 23, and the emitter of the transistor 23 is connected to the transistor 2
4 and one end of a constant current source 25.

The collectors of the transistors 21 and 22 are connected to one ends of the resistors 19 and 20, and output differential analog signals 202 and 203 from the connection point. Further, the other ends of the resistors 19 and 20, the transistor 2
4 are connected to a positive voltage source, respectively, and the other end of the constant current source 25 is connected to a negative voltage source.

Here, the operation of the D / A converter shown in FIG. 5 will be described. When the control signal 201 is at “high level”, the voltage becomes larger than the threshold voltage “Vth2”, so that the transistor 23 is turned “ON” and the transistor 24 is “OFF”.
become.

Here, if the digital signal 200 is "high level", the transistor 21 is turned "ON" and the transistor 22 is turned "OFF". As a result, a current flows through the resistor 19 to cause a voltage drop, and the potential corresponding to the voltage drop is output as an analog signal 202. Since no current flows through the resistor 20, the potential of the positive voltage source remains unchanged.
It is output as 3.

On the other hand, here, the digital signal 200 is "
If the level is low, the transistor 21 is turned off and the transistor 22 is turned on.
Since no current flows through the resistor 20, the potential of the positive voltage source is output as it is as an analog signal 202, and a current flows through the resistor 20 to cause a voltage drop.
It is output as 3. Therefore, if one analog signal is used as a reference, the digital signal 200 outputs a positive or negative potential corresponding to the voltage drop.

However, if the control signal 201 is at "low level", it becomes smaller than the threshold voltage "Vth2", so that the transistor 23 is turned "OFF" and the transistor 24 is turned off.
Becomes "ON". Therefore, transistors 21 and 2
2 is also "OFF" and no current flows through the resistors 19 and 20, so that the potential of the positive voltage source remains
2 and 203, the difference is “0V”
become. In other words, it means that the D / A converter 15 is controlled by the control signal 201 and the output is stopped.

The voltages “+ Δv” and “−” applied to each of the comparators 16 and 17 constituting the transition state detector 52
Regarding Δv ”, the operation of the window comparator 50a is not affected by setting“ ΔV> Δv ”to“ ΔV ”which is a voltage applied to the window comparator 50a.

[0058]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. According to the first to third aspects of the present invention, a normal comparator is used and a transition state detector for detecting a transition state of the output of the comparator is provided. By separating the output of the converter, a cascade A / D converter capable of improving A / D conversion accuracy and improving propagation delay time while maintaining settling characteristics can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first stage of an embodiment of a cascade A / D converter according to the present invention.

FIG. 2 is a characteristic curve diagram showing input / output characteristics of a comparator.

FIG. 3 is a table comparing delay times.

FIG. 4 is a table illustrating an operation of the transition state detector.

FIG. 5 is a circuit diagram illustrating an example of a D / A converter.

FIG. 6 is a configuration block diagram illustrating an example of a conventional cascade A / D converter.

FIG. 7 is a characteristic curve diagram showing each output or each input with respect to an analog input signal.

FIG. 8 is a characteristic curve diagram showing input / output characteristics of the comparator.

FIG. 9 shows input / output characteristics of a comparator having hysteresis characteristics.

[Explanation of symbols]

1a, 1b, 1c, 5a, 5b, 5c, 5d, 5e, 5
f, 14, 16, 17 Comparators 2a, 2b, 2c, 2d Latch circuits 3a, 3b, 15 D / A converters 4a, 4b Subtractors 6, 7, 8, 13 AND circuits 9, 11 EOR circuits 10, 12 OR circuit 18 NAND circuit 19, 20 Resistance 21, 22, 23, 24 Transistor 25 Constant current source 50a, 50b, 50c Window comparator 51 Error correction circuit 52 Transition state detector 100 Analog input signal 101 Digital output signal 200 Digital signal 201 Control signal 202, 203 Analog signal

Claims (3)

[Claims] A comparator for converting an analog input signal into a digital signal; a latch circuit for holding an output of the comparator; and a D for converting an output of the comparator into an analog signal again.
/ A converter and a subtractor for subtracting the output of the D / A converter from the analog input signal in a cascade of a plurality of stages. A plurality of window comparators for detecting a code change; an error correction circuit for removing noise generated at a code change point based on an output of the window comparator; and a transition state for detecting a transition state of the plurality of comparators A cascade A comprising: a detector; and the D / A converter for controlling an output based on an output of the transition state detector.
/ D converter. 2. The cascade A / D converter according to claim 1, wherein said transition state detector comprises a window comparator. 3. A differential circuit, wherein the D / A converter outputs an analog signal based on an output of the comparator, and a current switch which controls an operation of the differential circuit based on an output of the transition state detector. 2. The cascade A / D converter according to claim 1, further comprising a circuit.