JP3353626B2 - Cascade A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cascade A / D converter, and more particularly to a cascade A / D converter capable of operating at high speed.

[0002]

2. Description of the Related Art As a conventional A / D converter capable of high-speed operation, there is an all-parallel A / D converter or a serial-parallel A / D converter.

FIG. 13 is a configuration block diagram showing an example of such a conventional A / D converter. 13A shows an all-parallel A / D converter, and FIG. 13B shows a serial-parallel A / D converter.
/ D converters are shown.

In FIG. 13A, reference numeral 1 denotes a resistor array;
Is a comparator, 3 is an encoder, 100 is an analog input signal, and 101 is a digital output signal.

[0005] A reference voltage is applied to one end of the resistor array 1, and the other end of the resistor array 1 is grounded. The voltage between the taps of the resistor array 1 is connected to the inverting input terminals of the plurality of comparators 2, respectively, and the analog input signal 100 is input to the non-inverting input terminals of the plurality of comparators 2.

The outputs of the plurality of comparators 2 are respectively connected to an encoder 3, and the output of the encoder 3 is output as a digital output signal 101.

On the other hand, in FIG. 13B, 4 and 7 are parallel A / D converters, 5 is a D / A converter, 6 is a subtractor, 1
00a is an analog input signal, and 101a and 101b are digital output signals.

The analog input signal 100a is a parallel A / D
The signals are input to the addition input terminals of the converter 4 and the subtractor 6, respectively, and the output of the parallel A / D converter 4 is output as the higher-order digital output signal 101a and the D / A converter 5
Connected to.

The output of the D / A converter 5 is connected to a subtraction input terminal of a subtractor 6, and the output of the subtracter 6 is connected to a parallel A / D converter 7. The parallel A / D converter 7 outputs a lower digital output signal 101b.

Now, the operation of the conventional example shown in FIGS. 13A and 13B will be described. However, since both are typical A / D converters, they will be briefly described.

In FIG. 13A, a reference voltage is divided into a plurality of reference voltages by a resistor array 1, and an analog input signal 100 is compared with the plurality of reference voltages by a plurality of comparators 2, respectively. The encoder 3 encodes the outputs of the plurality of comparators 2 to generate a digital output signal 10.
Outputs 1.

As a result, the analog input signal 100 is compared and encoded by the plurality of comparators 2 at the same time, so that high-speed operation becomes possible.

On the other hand, in FIG. 13B, the analog input signal 100a is converted into a higher-order digital output signal 101a by the parallel A / D converter 4 and output.

At this time, the D / A converter 5 converts the higher-order digital output signal 101a into an analog signal again,
The subtractor 6 subtracts a higher-order component from the analog input signal 100a.

Further, the analog signal from which the higher-order component has been subtracted is converted into a lower-order digital output signal 101b by the parallel A / D converter 7 and output.

As a result, the upper digital output signal 10
By separately converting 1a and the lower digital output signal 101b, the circuit scale of the parallel A / D converters 4 and 7 can be reduced.

However, the two conventional examples still have a problem that the circuit scale, power consumption, and input capacity are large.

On the other hand, there is a cascade A / D converter as an A / D converter having a small circuit scale, low power consumption and low input capacity. FIG. 14 and FIG. 15 are a circuit diagram and a timing diagram showing an example of such a cascade A / D converter. Here, a 4-bit A / D converter is illustrated for simplicity.

In FIG. 14A, 8a, 8b, 8c and 8d are comparators, 9a, 9b, 9c and 9d are latch circuits, 10a, 10b and 10c are D / A converters, 11a
a, 11b and 11c are subtractors, 100b is an analog input signal, and 101c is a digital output signal.

The analog input signal 100b is input to the non-inverting input terminal of the comparator 8a and the addition input terminal of the subtractor 11a, and the output of the comparator 8a is connected to the latch circuit 9a.

The output of the latch circuit 9a is output as the MSB of the digital output signal 101c and is connected to the D / A converter 10a. The output of the D / A converter 10a is connected to the subtraction input terminal of the subtractor 11a.

The output of the subtractor 11a is connected to the non-inverting input terminal of the comparator 8b and the addition input terminal of the subtractor 11b.
The output of the comparator 8b is connected to the latch circuit 9b.

The output of the latch circuit 9b is output as a digital output signal 101c and the D / A converter 10b
Connected to. The output of the D / A converter 10b is a subtractor 11
b is connected to the subtraction input terminal.

The output of the subtractor 11b is connected to the non-inverting input terminal of the comparator 8c and the addition input terminal of the subtractor 11c.
The output of the comparator 8c is connected to the latch circuit 9c.

The output of the latch circuit 9c is output as a digital output signal 101c and a D / A converter 10c.
Connected to. The output of the D / A converter 10c is a subtractor 11
c is connected to the subtraction input terminal.

The output of the subtractor 11c is connected to the non-inverting input terminal of the comparator 8d, and the output of the comparator 8d is
d. The output of the latch circuit 9d is output as the LSB of the digital output signal 101c. Further, the inverting input terminals of the comparators 8a, 8b, 8c and 8d are grounded.

Here, the operation of the conventional example shown in FIG. 14A will be described with reference to FIG. In FIG. 14B, (a), (b), (c) and (d) show the latch circuit 9.
The latch clocks a, 9b, 9c and 9d are shown, and the latch operation is performed at "high level".

The comparator 8a determines the zero crossing of the analog input signal 100b, and its output is latched by the latch circuit 9a at the "high level" timing shown in FIG.

When the output of the comparator 8a is latched, the D / A converter 10a converts the output to an analog signal again,
The value of the upper bits is subtracted by the subtractor 11a.

Similarly, at each stage, the outputs of the comparators 8b to 8d are latched at the "high level" timing shown in FIG.
Can be obtained.

As a result, the digital signal is converted into a digital signal "1 bit" at each stage, resulting in a small circuit scale, low power consumption, and low input capacitance.

On the other hand, in FIG.
b and 12c are sample and hold circuits, 100c is an analog input signal, and 101d is a digital output signal.
Also, 8a to 8d, 9a to 9d, 10a to 10c, 11
Reference numerals a to 11c denote the same parts as in FIG.

The connection relationship is almost the same as that of FIG. 14A, except for the subtraction circuits 11a, 11b and 11b.
The point is that the sample and hold circuits 12a, 12b and 12c are provided in the output stage of c.

The operation of the conventional example shown in FIG. 15A is basically the same as that of FIG. 14A, except that the latch operation of the latch circuits 9a to 9c is performed as shown in FIG. The point is that the outputs of the sample-and-hold circuits 12a to 12c are subsequently held at the "high level" timings of (b), (d) and (f) in FIG.

The effects are the same as those of the conventional example shown in FIG. 14A, and the circuit size, power consumption, and input capacity are small.

[0036]

However, in the conventional example shown in FIG. 14, since the conversion of the next bit is performed after the conversion result of the upper bit is determined, the number of bits is changed as shown in FIG. However, there is a problem that the time for the A / D conversion increases in proportion to.

Also, by providing a sample-and-hold circuit for each stage and performing a pipeline operation as in the conventional example shown in FIG. 15, the A / D conversion time is reduced as shown in FIG.
(B) Although it is shortened as indicated by "a" in the middle, there is a problem that a large number of sample and hold circuits with large power consumption and circuit scale are required, and the circuit scale is large and power consumption is large. .

On the other hand, when the cascade A / D converter is operated by one clock, the operation becomes high speed, but there is a problem that an error occurs.

Here, the reason why an error occurs when the cascade A / D converter is operated in one clock will be described.

FIG. 16 is a circuit diagram when the cascade A / D converter is operated by one clock. In FIG. 16, 1
00d is an analog input signal, and 101e is a digital output signal.

The other reference numerals are the same as those in FIG. 14 (A), and the connection relation is the same except that the outputs of the comparators 8a to 8c are directly connected to the D / A converters 10a to 10c. 14 (A).

Here, the operation of the conventional example shown in FIG.
7 will be described. FIG. 17 is a characteristic curve diagram showing the operation of the conventional example shown in FIG.

In FIG. 17, the horizontal axis indicates the level of the input analog input signal 100d, and indicates the input level from "-FS / 2" to "+ FS / 2". here,
“FS” indicates the full scale of the cascade A / D converter.

(A) is the output of the comparator 8a, (b) is the D /
The output of the A converter 10a, (c) is the output of the subtractor 11a,
(D) is the output of the comparator 8b, (e) is the output of the comparator 8c, (f) is the output of the comparator 8d, and (g) is the digital output signal 101e.

In the case of operating with one clock, for example, since the output of the comparator 8a is directly used as the input of the D / A converter 10a, the code is affected by the finite gain of the comparator 8a and the D / A converter 10a. Does not change abruptly, and its influence extends to the subsequent stage via the subtractor 11a.

That is, as shown by "A" in FIG. 17, the output of the subtractor 11a changes slowly when the level of the analog input signal 100d is "0". The effect is, for example, as shown in FIG.
At the point where 00e changes from “0001” to “0010”, the values of (e) and (f) in FIG. 17 become incomplete values, and values such as “0011” and “0000” are output. Error in some cases. Therefore, an object of the present invention is to realize a cascade A / D converter that can operate without errors in one clock.

[0047]

According to a first aspect of the present invention, there is provided a comparator for converting an analog input signal into a digital signal, a latch circuit for holding an output of the comparator. , A D / A converter for converting the output of the comparator into an analog signal again, and a subtractor for subtracting the output of the D / A converter from the analog input signal in a plurality of cascades. The A / D converter includes a plurality of window comparators for detecting a change in code of the plurality of stages of comparators, and an error correction circuit for removing noise generated at a code change point based on the output of the window comparator. It is characterized by having.

In order to achieve such a task,
According to a second aspect of the present invention, a comparator for converting an analog input signal to a digital signal, a latch circuit for holding the output of the comparator, and a D / A converter for converting the output of the comparator to an analog signal again are provided. A cascade A / D converter constructed by cascading a plurality of stages of a subtractor for subtracting the output of the D / A converter from the analog input signal, and detecting a change in code of the plurality of comparators A plurality of window comparators, a delay means for delaying an output of the window comparator, and an error correction circuit for removing noise generated at a code change point based on the output of the window comparator or the delay means. It is characterized by having.

In order to achieve such a task,
According to a third aspect of the invention, in the first or second aspect of the invention, the comparator is provided with a hysteresis characteristic.

[0050]

By detecting a change in the code of the cascade A / D converter with a window comparator and removing noise generated at the point where the code changes, it becomes possible to operate all stages with one clock, thereby achieving high-speed operation. Becomes

Further, since the circuit operates with a circuit configuration one stage smaller than that of the conventional cascade A / D converter, higher speed operation is possible.

[0052]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of a cascade A / D converter according to the present invention. Here, for simplicity, 4
2 illustrates a bit A / D converter.

In FIG. 1, 13a, 13b, 13c, 1
3d, 13e and 13f are comparators, and 14, 15, 16 and 21 are AND circuits (hereinafter referred to as AND circuits), 1
7 and 19 are exclusive OR circuits (hereinafter referred to as EOR circuits), 18 and 20 are OR circuits (hereinafter referred to as OR circuits), 100e is an analog input signal, and 101f is a digital output signal.

Also, 8a to 8c, 9a to 9d, 10a,
Reference numerals 10b, 11a and 11b denote the same reference numerals as in FIG. 14, 13a, 13b and 14 denote window comparators 50a, and 13c, 13d and 15 denote window comparators.
Comparator 50b, 13e, 13f and 16 constitute a window comparator 50c, and 18, 20 and 21 constitute an error correction circuit 51, respectively.

The analog input signal 100e is input to the non-inverting input terminals of the comparators 8a and 13a, the inverting input terminal of the comparator 13b, and the addition input terminal of the subtractor 11a.

The output of the comparator 8a is supplied to the latch circuit 9a, D /
The A converter 10a is connected to one input terminal of the EOR circuit 17, and the output of the D / A converter 10a is connected to the subtraction input terminal of the subtractor 11a.

The outputs of the comparators 13a and 13b are respectively connected to the input terminals of an AND circuit 14, and the output of the AND circuit 14 is connected to one input terminal of an OR circuit 18, and
The negative logic input terminals of the circuits 15 and 21 and one negative logic input terminal of the AND circuit 16 are connected.

The output of the subtractor 11a is supplied to comparators 8b and 13
c, the inverting input terminal of the comparator 13d, and the addition input terminal of the subtractor 11b.

The output of the comparator 8b is a D / A converter 10b,
The other input terminal of the EOR circuit 17 is connected to one input terminal of the EOR circuit 19, and the output of the D / A converter 10b is connected to the subtraction input terminal of the subtractor 11b.

The outputs of the comparators 13c and 13d are respectively connected to the other two positive logic input terminals of the AND circuit 15, and the output of the AND circuit 15 is connected to one input terminal of the OR circuit 20 and the other of the AND circuit 16. Is connected to the negative logic input terminal.

Further, the output of the EOR circuit 17 is connected to the other input terminal of the OR circuit 18, and the output of the OR circuit 18 is connected to the latch circuit 9b.

The output of the subtractor 11b is supplied to comparators 8c and 13
e and the non-inverting input terminal of the comparator 13f.

The output of the comparator 8c is connected to the other input terminal of the EOR circuit 19, and the output of the EOR circuit 19 is connected to the other input terminal of the OR circuit 20. The output of the OR circuit 20 is connected to the positive logic input terminal of the AND circuit 21,
The output of ND circuit 21 is connected to latch circuit 9c.

The outputs of the comparators 13e and 13f are connected to the other two positive logic input terminals of the AND circuit 16, and the output of the AND circuit 16 is connected to the latch circuit 9d.

The outputs of the latch circuits 9a to 9d are output as digital output signals 101f.

The inverting input terminals of the comparators 8a to 8c are grounded, and the non-inverting input terminals of the comparators 13b, 13d and 13f receive the voltage of "+ .DELTA.V".
And 13e are applied with a voltage of “−ΔV”, respectively. However, “ΔV = FS / 16”.

The operation of the embodiment shown in FIG. 1 will now be described with reference to FIG. FIG. 2 shows the range from “−FS / 2” to “+ FS /
FIG. 14 is a characteristic curve diagram showing each output or each input with respect to the analog input signal 100e of “2”.

In FIG. 2, (a), (b) and (c) show outputs of comparators 8a, 8b and 8c, and (d), (e) and (f) show outputs of window comparators 50a, 50b and 50c. , (G) and (h) show the outputs of the EOR circuits 17 and 19, and (i), (j), (k) and (l) show the inputs of the latch circuits 9a, 9b, 9c and 9d, respectively.

Further, the embodiment shown in FIG. 1 exemplifies a cascade A / D converter which outputs an alternating binary code (hereinafter referred to as a Gray code).

The operation of comparators 8a, 8b and 8c is shown in FIG.
2 (a), (b) and (c) in FIG.
Are the same as (a), (d) and (e) in FIG.

Window comparators 50a, 50b
And 50c output "high level" when the input signal is near "0" and the output of the preceding window comparator is "low level".

Therefore, the window comparator 50a
Is the analog input signal 100e as shown in FIG.
Outputs a “high level” near “0”.

As can be seen from FIG. 2B, the window comparator 50b sets the analog input signal 100e to "
There is a possibility that a “high level” is output near “0” and “± FS / 4”, but the analog input signal 100 e is “0”.
In the vicinity, the preceding window comparator 50a
Is at the "high level", only the vicinity of ". ± .FS / 4" becomes the "high level" as shown in FIG.

Similarly, the window comparator 10c has "high level" at seven locations as can be seen from FIG.
However, since the high-level portions of the window comparators 10a and 10b at the preceding stage are excluded, the state becomes as shown in FIG. 2 (f).

The outputs of the EOR circuits 17 and 19 output a gray code of an intermediate bit in the digital output signal 101f, and are "A", "B", "C" and "B" in FIG.
It can be seen that spike-like noise is generated as shown in (d). This is from "high level" to "low level" or "low level" of the outputs of the comparators 8a to 8c.
This is due to the slowing down of "high-level" changes.

Here, the error correction circuit 51 corrects the portion where the spike-like noise is generated by the output of the window comparator, thereby obtaining the spike-like noise as shown in (j) and (k) in FIG. To eliminate noise.

That is, the spike-like noises "a" and "c" in FIG. 2 are output from the window comparator 50a, while the spike-like noises "b" and "d" in FIG. It can be removed by masking with the output of 50b.

The output ((f) in FIG. 2) of the final stage window comparator 50c can be directly output as the LSB of the digital output signal 100f as shown in (l) in FIG. Circuit can be reduced.

The window width of the window comparator may be set equal to "2 LSB (.DELTA.V = FS / 16)" only for the final stage window comparator 50c. If it is sufficient to mask noise, it is not necessary to set strictly.

As a result, a change in the code of the cascade A / D converter is detected by the window comparator, and noise generated at the code change point is removed, whereby all stages can be operated with one clock. , High speed operation.

Further, since the circuit operates with a circuit configuration one stage smaller than that of the conventional cascade A / D converter, higher speed operation is possible.

In other words, high-speed operation comparable to an all-parallel A / D converter becomes possible with a circuit scale, power consumption and input capacity comparable to those of a normal cascade A / D converter.

In the embodiment shown in FIG. 1, a cascade A / D converter for outputting a gray code is exemplified.
Of course, it is also possible to output a normal binary code (hereinafter, referred to as a binary code).

FIG. 3 is a circuit diagram showing an embodiment of a cascade A / D converter for outputting such a binary code.

In FIG. 3, reference numeral 8e denotes a comparator, 22a and 22a.
b, 22c, 22d, 22e, 22f and 22g are latch circuits, and 23a, 23b, 23c, 23d and 24 are A
ND circuits, 25, 26 and 27 are OR circuits, 100f is an analog input signal, and 101g is a digital output signal.

Here, 8a to 8c, 10a, 10b, 1
1a, 11b, 13a to 13f, 14 to 16 and 50a
To 50c are assigned the same reference numerals as in FIG.
d and 24 to 27 constitute an error correction circuit 52.

Regarding the connection relation, the basic parts are the same, and the different points are as follows. Analog input signal 1
00f is input to the non-inverting input terminal of the comparator 8e, and the output of the comparator 8e is connected to the latch circuit 22g. Also,
The inverting input terminal of the comparator 8e has "7/8. (FS /
2) "voltage is applied.

The outputs of the comparators 8a, 8b and 8c are connected to latch circuits 22a, 22c and 22e, respectively, and the outputs of the window comparators 50a, 50b and 50c are connected to latch circuits 22b, 22d and 22f.

The inverted output of the latch circuit 22a is connected to one input terminal of the AND circuit 23a.

The output of the latch circuit 22b is
a, and the inverted output of the latch circuit 22b is connected to one input terminal of the AND circuit 23b and AND
It is connected to the first input terminal of the circuit 24.

The output of the latch circuit 22c is
b, and the inverted output of the latch circuit 22c is connected to one input terminal of the AND circuit 23c.

The output of the latch circuit 22d is output to the AND circuit 23.
c, and the inverted output of the latch circuit 22d is connected to the second input terminal of the AND circuit 24.

The output of the latch circuit 22e is the AND circuit 24
And the inverted output of the latch circuit 22e is connected to one input terminal of an AND circuit 23d.

The output of the latch circuit 22f is the AND circuit 23
The output of the latch circuit 22g is connected to the fourth input terminal of the OR circuit 27.

The output of the AND circuit 23a is connected to one input terminal of the OR circuit 25, the first input terminal of the OR circuit 26, and O
Each is connected to a first input terminal of the R circuit 27.

The output of the AND circuit 23b is connected to the other input terminal of the OR circuit 25, and the output of the AND circuit 23c is connected to the second input terminal of the OR circuit 26 and the second input terminal of the OR circuit 27.
Is connected to the input terminal.

The output of the AND circuit 24 is connected to the third input terminal of the OR circuit 26, and the output of the AND circuit 23d is
Connected to the third input terminal of R circuit 27.

Further, the output of the latch circuit 22a and the outputs of the OR circuits 25 to 27 correspond to the M of the digital output signal 101g.
It is output as SB to LSB.

The operation of the embodiment shown in FIG. 3 will now be described with reference to FIGS. FIGS. 4 and 5 show “−FS /
FIG. 11 is a characteristic curve diagram showing each output or each input with respect to the analog input signal 100f from “2” to “+ FS / 2”.

In FIG. 4, (a), (b), (c),
(D), (e), (f) and (g) show the latch circuit 22.
a, 22c, 22e, 22g, 22b, 22d and 22
f is input.

In FIG. 5, (a), (b), (c),
(D) and (e) are AND circuits 23a, 23b, 23
Outputs of c, 24 and 23d, (f), (g), (h) and (i) are outputs of the latch circuit 22a and the OR circuits 25, 26 and 27.

Since the characteristics other than (d) in FIG. 4 are the same as those shown in FIG. 2, the description is omitted. Since the voltage of “7/8 · (FS / 2)” is applied to the inverting input terminal of the comparator 8e, the analog input signal 1 is output as shown in FIG.
It becomes “high level” only when 00f exceeds “7/8 · (FS / 2)”.

In FIG. 5, (a) shows the latch circuit 2
The logical product of the inverted output of 2a and the output of latch circuit 22b,
(B) is obtained by obtaining the logical product of the output of the latch circuit 22c and the inverted output of the latch circuit 22b, and (c) is obtained by obtaining the logical product of the inverted output of the latch circuit 22c and the output of the latch circuit 22d.

Similarly, (d) shows the logical product of the output of the latch circuit 22e and the inverted outputs of the latch circuits 22b and 22d.
(E) shows the inverted output of the latch circuit 22e and the latch circuit 22;
It is obtained by calculating the logical product of the output of f and the output of f.

In FIG. 5, (f) shows the output of the latch circuit 22a, (g) shows the logical sum of the outputs of the AND circuits 23a and 23b, (h) shows the logical sum of the outputs of the AND circuits 23a, 23c and 24, (I) AND circuits 23a and 23
It is obtained by calculating the logical sum of the outputs of c, 23d and the latch circuit 22g.

Here, (f) to (i) in FIG. 5 indicate the digital output signal 101g, and it can be seen from FIG. 5 that the output is a binary code.

As a result, a cascade A / D converter with a binary code output that can be operated with one clock can be realized.

The error correction circuit may be provided before or after the latch circuit, as can be seen from the embodiments of FIGS.

In each of the above-described conventional examples, the resolution of each stage is made to correspond to one bit at a time. However, the present invention is not limited to this, and it is also possible to perform processing with the resolution of each stage being two bits or more. .

FIG. 6 is a circuit diagram showing an example in which the embodiment shown in FIG. 1 has a 5-bit configuration. In FIG.
8c, 9a to 9c, 10a, 10b, 11a, 11b,
13a to 13f, 14 to 21 and 50a to 50c are shown in FIG.
8f, 13g and 13h are comparators, 10d is a D / A converter, 11d is a subtractor, 28 and 31 are AND circuits, 29 is an EOR circuit, 30 is an OR circuit, and 100g is An analog input signal 101h is a digital output signal.

Further, reference numerals 13g, 13h and 28 denote window comparators 50d and 18, 20, 21, 30 respectively.
And 31 constitute an error correction circuit 53, respectively.

The connection relationship is basically the same as that of FIG. 1 and the differences are as follows. The output of the subtractor 11b is connected to the addition input terminal of the subtractor 11d, and the comparator 8c
Is connected to the input terminal of the D / A converter 10d,
The output of the / A converter 10d is connected to the subtraction input terminal of the subtractor 11d.

The output of the subtractor 11d is supplied to the comparators 8f and 13
g is connected to the non-inverting input terminal of the comparator 13h and the output of the comparator 8f is connected to one input terminal of the EOR circuit 29. The output of the comparator 8c is connected to the other input terminal of the EOR circuit 29.

The output of EOR circuit 29 is connected to one input terminal of OR circuit 30, and the output of OR circuit 30 is AND
Connected to the input terminal of the circuit 31. Also, the AND circuit 3
The output of 1 is connected to the input terminal of the latch circuit 9e.

The other input terminal of the OR circuit 30 has AND
The output of the circuit 16 is connected to the outputs of the AND circuits 14 and 15 to two negative logic input terminals of the AND circuit 31 respectively.

Outputs of the comparators 13g and 13h are respectively connected to two input terminals of an AND circuit 28, and three negative logic input terminals of the AND circuit 28 are connected to the AND circuits 14, 1 respectively.
The outputs of 5 and 16 are respectively connected. Also, AND
The output of the circuit 28 is connected to the input terminal of the latch circuit 9f.

The inverting input terminal of the comparator 8f is grounded, the non-inverting input terminal of the comparator 13h receives a voltage of “+ ΔV”, and the inverting input terminal of the comparator 13g receives a voltage of “−ΔV”. Applied.

Since the basic operation of the circuit shown in FIG. 6 is the same as that of the embodiment shown in FIG. 1, the description of the basic operation will be omitted.

FIG. 7 is a table showing differences in signal paths depending on the level of the analog input signal 100g in the circuit shown in FIG. Incidentally, the reference numerals used in the "signal path" of FIG. 7 are the same as those used in FIG.

For example, although the number of circuits on the signal path is small at "A" in FIG. 7, the number of circuits on the signal path is large at "B" in FIG. It can be seen that the time required for the / D conversion varies.

Further, in the circuit diagram shown in FIG. 6, the output of the window comparator of a certain stage is connected to the error correction circuits of all subsequent stages. For example, in FIG. 6, the output of the window comparator 50a is connected to the OR circuit 18 and the AND circuits 21 and 31, which constitute the error correction circuit 53, respectively.

Therefore, when the output of the window comparator of a certain stage becomes "1", the error correction circuit 53 may immediately determine all the digital data of the stages after the window comparator.

For example, the window comparator 50a
Becomes "1" at that time, the error correction circuit 53
The output of the OR circuit 18 is “1”, and the AND circuit 2
The outputs of 1 and 31 are determined to be "0", and the output of the window comparator 50d is determined to be "0".

The cascade A / D converter sequentially converts the A / D conversion result from the most significant bit. The result of the conversion is determined by the sequentially delayed clock signal, so that the next stage before the end of the final settling is completed. It is possible to shift to A / D conversion work and to reduce the A / D conversion time.

However, depending on the level of the analog input signal, the A / D conversion may be immediately completed up to the least significant bit as described above. If the signal is subjected to A / D conversion, the previous A / D conversion result will be destroyed.

Therefore, the effect of shortening the A / D conversion time due to the fact that the A / D conversion of the next analog input signal can be started before the end of the A / D conversion of the previous analog input signal may not be realized. .

Further, as the number of bits increases, the number of input terminals of the AND circuit constituting the window comparator increases, the types of required AND circuits increase, and the wiring becomes complicated.

FIG. 8 is a circuit diagram showing an embodiment in which such a problem is solved. In FIG. 8, 8a to 8c, 8f, 9
a to 9c, 9e, 9f, 10a, 10b, 10d, 11
a, 11b, 11d, 13a to 13h, 14, 15, 1
7 to 21, 29, 30, and 50a to 50b are denoted by the same reference numerals as in FIG. 6, and 16a, 28a, and 31a are AND
Circuits, 32 and 33 are OR circuits, 100h is an analog input signal, and 101i is a digital output signal.

Further, reference numerals 13e, 13f and 16a denote window comparators 50e and 13g, 13h and 2
8a stores the window comparator 50f,
0, 21, 30, and 31a indicate that the error correction circuit 54 is
2 and 33 constitute delay means 55, respectively.

The connection relation is almost the same as that of FIG. 6 and different points are as follows. That is, the outputs of the AND circuits 14 and 15 are connected to the OR circuit 32, respectively, and the output of the OR circuit 32 is connected to the inverted input terminals of the AND circuits 16a and 31a.
Connected to one input terminal of R circuit 33.

The other input terminal of the OR circuit 33 is AND
The output of the circuit 16a is connected, and the output of the OR circuit 33 is A
Connected to the negative logic input terminal of ND circuit 28a.

The operation of the embodiment shown in FIG. 8 will be described with reference to FIGS. 9 and 10. FIG. 9 is a table showing logical formulas and the like of each signal in FIGS. 6 and 8, and FIG. 10 is a table showing a difference in signal path depending on the level of the analog input signal 100h in the embodiment shown in FIG. Incidentally, the reference numerals used in the “signal path” of FIG. 10 are the same as those used in FIG.

Window comparator 5 in FIG.
0a, 50b, 50c and 50d are output as "W1
O "," W2O "," W3O ", and" W4O ", the window comparators 50a, 50b,
The output signals of 50e and 50f are referred to as "W1O '", "W2
O '","W3O'"and" W4O '".

The output signals of the comparators 13a to 13h are "C1LO", "C1HO", and "C2L", respectively.
O "," C2HO ", C3LO", "C3HO", "C
4LO "and" C4HO ".

Further, the comparators 8a, 8b, 8c and 8f
Output signals of "C1O", "C2O", "C3
O "and" C4O ".

As can be seen from FIG. 9A, the output signals "W1O" to "W4O" of the window comparator are equal to "W1O '" to "W4O'", respectively.
As can be seen from (B), the latch circuits 9a, 9b, 9c,
The logical expressions of the inputs to 9e and 9f are also the same between FIG. 6 and FIG.

Therefore, the embodiment shown in FIG. 8 operates similarly to the circuit diagram shown in FIG.

On the other hand, as can be seen from FIG. 10, regarding the input path to the latch circuits 9e and 9f, "O" in FIG.
As shown by the marks, a delay occurs due to the addition of the OR circuits 32 and 33 to the path, and the variation of the A / D conversion time due to the level of the analog input signal in the same bit can be suppressed.

Further, the OR circuits 32 and 33 are the same as those shown in FIG.
Since it does not enter the paths indicated by "a", "b", "c" and "d", settling is not deteriorated.

Also, by increasing the delay time of the OR circuits 32 and 33, the difference in A / D conversion time for the same bit can be suppressed, or by providing a delay circuit at the input or output of the OR circuits 32 and 33. A /
The difference in D conversion time may be suppressed.

As a result, by giving a delay to the output of the window comparator, it is possible to suppress the fluctuation of the A / D conversion time due to the level of the analog input signal for the same bit.

Also, even if the number of bits increases, the window
The number of inputs of the AND circuit constituting the comparator may be three, the number of necessary AND circuits is reduced, the wiring is formed in a simple repetitive pattern, the wiring area is reduced, and the number of design steps can be reduced.

In the embodiment shown in FIG. 1 and the like, the overall amplification of the signal path passing through the comparator, D / A converter, subtractor, etc. of each stage becomes extremely large at the transition of the code.
In some cases, settling deteriorated, noise occurred, and it was difficult to ensure stability.

For example, FIG. 11 is a characteristic curve diagram showing input / output characteristics of the comparators 8a to 8c and the like. It is assumed that the analog input signal is a pulse signal which fluctuates near the threshold value of the comparator while ringing as shown by "A" in FIG.

The input / output characteristics of the comparator are shown in FIG.
Since the characteristics are as shown in “b” in FIG.
When an analog input signal as shown in FIG.
An output signal as shown in "C" is output.

The output signal indicated by "c" in FIG.
Ringing appears in the middle "d" portion, and this ringing continues to be amplified by passing through a D / A converter, a subtractor, another comparator, and the like at the subsequent stage. Actually, ringing is present until the analog input changes, which may cause noise or hinder stable operation.

In this case, it is improved by providing the comparator with a hysteresis characteristic. For example, FIG. 12 is a characteristic curve showing input / output characteristics and the like of a comparator having hysteresis characteristics.
It is assumed that the pulse signal is the same as in the case of "a".

In FIG. 12, "A" indicates the input / output characteristics of the comparator having the hysteresis characteristic. Even when a pulse signal as shown in "B" in FIG. 12 is applied, the vicinity of the threshold value becomes a dead zone due to the hysteresis characteristic. Therefore, the output signal is
As shown in the middle "c", the signal becomes a signal in which the ringing of the input is absorbed.

As a result, the settling characteristic is improved by giving the comparator a hysteresis characteristic. Also,
If the width of the dead zone is made smaller than the window width of the window comparator, there is no effect on the DC accuracy of the A / D conversion.

[0150]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. Cascade A /
A cascade A / D converter capable of operating without errors by one clock can be realized by detecting a change in the code of the D converter with a window comparator and removing noise generated at a point where the code changes.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a cascade A / D converter according to the present invention.

FIG. 2 is a characteristic curve diagram showing each output or each input with respect to an analog input signal.

FIG. 3 shows a cascade A / D that outputs a binary code.
FIG. 3 is a circuit diagram showing one embodiment of a converter.

FIG. 4 is a characteristic curve diagram showing each output or each input with respect to an analog input signal.

FIG. 5 is a characteristic curve diagram showing each output or each input with respect to an analog input signal.

FIG. 6 is a circuit diagram showing an example in which the embodiment shown in FIG. 1 has a 5-bit configuration.

FIG. 7 is a table showing differences in signal paths depending on the level of an analog input signal 100g of the circuit shown in FIG. 6;

FIG. 8 is a circuit diagram showing an embodiment that solves the problem.

FIG. 9 is a table showing a logical expression of each signal of FIGS. 6 and 8;

FIG. 10 shows the analog input signal 100 of the embodiment shown in FIG.
9 is a table showing differences in signal paths depending on the level of h.

FIG. 11 is a characteristic curve diagram showing input / output characteristics of the comparator.

FIG. 12 is a characteristic curve showing input / output characteristics and the like of a comparator having hysteresis characteristics.

FIG. 13 is a configuration block diagram illustrating an example of a conventional A / D converter.

FIG. 14 is a circuit diagram and a timing diagram illustrating an example of a cascade A / D converter.

FIG. 15 is a circuit diagram and a timing diagram illustrating an example of a cascade A / D converter.

FIG. 16 is a circuit diagram when the cascade A / D converter is operated by one clock.

FIG. 17 is a characteristic curve diagram showing the operation of the conventional example shown in FIG.

[Description of Signs] 1 Resistor array 2, 8a, 8b, 8c, 8d, 8e, 8f, 13a, 1
3b, 13c, 13d, 13e, 13f, 13g, 13
h Comparator 3 Encoder 4, 7 Parallel A / D converter 5, 10a, 10b, 10c, 10d D / A converter 6, 11a, 11b, 11c, 11d Subtractor 9a, 9b, 9c, 9d, 22a, 22b, 22c, 2
2d, 22e, 22f, 22g Latch circuit 12a, 12b, 12c Sample hold circuit 14, 15, 16, 16a, 21, 23a, 23b, 2
3c, 23d, 24, 28, 28a, 31, 31a AND circuit 17, 19, 29 Exclusive OR circuit 18, 20, 25, 26, 27, 30, 32, 33 OR circuit 50a, 50b, 50c, 50d, 50e, 50f Window comparators 51, 52, 53, 54 Error correction circuit 55 Delay means 100, 100a, 100b, 100c, 100d, 1
00e, 100f, 100g, 100h Analog input signals 101, 101a, 101b, 101c, 101d, 1
01e, 101f, 101g, 101h, 101i Digital output signal

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-53832 (JP, A) JP-A-5-14199 (JP, A) JP-A-7-7431 (JP, A) JP-A-58-58 236660 (JP, A) JP-A-58-215127 (JP, A) JP-A-57-23322 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 1/00-1 / 88

Claims (3)

(57) [Claims] A comparator for converting an analog input signal into a digital signal; a latch circuit for holding an output of the comparator; and a D for converting an output of the comparator into an analog signal again.
/ A converter and a subtractor for subtracting the output of the D / A converter from the analog input signal in a cascade of a plurality of stages. A cascade A / D converter comprising: a plurality of window comparators for detecting a code change; and an error correction circuit for removing noise generated at a code change point based on an output of the window comparator. 2. A comparator for converting an analog input signal into a digital signal, a latch circuit for holding an output of the comparator, and a D for converting an output of the comparator into an analog signal again.
/ A converter and a subtractor for subtracting the output of the D / A converter from the analog input signal in a cascade of a plurality of stages. A plurality of window comparators for detecting a code change; delay means for delaying the output of the window comparator; and an error for removing noise generated at a code change point based on the output of the window comparator or the delay means. A cascade A / D converter comprising a correction circuit. 3. A cascade A / D converter according to claim 1, wherein said comparator has a hysteresis characteristic.