JP3446881B2 - Pipeline A / D converter - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a pipeline A /
Regarding the D converter, especially the pipeline A with improved linearity
/ D converter.

[0002]

2. Description of the Related Art A conventional pipeline A / D converter quantizes an input signal with a 1-bit A / D converter, subtracts the quantized analog value from the input signal, and appropriately amplifies the analog signal. The A / D converter is configured by connecting a plurality of pipeline stages for outputting to each other in series.

FIG. 5 is a block diagram showing an example of such a conventional N-bit pipeline A / D converter. In FIG. 5, 1a, 1b, 1c, 1d and 1e are 1
Bit A / D converters, 2a, 2b, 2c and 2d are 1-bit D / A converters, 3a, 3b, 3c and 3d are subtractors, 4a, 4b, 4c and 4d are residual amplifiers, and 100 is an analog input. A signal, 101 is a positive / negative reference voltage supplied to the D / A converters 2a to 2d, and 102 is a digital output signal.

Further, 1a to 4a are pipeline stages 50a, and 1b to 4b are pipeline stages 50b.
1c to 4c denote the pipeline stage 50c and 1d.
4d are pipeline stages 50d, 1e and 50
Each of a to 50d constitutes a pipeline A / D converter 51.

The analog input signal 100 is the A / D converter 1
a is connected to the input terminal of the subtractor 3a and the digital output of the A / D converter 1a is connected to the MSB.
Is output to the digital output signal 102 as
It is connected to the digital input terminal of the / A converter 2a. D
The output of the / A converter 2a is connected to the subtraction input terminal of the subtractor 3a, and the output of the subtractor 3a is output to the subsequent stage via the residual amplifier 4a.

The output of the residual amplifier 4a is the A / D converter 1b.
Of the D / A converter 2b and the digital output of the A / D converter 1b is output to the digital output signal 102.
Connected to the digital input terminal of. D / A converter 2b
Is connected to the subtraction input terminal of the subtractor 3b, and the output of the subtractor 3b is output to the subsequent stage via the residual amplifier 4b.

The output of the residual amplifier 4b is the A / D converter 1c.
Of the A / D converter 1c, and the digital output of the A / D converter 1c is output to the digital output signal 102 and the D / A converter 2c.
Connected to the digital input terminal of. D / A converter 2c
Is connected to the subtraction input terminal of the subtractor 3c, and the output of the subtractor 3c is output to the subsequent stage via the residual amplifier 4c.

The output of the residual amplifier 4c is the A / D converter 1d.
Of the A / D converter 1d, and the digital output of the A / D converter 1d is output to the digital output signal 102 and the D / A converter 2d.
Connected to the digital input terminal of. D / A converter 2d
Is connected to the subtraction input terminal of the subtractor 3d, and the output of the subtractor 3d is output to the subsequent stage via the residual amplifier 4d.

The output of the residual amplifier 4d is connected to the input terminal of the A / D converter 1e, and the digital output of the A / D converter 1e is used as the LSB to output the digital output signal 102.
Is output to. The positive / negative reference voltage 101 is connected to the positive / negative reference voltage input terminals of the D / A converters 2a to 2d, respectively.

The operation of the conventional example shown in FIG. 5 will be described. The "N-1" pipeline stages are connected in series, and the 1-bit A / D converters 1a to 1e forming this pipeline stage judge only the polarity of the input analog signal, and the analog input is " When it is "0" or "negative", a digital signal of "0" is output, and when the analog input is "positive", a digital signal of "1" is output.

On the other hand, the D / A converters 2a to 2d output a negative reference voltage when the digital input from the A / D converters 1a to 1d is "0", and when the digital input is "1". Outputs a positive reference voltage. For example, the reference voltage 10
If 1 is "+ Vr" and "-Vr", "-V" is input when the digital inputs are "0" and "1", respectively.
It outputs r "and" + Vr ".

The analog input signal 100 is the A / D converter 1
The polarity is judged by a, and when the polarity is "positive", the positive reference voltage of the D / A converter 2a is subtracted from the analog input signal 100 in the subtractor 3a. Residual amplifier 4
The result a is doubled and the amplified result is output to the subsequent pipeline stage 50b. Then, the same operation is performed in the pipeline stages 50b to 50d, and finally the digital output signal 102 by the A / D converter 1e.
Is determined.

That is, by connecting a plurality of such pipeline stages in series, the reference voltage is sequentially added or subtracted from the analog input signal 100 and is doubled before being output to the subsequent stage. It operates as an A / D converter having a resolution of line stage number + 1 ″.

[0014]

However, in the residual amplifiers 4a to 4d generally used in the pipeline stages 50a to 50d, a gain error occurs due to the finite open loop DC gain of the operational amplifier. For example, when the open loop gain of the operational amplifier is "A" and the feedback rate is "β", the closed loop gain "G" is G = A / (1 + A · β) (1).

For this reason, the gain error “ΔG” with respect to the ideal gain “1 / β” is ΔG = A / (1 + A · β) −1 / β = −1 / {(1 + A · β) · β } (2)

The gain error "δ" normalized by the gain value is δ = ΔG / G≅-1 / (Aβ) (3)

The gain error "δ" deteriorates the linearity in the entire A / D conversion characteristic. this is,
This is because the subtraction is performed with the same reference voltage as that of the first stage even though the full scale of the output of the residual amplifier is reduced due to the gain error of the residual amplifier that constitutes each pipeline stage.

This phenomenon will be described with reference to FIG. FIG. 6 shows an A / D converter, D /
It is explanatory drawing explaining operation | movement of an A converter, a subtractor, and a residual amplifier, (a) and (e) in FIG. 6 are A / D converter 1a.
And 1b for the analog input signal 100, (b) and (f) in FIG. 6 are analog outputs of the D / A converters 2a and 2b, and (c) and (g) in FIG. 6 are subtractors 3a and 3b. , The output of the residual amplifier 4a is shown in FIG. 6 (d), and the quantization levels for 3 bits are shown in (h) and (i) of FIG.

When the full scale of the analog input signal 100 is "-4Vr" of "-2Vr to + 2Vr" and the reference voltages supplied to the D / A converter are "-Vr" and "+ Vr", the A / D converter is assumed. Since 1a determines the polarity of the input signal, its output outputs the values "0" and "1" with "0" of the analog input signal 100 as the boundary, as shown in FIG. 6 (a).

Therefore, the output of the D / A converter 2a is shown in FIG.
"0" of analog input signal 100 as shown in middle (b)
"-Vr" and "+ Vr" are output at the boundary.

On the other hand, the subtractor 3a is connected to the analog input signal 10
Since the output of the D / A converter 2a is subtracted from 0, in the range where the analog input signal 100 increases from "-2Vr" to "0", the analog input signal 100 is converted to "-V".
Since r "is subtracted, the output of the subtractor 3a increases from" -Vr "to" + Vr "as shown in FIG. 6 (c).

Further, the analog input signal 100 is "0".
Up to "+ 2Vr", analog input signal 1
Since "+ Vr" is subtracted from 00, the output of the subtractor 3a increases from "-Vr" to "+ Vr" as shown in (c) of FIG.

The output of the subtractor 3a as shown in FIG. 6 (c) is doubled by the residual amplifier 4a and becomes as shown in FIG. 6 (d). As shown by the solid line in (d) of FIG.
It falls within the range of −2 (1 + δ) Vr ″ to “+2 (1 + δ) Vr”. On the other hand, in the ideal case where there is no gain error, it is completely 2 as shown by the broken line in (d) of FIG. It is doubled to be in the range of "-2Vr" to "+ 2Vr".

Further, the A / D converter 1b is a residual amplifier 4
Since the polarity of the output of a is judged, the output is shown in FIG.
As shown in, the analog input signal 100 is "-2Vr".
"0" in the range of "-Vr" and "0"-"+ Vr"
Value is output and the analog input signal 100 is "-Vr".
In the range of "0" and "+ Vr" to "+ 2Vr"
The value of 1 ”is output.

Therefore, the output of the D / A converter 2b is shown in FIG.
As shown in middle (f), the analog input signal 100 is "-2".
In the range of Vr "to" -Vr "and" 0 "to" + Vr ", the value of" -Vr "is output and the analog input signal 100
In the range of "-Vr" to "0" and "+ Vr" to "+ 2Vr", the value of "+ Vr" is output.

Since the subtractor 3b subtracts the output of the D / A converter 2b from the output of the residual amplifier 4a shown in FIG. 6D, the analog input signal 100 is "-".
In the range of 2Vr "to" -Vr "and" 0 "to" + Vr "," -Vr "is subtracted from the output of the residual amplifier 4a, so that the output of the subtractor 3b is as shown in FIG. "-
(1 + 2δ) Vr ″ to “+ Vr”.

The analog input signal 100 is "-V".
Since "+ Vr" is subtracted from the output of the residual amplifier 4a in the range of r "to" 0 "and" + Vr "to" + 2Vr ", the output of the subtractor 3b is"-"as shown in FIG. V
r ″ to “+ (1 + 2δ) Vr”.

The zero-cross point of the output of the subtractor 3b shown in FIG. 6 (g) is shown in FIGS. 6 (h) and 6 (i). As shown in the figure, "○" shows that the quantization levels are evenly arranged, but when there is a gain error, "●" shows that the quantization levels are not even and the linearity deteriorates as shown in FIG. 6 (h). I understand.

The linearity error “linerr” with respect to the standardized gain error “δ” is expressed as linerr = δ {1- (1/2 ^N−1 )} · 2 ^N [LSBp-p] (4) It is approximated.

For example, when configuring an 8-bit pipeline A / D converter with "N = 8", "A = 512"
And when the linearity of the quantum level is plotted by using the equation (4) with “β = ½ (δ = 0.390625%)”, it becomes as shown in FIG. 7. FIG. 7 is a characteristic curve diagram showing an example of the linearity of the quantum level, and a linearity error of about "1 LSBp-p" occurs when the input is near "0".

At this time, there is a problem that the operating speed is sacrificed when the DC gain of the operational amplifier is increased to improve the linearity. On the contrary, there is a problem that a high-speed operational amplifier cannot obtain a sufficiently large DC gain, and it is difficult to achieve both accuracy and conversion speed. Therefore, the problem to be solved by the present invention is to realize a pipeline A / D capable of improving linearity at high speed.
It is to realize the converter.

[0032]

In order to achieve the above-mentioned object, the invention according to claim 1 of the present invention is a pipeline A / D converter having a plurality of stages connected in series.
A 1-bit A / D converter that determines the polarity of the input signal
1 bit that converts the output of the A / D converter of
D / A converter and the D / A converter from the input signal
A subtractor that subtracts the output of
And a pipeline stage composed of a residual amplifier for outputting and a second 1-bit A / D converter, and the pipeline of the first stage.
Group supplied to the D / A converter that constitutes the on-stage.
A replica circuit to which a quasi voltage is input, the reference voltage and
The output of the replica circuit and the voltage of the residual amplifier are divided by voltage division.
The correction reference voltage for correcting the in-error is set to the second and subsequent steps.
Each D / A change that constitutes each pipeline stage
Reference voltage generation consisting of voltage dividing means for supplying to converter
By and means, it is possible to improve the linearity at high speed.

[0033] According to a second aspect of the invention, in a pipelined A / D converter is the invention of claim 1, wherein said replica
The Ricah circuit makes up the residuals that make up each of the pipeline stages.
Multiple stages of amplifiers with the same DC characteristics as the difference amplifier in series
The connection makes it possible to improve linearity at high speed.

According to a third aspect of the invention, in the pipeline A / D converter according to the first aspect of the invention, the partial pressure is
Means for connecting a plurality of resistors in series to determine the voltage at each connection point
Each of the pipelines from the second stage onward as a correction reference voltage
To the D / A converters that make up each stage.
Since the resistance is a resistance, the linearity can be improved at high speed.

According to a fourth aspect of the invention, in the pipeline A / D converter according to the first aspect of the invention, the residual
The amplifier and the subtractor are used to input the input signal in the first phase.
Amplified, and the D / A to the amplified value in the second phase.
Switched capacity to add or subtract the output of the converter
The linear amplifier can be improved at a high speed by using the sita type amplifying means .

[0036]

[0037]

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of a pipeline A / D converter according to the present invention. In FIG. 1, 1a to 1e, 2a to 2d, 3a to 3d, 4a to 4d,
Reference numerals 50a to 50d, 51 and 100 to 102 are the same as those in FIG. 5, 5a, 5b, 6a, 6b, 7a and 7b are resistors, 8 is a replica circuit, and 9a and 9b are buffer amplifiers. Also, 5a, 5b, 6a, 6b, 7a
Reference numerals 7 and 7b constitute the voltage dividing means 52, and reference numerals 8, 9a, 9b and 52 constitute the reference voltage generating means 53, respectively.

The analog input signal 100 is the A / D converter 1
a is connected to the input terminal of the subtractor 3a and the digital output of the A / D converter 1a is connected to the MSB.
Is output to the digital output signal 102 as
It is connected to the digital input terminal of the / A converter 2a. D
The output of the / A converter 2a is connected to the subtraction input terminal of the subtractor 3a, and the output of the subtractor 3a is output to the subsequent stage via the residual amplifier 4a.

The output of the residual amplifier 4a is the A / D converter 1b.
Of the D / A converter 2b and the digital output of the A / D converter 1b is output to the digital output signal 102.
Connected to the digital input terminal of. D / A converter 2b
Is connected to the subtraction input terminal of the subtractor 3b, and the output of the subtractor 3b is output to the subsequent stage via the residual amplifier 4b.

The output of the residual amplifier 4b is the A / D converter 1c.
Of the A / D converter 1c, and the digital output of the A / D converter 1c is output to the digital output signal 102 and the D / A converter 2c.
Connected to the digital input terminal of. D / A converter 2c
Is connected to the subtraction input terminal of the subtractor 3c, and the output of the subtractor 3c is output to the subsequent stage via the residual amplifier 4c.

The output of the residual amplifier 4c is the A / D converter 1d.
Of the A / D converter 1d, and the digital output of the A / D converter 1d is output to the digital output signal 102 and the D / A converter 2d.
Connected to the digital input terminal of. D / A converter 2d
Is connected to the subtraction input terminal of the subtractor 3d, and the output of the subtractor 3d is output to the subsequent stage via the residual amplifier 4d.

The output of the residual amplifier 4d is connected to the input terminal of the A / D converter 1e, and the digital output of the A / D converter 1e is used as the LSB to output the digital output signal 102.
Is output to.

The positive reference voltage of the reference voltage 101 is D
Connected to the positive reference voltage input terminal of the A / A converter 2a, one end of the resistor 5a and one input terminal of the replica circuit 8, and the negative reference voltage of the reference voltage 101 is the negative reference voltage of the D / A converter 2a. Input terminal, one end of resistor 5b and replica circuit 8
Connected to the other input terminal of.

The other end of the resistor 5a is connected to one end of the resistor 6a and D /
It is connected to the positive reference voltage input terminal of the A converter 2b, and the other end of the resistor 5b is connected to one end of the resistor 6b and the negative reference voltage input terminal of the D / A converter 2b.

The other end of the resistor 6a is connected to one end of the resistor 7a and D /
It is connected to the positive reference voltage input terminal of the A converter 2c, and the other end of the resistor 6b is connected to one end of the resistor 7b and the negative reference voltage input terminal of the D / A converter 2c.

The other end of the resistor 7a is connected to the positive reference voltage input terminal of the D / A converter 2d and the output of the buffer amplifier 9a, and the other end of the resistor 7b is input to the negative reference voltage of the D / A converter 2d. It is connected to the terminal and the output of the buffer amplifier 9b. Then, the two outputs of the replica circuit 8 are connected to the input terminals of the buffer amplifiers 9a and 9b, respectively.

The operation of the embodiment shown in FIG. 1 will be described here. However, "N-1" pipeline stages are connected in series, and the operation is the same as in the conventional example shown in FIG.

The replica circuit 8 is an operational amplifier having the same DC characteristics as the residual amplifier 4a and the like, and has a closed loop gain ".
Configure the feedback circuit so that it becomes "1" and "2 (N-2)"
They are connected in series.

The normalized gain error "δ" generated in one stage of the residual amplifier is obtained by substituting "β = 1/2" into the equation (3), and δ = ΔG / G = -2 / A (5 ).

On the other hand, the standardized gain error "δrep" of one stage of the operational amplifier which constitutes the above-mentioned replica circuit 8 is obtained.
Is expressed by δrep = ΔGrep / Grep = -1 / A (6).

Here, the input full scale of the pipeline A / D converter 51 is set to "Vfso (= 4Vr)".
Considering the attenuation due to the gain error of the residual amplifier accumulated up to the output of the “kth” pipeline stage, “k
Th “pipeline stage output full scale”
Vfsk ″ is Vfsk = Vfso (1 + δ) ^k ≉Vfso (1 + kδ) = Vfso (1-2 k / A) (7)

On the other hand, in the replica circuit 8, "2 (N-2)" amplifiers having a closed loop gain of "1" are connected in series, and a gain error ".delta.rep.
l ″ is δrep.total = (1 + δrep) ^{2 (N−2)} −1 ≈2 (N−2) · δrep = −2 (N−2) / A (8).

Final output of replica circuit 8 and reference voltage 10
The correction reference voltage “Vrefm”, which is the output voltage of the “mth” tap obtained by dividing the potential difference “Vref0 (= 2Vr)” of 1 by the reference ladder resistor 52, is Vrefm = Vref0 · (1 + δrep.total · m / (N-2)) = Vref0 * (1- {2 (N-2) / A} * (m / N-2)) = Vref0 * (1-2m / A) (9).

Here, when the tap number "m" and the pipeline stage number "k" are made to correspond to each other, Vfsk / Vrefm = (Vfso / Vref0) * (1-2k / A) / (1 -2m / A) = 4Vr / 2Vr = 2 (∵k = m) (10).

That is, as can be seen from the equation (10), the ratio between the full scale of each pipeline stage and the correction reference voltage of the D / A converter is the same in all pipeline stages.

This state will be described with reference to FIG. FIG. 2 shows an A / D converter, D /, which constitutes each pipeline stage.
It is explanatory drawing explaining operation | movement of an A converter, a subtractor, and a residual amplifier, (a) and (e) in FIG. 2 are A / D converter 1a.
And 1b for the analog input signal 100, (b) and (f) in FIG. 2 are analog outputs of the D / A converters 2a and 2b, and (c) and (g) are subtractors 3a and 3b in FIG. , The output of the residual amplifier 4a is shown in FIG. 2 (d), and the quantization level for 3 bits is shown in FIG. 2 (h).

When the full scale of the analog input signal 100 is "-4Vr" of "-2Vr to + 2Vr" and the reference voltage supplied to the D / A converter is "-Vr" and "+ Vr", the A / D converter is assumed. Since 1a determines the polarity of the input signal, its output outputs the values of "0" and "1" at the boundary of "0" of the analog input signal 100, as shown in FIG.

Therefore, the output of the D / A converter 2a is shown in FIG.
"0" of analog input signal 100 as shown in middle (b)
"-Vr" and "+ Vr" are output at the boundary.

On the other hand, the subtractor 3a operates on the analog input signal 10
Since the output of the D / A converter 2a is subtracted from 0, in the range where the analog input signal 100 increases from "-2Vr" to "0", the analog input signal 100 is converted to "-V".
Since r "is subtracted, the output of the subtractor 3a increases from" -Vr "to" + Vr "as shown in (c) of FIG.

Further, the analog input signal 100 is "0".
Up to "+ 2Vr", analog input signal 1
Since "+ Vr" is subtracted from 00, the output of the subtractor 3a increases from "-Vr" to "+ Vr" as shown in (c) of FIG.

The output of the subtractor 3a as shown in FIG. 2 (c) is doubled by the residual amplifier 4a and becomes as shown in FIG. 2 (d). It is not completely doubled, but from "-2 (1 + δ) Vr" to "+2
It is in the range of (1 + δ) Vr ″.

Further, the A / D converter 1b is the residual amplifier 4
Since the polarity of the output of a is judged, its output is shown in FIG.
As shown in, the analog input signal 100 is "-2Vr".
"0" in the range of "-Vr" and "0"-"+ Vr"
Value is output and the analog input signal 100 is "-Vr".
In the range of "0" and "+ Vr" to "+ 2Vr"
The value of 1 ”is output.

At this time, from the equation (10), the ratio between the full scale “± 2 (1 + δ) Vr” of the output of the residual amplifier 4a and the corrected reference voltage of the D / A converter 2b is “2” by the reference voltage generating means 53. Therefore, the correction reference voltage supplied to the D / A converter 2b is "± (1 + δ) Vr". Therefore, the output of the D / A converter 2b is the analog input signal 100 from "-2Vr" to "-Vr" as shown in (f) of FIG.
And "-(1 + δ) V in the range of" 0 "to" + Vr "
The value of r "is output and the analog input signal 100 is" -V.
In the range of r "to" 0 "and" + Vr "to" + 2Vr ", the value of" + (1 + δ) Vr "is output.

Since the subtractor 3b subtracts the output of the D / A converter 2b from the output of the residual amplifier 4a shown in FIG. 2D, the analog input signal 100 is "-".
In the range of 2Vr "to" -Vr "and" 0 "to" + Vr ","-(1 + δ) Vr "is subtracted from the output of the residual amplifier 4a, so that the subtracter 3b is provided as shown in FIG. Output increases from "-(1 + δ) Vr" to "+ (1 + δ) Vr".

The analog input signal 100 is "-V".
In the range of r "to" 0 "and" + Vr "to" + 2Vr "," + (1 + δ) Vr "is subtracted from the output of the residual amplifier 4a. The output increases from "-(1 + δ) Vr" to "+ (1 + δ) Vr".

When the zero crossing point of the output of the subtractor 3b shown in FIG. 2 (g) is shown in FIG. 2 (h), it can be seen that "" are evenly arranged in the quantization level and the linearity is improved.

As a result, the output of the replica circuit 8 in which a plurality of operational amplifiers having the same DC characteristics as the residual amplifier are connected in series and the reference voltage 101 are divided by the voltage dividing means 52, and each voltage is obtained in each pipeline stage. By supplying it as the correction reference voltage of the D / A converter, the ratio between the full scale of each pipeline stage and the correction reference voltage of the D / A converter becomes the same in all the pipeline stages. It is possible to improve the linearity at high speed without sacrificing.

FIG. 3 shows the pipeline stage 50a.
FIG. 6 is a circuit diagram showing a specific example of a switched capacitor type residual amplifier having functions of a subtracter and a residual amplifier in the above.

In FIG. 3, 10a, 10b, 10c and 10d are capacitors, 11 is a differential input / output amplifier, 12a, 1
2b, 12c, 12d, 13a, 13b, 14a, 14
b, 14c, 14d, 15a and 15b are switch circuits, 103 and 104 are differential input signals, and 105 and 1
06 is a differential output signal, and 107 and 108 are 1-bit D
Output signals of the A / A converter, and 109 and 110 are control signals of the switch circuit.

The input signal 103 is connected to one end of the switch circuits 12a and 12b, and the input signal 104 is connected to one end of the switch circuits 12c and 12d. The other end of the switch circuit 12a is connected to one end of the capacitor 10a and the switch circuit 14a
Is connected to one end of the switch circuit 12b and the other end of the switch circuit 12b has a capacitance of
0b and one end of the switch circuit 14c, and the output signal 107 is connected to the other end of the switch circuit 14c.

The other end of the switch circuit 12c is connected to one end of the capacitor 10c and one end of the switch circuit 14d, the output signal 108 is connected to the other end of the switch circuit 14d, and the other end of the switch circuit 12d is connected to the capacitor 10d. It is connected to one end and one end of the switch circuit 14b.

The other end of the capacitor 10a is connected to the other end of the capacitor 10b, the non-inverting input terminal of the amplifier 11 and one end of the switch circuit 13a, and the other end of the capacitor 10c is the other end of the capacitor 10d.
It is connected to the inverting input terminal of the amplifier 11 and one end of the switch circuit 13b.

The inverting output terminal of the amplifier 11 outputs the output signal 10
5 is connected to the other ends of the switch circuits 13a and 14a, and the non-inverting output terminal of the amplifier 11 outputs the output signal 106 and the switch circuits 13b and 14b.
Is connected to the other end of.

Further, the control signal 109 is the switching circuit 12
a to 12d and 13a to 13b are connected to the control terminals,
The control signal 110 is connected to the control terminals of the switch circuits 14a to 14d.

The operation of the circuit shown in FIG. 3 will be briefly described. In the first phase, the control signal 109 causes the switch circuits 12a to 12d and 13a to 13b to be "ON",
The control signals 110 cause the switch circuits 14a to 14d to
When turned off, the amplifier 11 enters a reset state in which the input and output are short-circuited, and the differential input signals 103 and 104 are sampled in the capacitors 10a to 10d.

Next, in the second phase, the control signal 109 causes the switch circuits 12a to 12d and 13a to 13b.
Is "OFF", and the switch circuit 14 is activated by the control signal 110.
When a to 14d are turned "ON", the output signals 107 and 10 have a voltage twice the potential difference between the input signal 103 and the input signal 104 stored in the capacitors 10a to 10d in the first phase.
An output signal obtained by adding 8 is output.

In the second phase, the input signal 103
Since and 104 are insulated and are not affected, if the phase of the residual amplifier before and after the pipeline stage is shifted, the output at the time of the first phase will not be input to the subsequent pipeline stage. 1 bit D /
If the polarity of the output signal from the A converter is reversed, it will operate as a subtractor.

As a result, the use of the residual amplifier as shown in FIG. 3 eliminates the need for a special subtraction circuit, so that the circuit structure can be simplified.

FIG. 4 is a configuration block diagram showing a specific example of the circuit configuration of the replica circuit when the residual amplifier as shown in FIG. 3 is used in the pipeline stage. In FIG. 4, 16a and 16b are capacitors, 17 is a differential input / output amplifier having the same DC characteristics as the amplifier 11 in FIG.
8a, 18b, 19a, 19b, 20a and 20b are switch circuits, 111 and 112 are input signals, 113 and 1
Reference numeral 14 is an output signal, and 115 and 116 are control signals.

Further, 16a, 16b, 17, 18a, 1
8b, 19a, 19b, 20a and 20b are amplification means 5
4, 54a, 54b and 54c are amplifying means having the same configuration as the amplifying means 54. In addition, the whole constitutes a replica circuit 55.

The input signals 111 and 112 are connected to one ends of the switch circuits 18a and 18b, respectively.
The other end of a is connected to one end of the capacitor 16a and one end of the switch circuit 20a. The other end of the switch circuit 18b is connected to one end of the capacitor 16b and one end of the switch circuit 20b.

The other end of the capacitor 16a is connected to the non-inverting input terminal of the amplifier 17 and one end of the switch circuit 19a, and the other end of the capacitor 16b is connected to the inverting input terminal of the amplifier 17 and one end of the switch circuit 19b.

The inverting output terminal of the amplifier 17 is connected to the amplifying means 54a in the subsequent stage and the switch circuits 19a and 2a.
0a, the non-inverting output terminal of the amplifier 17 is connected to the amplifying means 54a in the subsequent stage and the other ends of the switch circuits 19b and 20b.

Further, the control signal 115 is the switching circuit 18
connected to the control terminals of a, 18b, 19a and 19b,
The control signal 116 is connected to the control terminals of the switch circuits 20a and 20b.

Similarly, the output of the amplifying means 54a is connected to the amplifying means 54b, and the output signals 113 and 114 of the amplifying means 54c at the final stage are output as the output signals of the replica circuit 55.

Here, the operation of the amplifying means shown in FIG. 4 will be briefly described. In the first phase, the control signal 115 causes the switch circuits 18a to 18b and 19a to 19b to be "O".
N ″, the control signal 116 causes the switch circuits 20a and 20a and 2
When 0b becomes "OFF", the amplifier 17 enters a reset state in which the input and output are short-circuited and the differential input signal 1
11 and 112 are sampled in the capacitors 16a and 16b.

Next, in the second phase, the switch circuits 18a-18b and 19a-19b are controlled by the control signal 115.
Is "OFF", and the switch circuit 20 is activated by the control signal 116.
When “a” and “20b” are turned “ON”, a voltage that is one time the potential difference between the input signal 111 and the input signal 112 stored in the capacitors 16a and 16b in the first phase is output.

In the second phase, the input signal 111
Since 112 and 112 are insulated and are not affected, if the phases before and after the amplifying means are shifted, the output at the time of the first phase will not be input to the amplifying means in the subsequent stage.

As a result, when the residual amplifier as shown in FIG. 3 is used in the pipeline stage, by using the replica circuit 55 shown in FIG. 4, the linearity can be improved at high speed.

Although the buffer amplifiers 9a and 9b are provided at the subsequent stage of the replica circuit 8 in the embodiment shown in FIG. 1, the buffer amplifiers 9a and 9b are not necessary if the output stage of the replica circuit 8 has a buffer function.

Further, in the residual amplifier shown in FIG. 3, the polarity of the output of the D / A converter is reversed and input.
The A converter itself outputs an output of opposite polarity, and FIG.
Of course, addition processing may be performed by the residual amplifier shown in FIG.

[0093]

As is apparent from the above description,
The present invention has the following effects. According to the first to fifth aspects of the invention, the output of the replica circuit in which a plurality of operational amplifiers having the same DC characteristics as the residual amplifier are connected in series and the reference voltage are divided by the voltage dividing means to obtain each voltage. By supplying as the correction reference voltage of the D / A converter of each pipeline stage, the ratio between the full scale of each pipeline stage and the correction reference voltage of the D / A converter becomes the same in all the pipeline stages. Therefore, it becomes possible to improve the linearity at high speed without sacrificing the operating speed.

According to the invention of claim 6, the residual amplifier and the subtractor amplify the input signal in the first phase and add the output of the D / A converter to the value amplified in the second phase. Alternatively, by replacing with a switched-capacitor type amplifier for subtraction, a subtraction circuit is not required, so that the circuit configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of a pipeline A / D converter according to the present invention.

FIG. 2 is an explanatory diagram illustrating operations of an A / D converter, a D / A converter, a subtractor, and a residual amplifier.

FIG. 3 is a circuit diagram showing a specific example of a switched capacitor type residual amplifier.

FIG. 4 is a configuration block diagram showing a specific example of a circuit configuration of a replica circuit.

FIG. 5 is a configuration block diagram showing an example of a conventional pipeline A / D converter.

FIG. 6 is an explanatory diagram illustrating operations of an A / D converter, a D / A converter, a subtracter, and a residual amplifier.

FIG. 7 is a characteristic curve diagram showing an example of quantum level linearity.

[Description of Reference Signs] 1a, 1b, 1c, 1d, 1e 1-bit A / D converters 2a, 2b, 2c, 2d 1-bit D / A converters 3a, 3b, 3c, 3d Subtractors 4a, 4b, 4c, 4d Residual amplifiers 5a, 5b, 6a, 6b, 7a, 7b Resistors 8, 55 Replica circuits 9a, 9b Buffer amplifiers 10a, 10b, 10c, 10d, 16a, 16b Capacitance 11, 17 Amplifiers 12a, 12b, 12c, 12d, 13a, 13b, 1
4a, 14b, 15a, 15b, 18a, 18b, 19
a, 19b, 20a, 20b switch circuits 50a, 50b, 50c, 50d pipeline stage 5 51 pipeline A / D converter 52 voltage dividing means 53 reference voltage generating means 54, 54a, 54b, 54c amplifying means 100 analog input signal 101 reference voltage 102 digital output signal 103, 104, 111, 112 input signal 105, 106, 107, 108, 113, 114 output signal, 109, 110, 115, 116 control signal

Continuation of the front page (56) References Japanese Patent Laid-Open No. 59-191928 (JP, A) Suturja, S. et al. Gray, P .; R. , A 250 Ks / s 13 b pipelined A / D Converter, 1988 IEEE International Solid-State Circuits Confence. Digest of Technical Papers. 31st ISSCC. , USA, February 17, 1988, First Edition, p. 228,229,381 (58) Fields investigated (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (4)

(57) [Claims] 1. In a pipeline A / D converter , a 1-bit signal for determining the polarities of input signals of a plurality of stages connected in series is provided.
A / D converter and the output of this A / D converter
1-bit D / A converter for converting the input signal
A subtractor for subtracting the output of the D / A converter from the signal
The residual amplifier that amplifies and outputs the output of the subtractor
Pipeline stage is made and a second 1-bit A /
A pipeline A / D converter including a D converter, and the D / A constituting the first pipeline stage.
Replica times when the reference voltage supplied to the A converter is input
Voltage, the reference voltage and the output of the replica circuit
Correction standard for correcting the gain error of the residual amplifier
Configure each of the above pipeline stages after the second voltage
From the voltage dividing means that supplies each D / A converter
And a reference voltage generating means configured . 2. The replica circuit is the same as the residual amplifier constituting each of the pipeline stages.
Multiple amplifiers with a single DC characteristic connected in series
The pipeline A / D converter according to claim 1. 3. The voltage dividing means connects a plurality of resistors in series and the voltage at each connection point is used as the correction reference.
As the voltage, the pipeline stages from the second stage onward are used.
Ladder resistance supplied to each D / A converter
The pipeline A according to claim 1, wherein
/ D converter. 4. The residual amplifier and the subtractor amplify an input signal in a first phase and in a second phase.
Add the output of the D / A converter to the amplified value.
Is a switched-capacitor type amplification means for subtraction.
The pipeline A / D according to claim 1, characterized in that
converter.