JP2000236257A - Cascade a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actualize the cascade A/D converter which can prevent errors due to noise from being generated. SOLUTION: This cascaded A/D converter constituted by cascading in stages comparators 8a to 8d, which convert analog input signals into digital signals, latching circuits 9a to 9d which hold the outputs of the comparators 8a to 8d, D/A converters which reconvert the outputs of the comparators 8a to 8d into analog signals, and subtracters 11d to 11f which subtract the outputs of the D/A converters from the analog signals is improved. This device has a combining circuit 60 which puts together variation waveforms of the codes of the comparators 8a to 8d, code change point vicinity detecting means which input the variation waveform of the composing circuit 60 and detect changes in the codes of the comparators 8a to 8d with width of code change point vicinity detection of >=2 stages, and an error-correcting circuit which removes noise generated at change points of the codes according to the outputs of the code change points vicinity detecting means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cascade A / D converter which can be operated without error in one clock, and more particularly to a cascade A / D converter which can prevent occurrence of an error due to noise.

[0002]

2. Description of the Related Art As an A / D converter, there is a cascade A / D converter having a small circuit scale, low power consumption and low input capacity.
When the cascade A / D converter is operated by one clock, the operation is performed at high speed, but an error occurs. Therefore, the present inventors have invented a cascade A / D converter that can be operated without error in one clock. This invention is disclosed in Japanese Patent Application Laid-Open No. 9-238077.
No. pp. 147-64.

[0003] Such an apparatus will be described with reference to FIG. The device shown here is a 5-bit A / D converter, and exemplifies a cascade A / D converter that outputs an alternating binary code (hereinafter referred to as a Gray Code).

In the figure, reference numerals 8a to 8d denote comparators, and 9a to 9d.
9e is a latch circuit, 10a to 10c are D / A converters, 1
1a to 11c are subtractors. 13a to 13h are comparators, 14 to 17 are AND circuits (hereinafter, referred to as AND circuits), and 18 to 20 are exclusive OR circuits (hereinafter, EOR circuits).
Called circuit. , 21 to 23 are OR circuits (hereinafter referred to as OR circuits).
Called circuit. ), 24, and 25 are AND circuits (hereinafter, AN)
Called D circuit. ), 100a are analog input signals, 10a
1a is a digital output signal.

The comparators 13a and 13b and the AND circuit 14 constitute a window comparator 50a. The comparators 13c and 13d and the AND circuit 15
Constitutes the window comparator 50b. The comparators 13e and 13f and the AND circuit 16
The comparator 50c is configured. Comparators 13g, 13h
And the AND circuit 17 include a window comparator 50
Construct d. OR circuits 21 to 23 and AND circuit 2
4 and 25 constitute an error correction circuit 51.

The analog input signal 100a is supplied to the comparator 8
a, 13a, the inverting input terminal of the comparator 13b, and the addition input terminal of the subtractor 11a.

The output of the comparator 8a is supplied to a latch circuit 9a, D
The / A converter 10a is connected to one input terminal of the EOR circuit 18, and the output of the D / A converter 10a is connected to the subtraction input terminal of the subtractor 11a.

The outputs of the comparators 13a and 13b are connected to input terminals of an AND circuit 14, respectively, and the output of the AND circuit 14 is connected to one input terminal of an OR circuit 21.
It is connected to the negative logic input terminals of the circuits 15 to 17, 24 and 25.

The output of the subtractor 11a is supplied to comparators 8b and 13
c, the inverting input terminal of the comparator 13d, and the addition input terminal of the subtractor 11b.

The output of the comparator 8b is supplied to the D / A converter 10
b, the other input terminal of the EOR circuit 18, the EOR circuit 19
The output of the D / A converter 10b is connected to a subtraction input terminal of a subtractor 11b.

The outputs of the comparators 13c and 13d are respectively connected to the other two positive logic input terminals of the AND circuit 15, and the output of the AND circuit 15 is connected to one input terminal of the OR circuit 22 and the AND circuit 16 , 17, and 25 are connected to the negative logic input terminals.

Further, the output of the EOR circuit 18 is connected to the other input terminal of the OR circuit 21, and the output of the OR circuit 21 is connected to the latch circuit 9b.

The output of the subtractor 11b is supplied to comparators 8c and 13
e, the inverting input terminal of the comparator 13f, and the adding input terminal of the subtractor 11c.

The output of the comparator 8c is supplied to the D / A converter 10
c, the other input terminal of the EOR circuit 19, the EOR circuit 20
The output of the EOR circuit 19 is connected to the other input terminal of the OR circuit 22. OR
The output of the circuit 22 is connected to the positive logic input terminal of the AND circuit 24, and the output of the AND circuit 24 is connected to the latch circuit 9c.

The outputs of the comparators 13e and 13f are respectively connected to the other two positive logic input terminals of the AND circuit 16, and the output of the AND circuit 16 is connected to one input terminal of the OR circuit 23 and the AND circuit 17 Is connected to the negative logic input terminal.

The output of the subtractor 11c is supplied to comparators 8d and 13
g is connected to the non-inverting input terminal of the comparator 13h.

The output of the comparator 8d is connected to the other input terminal of the EOR circuit 20, and the output of the EOR circuit 20 is
Connected to the other input terminal of R circuit 23. OR circuit 2
The output of the AND circuit 3 is connected to the positive logic input terminal of the AND circuit 25, and the output of the AND circuit 25 is connected to the latch circuit 9d.

The outputs of the comparators 13g and 13h are respectively connected to the other two positive logic input terminals of the AND circuit 17, and the output of the AND circuit 17 is connected to the latch circuit 9e.

The outputs of the latch circuits 9a to 9d are output as digital output signals 101a.

The inverting input terminals of the comparators 8a to 8d are grounded, and the non-inverting input terminals of the comparators 13b, 13d, 13f and 13h receive the voltage of "+ ΔV".
The inverting input terminals of a, 13c, 13e and 13g have "-"
ΔV ”is applied. However,“ ΔV = F
S / 32 "(FS: full scale).

Here, the operation of the device shown in FIG.
This will be described with reference to FIG. FIGS. 8 and 9 show that “−FS / 2” to “+
FIG. 10 is a characteristic curve diagram showing each output or each input with respect to the analog input signal 100a of “FS / 2”.

In the figure, (a) to (d) indicate the outputs of the comparators 8a to 8d, (e) to (h) indicate the outputs of the window comparators 50a to 50d, respectively, and (i) to (h).
(K) is the output of each of the EOR circuits 18 to 20, (l)
To (p) indicate the inputs of the latch circuits 9a to 9e, respectively.

The comparators 8a to 8d respectively include an analog input signal 100a, an output of the subtractor 11a, and a subtractor 11b.
And the zero crossing of the output of the subtractor 11c.

Then, the window comparator 50a
50d output "high level" when the input signal is close to "0" and the output of the preceding window comparator is "low level".

Therefore, the window comparator 50a
Is the analog input signal 100a as shown in FIG.
Outputs a “high level” near “0”.

The window comparator 50b is configured as shown in FIG.
As can be seen from the middle (b), the analog input signal 100a
May output “high level” near “0” and “± FS / 4”, but the analog input signal 100 a
In the vicinity of 0 ", the window comparator 5 in the preceding stage
Since the output of 0a is at "high level", (f) in FIG.
As shown in FIG. 7, only the vicinity of “± FS / 4” becomes “high level”.

The window comparator 50c is shown in FIG.
As can be seen from the middle (c), there is a possibility that "high level" may occur at seven places.
Since the portions where 0a and 50b are "high level" are excluded, they become as shown in FIG. 8 (g).

Similarly, the window comparator 50d
Can be "high level" at 15 locations as can be seen from FIG. 8 (d), but the high level portions of the preceding window comparators 50a to 50c are excluded. (H) is obtained.

Although the outputs of the EOR circuits 18 to 20 output gray codes of intermediate bits in the digital output signal 101a, spike-like noise is generated as shown in (i) to (k) of FIG. You can see that it is. This is because the change of the output of the comparators 8a to 8d from "high level" to "low level" or from "low level" to "high level" is slow.

Here, the error correction circuit 51 corrects the portion where the spike-like noise is generated by the output of the window comparator, thereby obtaining (m) to (m) in FIG.
As shown in (o), the spike-like noise is removed.

That is, the spike noise in FIG. 9 (i) is output from the window comparator 50a, and the spike noise in (j) in FIG.
With the outputs of the comparators 50a and 50b, the spike noise shown in FIG. 9 (k) can be removed by masking with the outputs of the window comparators 50a to 50c.

[0032]

The outputs of the window comparators 50a to 50c of such a device become "high level" in a range (hereinafter referred to as "window width") near the transition of the code, and all the lower levels are output. Has the function of determining the code. First stage window comparator 5
Focusing on 0a, near the transition of the MSB, 2
The bit is forcibly set to “high level”, the third bit,
The 4th bit and LSB (5th bit) are forced to "low level".

The window width for determining each bit does not need to be essentially the same. As shown in FIG. 9 (m), the range in which the second bit is set to “high level” can be allowed up to half of the full scale, and as shown in FIG. 9 (n), the third bit is full scale. Can be tolerated up to 1/4. The permissible window width becomes narrower toward the bottom, and in the LSB, as shown in FIG. 9 (p), it becomes 1/16 of the full scale, that is, 2LSB.

However, since the window comparator 50a for detecting the MSB transition propagates its output downward, the window width must be kept constant. For example, the second bit at the MSB transition is set to "high". The window width when the level is set to “level” is the same as the window width when the LSB is set to the “low level”.

Therefore, when the resolution increases and the window width approaches the noise level, the window
In the worst case, if the comparator 50a malfunctions due to the influence of noise, an error occurs in the code of the second bit.

Accordingly, an object of the present invention is to realize a cascade A / D converter that can prevent occurrence of an error due to noise.

[0037]

SUMMARY OF THE INVENTION The present invention provides a comparator for converting an analog input signal into a digital signal, a latch circuit for holding the output of the comparator, and a converter for converting the output of the comparator into an analog signal again. A D / A converter and this D / A
A cascade A / A configured by cascading a plurality of stages with a subtracter for subtracting the output of the converter from the analog signal.
In the D converter, a synthesizing circuit for synthesizing a changing waveform of the code of the comparator, and a changing waveform of the synthesizing circuit,
A plurality of code change point vicinity detecting means for detecting a change in code of the comparator in two or more stages of code change point vicinity detection widths; and a noise generated at a code change point based on an output of the code change point vicinity detection means. And an error correction circuit for removing the error.

According to the present invention, the synthesizing circuit synthesizes the change waveform of the code of the comparator. The code change point vicinity detecting means detects a code change based on the change waveform of the combining circuit with the width of the code change point vicinity detection means of two or more stages. Then, the error correction circuit removes noise generated at the code change point based on the output of the code change point vicinity detecting means.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of the present invention. Here, the same components as those in FIG. 7 are denoted by the same reference numerals, and description thereof is omitted.

In the figure, 11d to 11f are subtracters, 6
0a to 60c are amplifiers, 61a and 61b are analog multiplexers, 71a to 71h and 72a to 72h are comparators, 25a, 73a to 73h, 74d and 74e are logical product circuits (hereinafter, referred to as AND circuits), and 100b. An analog input signal 101b is a digital output signal.

The amplifiers 60a to 60c and the analog multiplexers 61a and 61b constitute a synthesizing circuit 60. Comparators 71a, 72a and AND circuit 73a
Constitutes a window comparator 70a. The comparators 71b and 72b and the AND circuit 73b constitute a window comparator 70b. Comparators 71c, 72
c and the AND circuit 73c constitute a window comparator 70c. Window comparator 70a ~
70c constitutes one code change point vicinity detecting means.

The comparators 71d and 72d and the AND circuit 73
d and 74d constitute a window comparator 70d. Comparators 71e, 72e and AND circuits 73e, 7
4e constitutes a window comparator 70e.
The window comparators 70d and 70e constitute a code change point vicinity detecting means.

The comparators 71f, 72f and the AND circuit 73
f constitutes a window comparator 70f. The comparators 71g and 72g and the AND circuit 73g constitute a window comparator 70g. The window comparators 70f and 70g constitute code change point vicinity detecting means.

The comparators 71h and 72h and the AND circuit 73
h constitutes a window comparator 70h. The window comparator 70h constitutes a code change point vicinity detecting means.

Regarding the connection relationship, the basic parts are the same, and the different points are as follows. Subtractors 11d to 11
f is provided in place of the subtractors 11a to 11c, and amplifies and outputs it twice.

The analog input signal 100b is supplied to the comparator 8
a, non-inverting input terminals of 71a to 71c, comparators 72a to 72c
72c, an addition input terminal of the subtractor 11d,
The signal is input to the amplifier 60a.

The outputs of the comparators 71a and 72a are connected to input terminals of an AND circuit 73a, respectively.
The output of the circuit 73a is connected to one input terminal of the OR circuit 21. Outputs of the comparators 71b and 72b are respectively connected to input terminals of an AND circuit 73b,
The output of 3b is connected to the negative logic input terminals of the AND circuits 24, 74d, 74e and the select terminal of the analog multiplexer 61a. The outputs of the comparators 71c and 72c are
Each is connected to the input terminal of the AND circuit 73c,
The output of the D circuit 73c is the analog multiplexer 61
b is connected to one select terminal.

The output of the amplifier 60a is input to one input terminal of an analog multiplexer 61a.

The output of the subtractor 11d is supplied to the non-inverting input terminal of the comparator 8b, the addition input terminal of the subtractor 11e,
Connected to the other input terminal of multiplexer 61a.
The output of the analog multiplexer 61a is
non-inverting input terminals d and 71e, inverting input terminals of comparators 72d and 72e, and amplifiers 60b and 60c.

The outputs of the comparators 71d and 72d are connected to an AND circuit 73d, respectively.
Is connected to the positive logic input terminal of the AND circuit 74d, and the output of the AND circuit 74d is connected to one input terminal of the OR circuit 22. The outputs of the comparators 71e and 72e are
Each of the AND circuits 73e is connected to an AND circuit 73e.
e is the positive logic input terminal of the AND circuit 74e,
Connected to the negative logic input terminals of the D circuits 25a and 73f,
The output of the ND circuit 74e is the analog multiplexer 6
1b is connected to the other select terminal. And AN
The output of the OR circuit 23 is connected to the positive logic input terminal of the D circuit 25a, and the output of the AND circuit 25a is connected to the latch circuit 9d.

The amplifiers 60b and 60c are input to the input terminals of the analog multiplexer 61b.

The output of the subtractor 11e is supplied to the non-inverting input terminal of the comparator 8c, the addition input terminal of the subtractor 11f,
The output of the analog multiplexer 61b is connected to the input terminal of the multiplexer 61b,
g and the non-inverting input terminals of the comparators 72f and 72g.

The outputs of the comparators 71f and 72f are connected to positive logic input terminals of an AND circuit 73f, respectively.
The output of the AND circuit 73f is connected to one input terminal of the OR circuit 23. Outputs of the comparators 71g and 72g are connected to input terminals of an AND circuit 73g, respectively.
The output of the circuit 73g is connected to the negative logic input terminal of the AND circuit 73h.

The output of the subtractor 11f is supplied to comparators 8d and 71
h and the non-inverting input terminal of the comparator 72h.

The outputs of the comparators 71h and 72h are connected to positive logic input terminals of an AND circuit 73h, respectively.
The output of the AND circuit 73h is connected to the latch circuit 9e.

The outputs of the latch circuits 9a to 9e are output as a digital output signal 101b.

The non-inverting input terminals of the comparators 72a to 72h have "+ FS / 4" and "+ FS /
8 "," + FS / 16 "," + FS / 4 "," + FS /
8 "," + FS / 4 "," + FS / 8 "," + FS /
4 "are supplied to the inverting input terminals of the comparators 71a to 71h, respectively, as" -FS / 4 "," -FS / 8 ", and" -F ".
S / 16 ","-FS / 4 ","-FS / 8 ","-F
S / 4 "," -FS / 8 ", and" -FS / 4 "are applied, respectively.

The operation of such a device will be described below.
2 to 5 are characteristic curve diagrams showing the operation of the device shown in FIG.

In FIG. 2, (a) is an analog input signal 100b from "-FS / 2" to "+ FS / 2", (b)
Is the output of the comparator 8a, (c) is the output of the subtractor 11d,
(D) is the output of the comparator 8b, (e) is the output of the subtractor 11e, and (f) is the output of the comparator 8c.

In FIG. 3, (g) shows the subtractor 11
f, (h) is the output of the comparator 8d, (i) to (k)
Are AND circuits 73a to 73c.

In FIG. 4, (l) denotes the output of the analog multiplexer 61a, and (m) to (o) denote ANs.
The outputs of the D circuits 74d, 73e, 74e, (p) is the output of the analog multiplexer 61b, and (q), (r) are A
ND circuits 73f and 73g.

Further, in FIG. 5, (s) shows the output of the AND circuit 73h, (t) shows the output of the OR circuit 21,
(U) and (v) show the outputs of the AND circuits 24 and 25a, respectively.

The comparator 8a receives the analog input signal 100b
And outputs the result to the latch circuit 9a, the D / A converter 10a, and the EOR circuit 18. D / A converter 10
a sets the output of the comparator 8a to an analog signal,
Output to 1d. The subtractor 11d outputs the analog input signal 1
The output of the D / A converter 10a is subtracted from 00b, amplified twice, and output.

The window comparator 70a corresponds to FIG.
As shown in FIG. 2 (i), the analog input signal 100b shown in FIG. 2 (a) has a window width “FS / near“ 0 ”.
2 ", a" high level "is output, and the output of the AND circuit 73a is used for removing spike noise of the second bit from the MSB.

The window comparator 70b is arranged as shown in FIG.
As shown in FIG. 2 (j), when the analog input signal 100b shown in FIG. 2 (a) has a window width “FS /
At "4", a "high level" is output, and the output of the AND circuit 73b is used for removing spike noise of the third bit from the MSB.

The window comparator 70c corresponds to FIG.
As shown in FIG. 2 (k), the analog input signal 100b shown in FIG. 2 (a) has a window width “FS /
8 "," high level "is output.

The comparator 8b determines the zero cross of the output of the subtractor 11d, and determines whether the D / A converter 10b and the EOR circuit 1
8 and 19 are output. The D / A converter 10b includes a comparator 8
The output of b is converted into an analog signal and output to the subtractor 11e. The subtractor 11e subtracts the output of the D / A converter 10b from the output of the subtractor 11d, amplifies it by two times, and outputs the result.

The analog multiplexer 61a combines the signal obtained by amplifying the analog input signal 100b by -2 times with the amplifier 60a and the output of the subtractor 11d. That is, the window comparator 70b (AND circuit 73b)
, The output of the amplifier 60a is selected during the "high level" period, and the subtractor 1 shown in FIG.
1d is selected, a change waveform of the code shown in (l) in FIG. 4 is created, and the window comparators 70d and 70d are output.
Enter e.

Then, the window comparator 70d
, The input signal outputs “high level” with a window width of FS / 4 near “0” from the AND circuit 73d. That is, as can be seen from (l) in FIG.
From S / 8 to + 3FS / 8 becomes "high level". Then, as shown in FIG. 4 (m), the window comparator 70b excludes the “high level” section, and the input signal changes “high level” with the window width of FS / 4 near “0” and AND Output from the circuit 74d. And AN
The output of the D circuit 74d is used for removing a spike-shaped noise of the third bit from the MSB.

The window comparator 70e has the configuration shown in FIG.
As shown in the middle (n), the FS /
8 with a window width of 8 and the AND circuit 7
As shown in FIG. 4 (o), the window comparator 70b excludes the "high level" section, and outputs "high level" at the window width of FS / 8 near "0". Is output from the AND circuit 74e. The output of the AND circuit 73e is 4 bits from the MSB.
It is used to remove bit-like spike noise.

The comparator 8c determines the zero crossing of the output of the subtractor 11e, and the D / A converter 10c and the EOR circuit 1
Output to 9 and 20. The D / A converter 10c includes a comparator 8
The output of c is converted to an analog signal and output to the subtractor 11f. The subtractor 11f subtracts the output of the D / A converter 10c from the output of the subtractor 11e, amplifies the result by two times, and outputs the result.

The analog multiplexer 61b outputs the output of the analog multiplexer 61a to the amplifier 60b,
In 60c, the signal multiplied by -2 and +2 respectively and the subtractor 11
and the output of e. That is, the output of the AND circuit 74e of the window comparator 70e is "high level".
2, the output of the amplifier 60b is selected, the output of the window comparator 70c is "high level", the output of the amplifier 60c is selected, and both are "low level", and the subtractor shown in FIG. 11e output,
A change waveform of the code shown in (p) in FIG. 4 is created and input to the window comparators 70f and 70g.

Then, the window comparator 70f
As shown in FIG. 4 (q), the section where the AND circuit 73e of the window comparator 70e excludes the "high level" section from the "high level" of the window width of the FS / 8 where the input signal is near "0" Then, the data is output from the AND circuit 73f. The output of the AND circuit 73f is 4 bits from the MSB.
It is used to remove bit-like spike noise.

The window comparator 70g has the configuration shown in FIG.
As shown in the middle (r), the FS /
"High level" is output from the AND circuit 73g with a window width of 16. The output of the AND circuit 73g is used for LSB noise removal.

The comparator 8d determines the zero cross of the output of the subtractor 11f and outputs the result to the EOR circuit 20.

Then, the window comparator 70h
(AND circuit 73h), as can be seen from (g) in FIG. 3, there is a possibility that it will be "high level" at 15 locations,
Since the portion where the window comparator 70g is "high level" is removed, it becomes as shown in FIG. 5 (s).

As in the prior art, the outputs of the EOR circuits 18 to 20 output gray codes having spike-like noise of intermediate bits in the digital output signal 101b.

Then, the error correction circuit 51 corrects the portion where the spike noise has occurred by the output of the window comparator, and removes the gray code spike noise.

That is, the spike noise in FIG. 9 (i) is output from the window comparator 70a, and the spike noise in (j) in FIG.
With the outputs of the comparators 70b and 70d, the spike noise shown in FIG. 9 (k) can be removed by masking with the outputs of the window comparators 70e and 70f, respectively.

As described above, since the code change waveform including the code change at the preceding stage is created by the synthesizing circuit 60, the window widths of the window comparators 70a to 70h can be set freely, and the window width increases as the upper bits become larger. Can be. That is, the influence of noise can be reduced, and the accuracy can be improved.

Further, since the window comparators 70a to 70g having different window widths are provided at each stage, the window width for removing errors can be maximized for all bits. That is, the influence of noise can be reduced as much as possible, and the accuracy can be improved.

The subtractors 11d to 11f and the amplifier 6
By doubling the gain of 0a to 60c, the voltage accuracy at the subsequent stage can be made easier and the circuit can be simplified. Further, a configuration including the function of an amplifier in the analog multiplexer may be employed.

The present invention may be used not only for a cascade A / D converter that outputs a gray code, but also for a cascade A / D converter that outputs a binary code (binary code). Further, the number of output bits is not limited.

The subtractors 11d to 11f and the amplifier 6
The gain of 0a to 60c is not limited to twice, and the same effect can be obtained if it is larger than 1.

Further, the code change point vicinity detecting means has shown the configuration of the window comparators 70a to 70h, but may have the configuration shown in FIG. That is, the window comparators 70 a to 70 h are configured by the absolute value circuit 12 and the comparator 13.

[0086]

According to the present invention, the following effects can be obtained. According to the first to third, fifth, and sixth aspects, the change waveform of the code including the code change at the preceding stage is created by the synthesizing circuit. It can be set, and the width of the code change point vicinity detection can be increased for the higher bits. That is, the influence of noise can be reduced, and the accuracy can be improved.

Further, since the code change point vicinity detecting means for detecting the code change point vicinity detection width of two or more stages is provided at each stage, the code change point vicinity detection width for error elimination is set to all bits. , Can be as large as possible.
That is, the influence of noise can be reduced as much as possible, and the accuracy can be improved.

According to the fourth aspect, by setting the gains of the subtractor and the amplifier to be larger than 1, the voltage accuracy at the subsequent stage can be made easier and the circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a characteristic curve diagram showing the operation of the device shown in FIG.

FIG. 3 is a characteristic curve diagram showing the operation of the device shown in FIG.

FIG. 4 is a characteristic curve diagram showing the operation of the device shown in FIG.

FIG. 5 is a characteristic curve diagram showing the operation of the device shown in FIG.

FIG. 6 is a block diagram showing another embodiment of the code change point vicinity detecting means.

FIG. 7 is a configuration diagram showing a conventional cascade A / D converter.

8 is a characteristic curve diagram showing the operation of the device shown in FIG.

FIG. 9 is a characteristic curve diagram showing the operation of the device shown in FIG.

[Explanation of symbols]

 8a-8d Comparator 9a-9e Latch circuit 10a-10c A / D converter 11d-11f Subtractor 12 Absolute value circuit 13 Comparator 70a-70h Window comparator 51 Error correction circuit 60 Synthesis circuit 60a-60c Amplifier 61a, 61b Analog multiplexer 100b Analog input signal 101b Digital output signal

Claims (6)

[Claims] A comparator for converting an analog input signal into a digital signal; a latch circuit for holding an output of the comparator; and a D / A for converting an output of the comparator into an analog signal again.
In a cascade A / D converter configured by cascading a plurality of stages of a converter and a subtracter for subtracting the output of the D / A converter from the analog signal, a change waveform of a code of the comparator is synthesized. A plurality of code change point vicinity detecting means for inputting a change waveform of the synthesis circuit and detecting a change in the code of the comparator in two or more stages of code change point vicinity detection widths; A cascade A / D converter, comprising: an error correction circuit for removing noise generated at a change point of the code based on an output of the point proximity detection means. 2. The cascade A / D according to claim 1, wherein said code change point vicinity detecting means increases the width of the code change point vicinity detection of upper bits than lower bits.
converter. 3. A synthesizing circuit comprising: an amplifier which receives an input of a code change point vicinity detecting means of a preceding stage and outputs an inverted output or a non-inverted output with the same gain as that of a subtractor; an output of the amplifier; And the output of the subtractor
Analog output to the code change point vicinity detection means of the own stage
3. The cascade A / D converter according to claim 1, further comprising a multiplexer. 4. The cascade A / D according to claim 3, wherein gains of the subtractor and the amplifier are set to be larger than 1.
converter. 5. The apparatus according to claim 1, wherein said code change point vicinity detecting means comprises a window comparator.
A cascade A / D converter according to any one of claims 1 to 4. 6. The code change point vicinity detecting means includes: an absolute value circuit for inputting a change waveform of a synthesis circuit to obtain an absolute value; and a second comparator for comparing an output of the absolute value circuit. The cascade A / according to claim 1, wherein
D converter.