TWI419274B - Packaging substrate and packaging structure - Google Patents

Packaging substrate and packaging structure Download PDF

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Publication number
TWI419274B
TWI419274B TW097134098A TW97134098A TWI419274B TW I419274 B TWI419274 B TW I419274B TW 097134098 A TW097134098 A TW 097134098A TW 97134098 A TW97134098 A TW 97134098A TW I419274 B TWI419274 B TW I419274B
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Taiwan
Prior art keywords
package
substrate
end portion
layer
package substrate
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TW097134098A
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Chinese (zh)
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TW201011873A (en
Inventor
Chung Jen Tsai
Hung Yi Chang
Chia Cheng Chen
Cheng Hsien Lin
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Zhen Ding Technology Co Ltd
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Publication of TWI419274B publication Critical patent/TWI419274B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating

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  • Carbon And Carbon Compounds (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

封裝基板以及封裝結構 Package substrate and package structure

本發明涉及電路板技術,尤其涉及一種封裝基板以及具有該封裝基板之封裝結構。 The present invention relates to circuit board technology, and in particular to a package substrate and a package structure having the package substrate.

於資訊、通訊及消費性電子產業中,電路板是所有電子產品不可或缺之基本構成要件。隨著電子產品往小型化、高速化方向發展,電路板亦從單面電路板往雙面電路板、多層電路板方向發展。多層電路板由於具有較多佈線面積與較高裝配密度而得到廣泛應用,請參見Takahashi,A.等人於1992年發表於IEEE Trans.on Components,Packaging,and Manufacturing Technology之文獻“High density multilayer printed circuit board for HITAC M~880”。 In the information, communications and consumer electronics industries, circuit boards are an essential component of all electronic products. With the development of electronic products in the direction of miniaturization and high speed, circuit boards have also evolved from single-sided circuit boards to double-sided circuit boards and multilayer circuit boards. Multilayer boards are widely used due to their large wiring area and high assembly density. Please refer to Takahashi, A. et al., 1992, IEEE Trans.on Components, Packaging, and Manufacturing Technology, "High Density Layer printed". Circuit board for HITAC M~880”.

佈線面積之增加、導電線路之細化使得電路板線寬越來越小,線路之電阻愈來愈大,產生之熱量亦愈來愈多。而裝配密度之增加極大地增加電路板上之封裝元件如集成晶片、電阻之數量,亦極大地增加封裝元件產生之熱量。亦即,先前技術之電路板產生較多熱量。惟,先前技術之電路板並不能較快地散熱。此係因為,一方面,電路板導電線路之電阻愈來愈大,導熱性能亦愈來愈弱;另一方面,電路板之絕緣層具有較低之導熱係數,不能有效導熱,更不能有效散熱。 The increase of the wiring area and the refinement of the conductive lines make the circuit board line width smaller and smaller, the resistance of the line becomes larger and larger, and the heat generated is more and more. The increase in assembly density greatly increases the number of package components such as integrated wafers and resistors on the board, and also greatly increases the amount of heat generated by the package components. That is, the prior art circuit board generates more heat. However, prior art boards do not dissipate heat faster. This is because, on the one hand, the resistance of the conductive lines of the circuit board is getting larger and larger, and the thermal conductivity is getting weaker. On the other hand, the insulation layer of the circuit board has a lower thermal conductivity, which cannot effectively conduct heat, and can not effectively dissipate heat. .

有鑑於此,提供一種具有較佳散熱性能之封裝基板以及封裝結構實屬必要。 In view of this, it is necessary to provide a package substrate and a package structure having better heat dissipation performance.

以下將以實施例說明一種封裝基板以及封裝結構。 A package substrate and a package structure will be described below by way of embodiments.

一種封裝基板,依次包括導電層、複合材料層以及金屬基板。該導電層具有導電圖形。該複合材料層具有第一表面與第二表面,該第一表面與金屬基板接觸,該第二表面與第一表面相對。複合材料層包括聚合物基體以及埋設於聚合物基體之奈米碳管陣列,該奈米碳管陣列中奈米碳管之軸向與第一表面之夾角為80~100度之間。 A package substrate comprising a conductive layer, a composite material layer and a metal substrate in sequence. The conductive layer has a conductive pattern. The composite layer has a first surface that is in contact with the metal substrate and a second surface that is opposite the first surface. The composite material layer comprises a polymer matrix and an array of carbon nanotubes embedded in the polymer matrix, wherein the carbon nanotubes have an axial angle between the anode and the first surface of between 80 and 100 degrees.

一種封裝結構,包括封裝元件以及如上該封裝基板,該封裝元件電連接於該導電圖形。 A package structure includes a package component and a package substrate as described above, the package component being electrically connected to the conductive pattern.

本技術方案之封裝基板以及封裝結構中具有金屬基板以及與金屬基板接觸之複合材料層,並且該複合材料層具有生長方向基本垂直於第一表面奈米碳管陣列,從而複合材料層具有優良之導熱性能,可較快地將導電圖形以及封裝元件散發之熱量傳導至金屬基板,並由金屬基板快速散發至外界。 The package substrate and the package structure of the technical solution have a metal substrate and a composite material layer in contact with the metal substrate, and the composite material layer has a growth direction substantially perpendicular to the first surface carbon nanotube array, so that the composite material layer has excellent properties. The thermal conductivity can quickly transfer the conductive pattern and the heat radiated from the package component to the metal substrate, and the metal substrate is quickly dissipated to the outside.

10、20、30‧‧‧封裝基板 10, 20, 30‧‧‧ package substrate

11、31‧‧‧導電層 11, 31‧‧‧ conductive layer

12、32‧‧‧複合材料層 12, 32‧‧‧ Composite layer

13、23、33‧‧‧金屬基板 13, 23, 33‧‧‧ metal substrates

111、211、311‧‧‧導電圖形 111, 211, 311‧‧‧ conductive patterns

1201、2201、3201‧‧‧第一表面 1201, 2201, 3201‧‧‧ first surface

1202、2202、3202‧‧‧第二表面 1202, 2202, 3202‧‧‧ second surface

121、221‧‧‧聚合物基體 121, 221‧‧‧ polymer matrix

122、222‧‧‧奈米碳管陣列 122, 222‧‧‧Nano Carbon Tube Array

1221、2221‧‧‧第一端部 1221, 2221‧‧‧ first end

1222、2222‧‧‧第二端部 1222, 2222‧‧‧ second end

100‧‧‧基底 100‧‧‧Base

14‧‧‧催化劑層 14‧‧‧ catalyst layer

35‧‧‧絕緣層 35‧‧‧Insulation

351‧‧‧通孔 351‧‧‧through hole

36‧‧‧封裝元件 36‧‧‧Package components

37‧‧‧封裝樹脂 37‧‧‧Encapsulation resin

361‧‧‧金屬導線 361‧‧‧Metal wire

圖1為本技術方案第一實施例提供之封裝基板之示意圖。 FIG. 1 is a schematic diagram of a package substrate provided by a first embodiment of the present technical solution.

圖2為本技術方案第一實施例提供之基底之示意圖。 FIG. 2 is a schematic diagram of a substrate provided by a first embodiment of the present technical solution.

圖3為本技術方案第一實施例提供之於基底上形成催化劑層之示意圖。 FIG. 3 is a schematic view showing the formation of a catalyst layer on a substrate according to a first embodiment of the present technical solution.

圖4為本技術方案第一實施例提供之於催化劑層上生長奈米碳管陣列之示意圖。 4 is a schematic view of a carbon nanotube array grown on a catalyst layer according to a first embodiment of the present technology.

圖5為本技術方案第一實施例提供之聚合物基體包覆奈米碳管陣列之第二端部之示意圖。 FIG. 5 is a schematic view showing the second end of the polymer matrix coated carbon nanotube array provided by the first embodiment of the present technical solution.

圖6為本技術方案第一實施例提供之去除基底與催化劑層之示意圖。 FIG. 6 is a schematic diagram of a substrate and a catalyst layer removed according to a first embodiment of the present technical solution.

圖7為本技術方案第一實施例提供之聚合物基體包覆奈米碳管陣列之第一端部之示意圖。 FIG. 7 is a schematic view showing the first end of the polymer matrix coated carbon nanotube array provided by the first embodiment of the present technical solution.

圖8為本技術方案第二實施例提供之封裝基板之示意圖。 FIG. 8 is a schematic diagram of a package substrate according to a second embodiment of the present technology.

圖9為本技術方案第三實施例提供之封裝基板之示意圖。 FIG. 9 is a schematic diagram of a package substrate provided by a third embodiment of the present technical solution.

圖10為本技術方案提供之包括如圖9所示之封裝基板之封裝結構之示意圖。 FIG. 10 is a schematic diagram of a package structure including the package substrate shown in FIG. 9 according to the technical solution.

下面將結合附圖及複數實施例,對本技術方案提供之封裝基板以及封裝結構作進一步之詳細說明。 The package substrate and package structure provided by the present technical solution will be further described in detail below with reference to the accompanying drawings and the embodiments.

請參閱圖1,本技術方案第一實施例提供之封裝基板10依次包括導電層11、複合材料層12以及金屬基板13。該導電層11具有導電圖形111,該導電圖形111用於與封裝元件電連接以實現訊號傳輸與處理。該複合材料層12位於導電層11與金屬基板13之間,具有相對且平行之第一表面1201與第二表面1202。該第一表面1201與金屬基板13接觸,該第二表面1202與導電層11相接觸。複合材料層12用於將第一表面1201之熱量較快地傳導至第二表面1202,從而將來自導電圖形111與封裝元件之熱量較快地傳導至金屬基板13。該金屬基板13由鋁、銅等具有較好導熱性能之金屬材料製成,用於將複合材料層12傳導之熱量快速散發至外界。 Referring to FIG. 1 , the package substrate 10 provided by the first embodiment of the present technical solution includes a conductive layer 11 , a composite material layer 12 , and a metal substrate 13 in sequence. The conductive layer 11 has a conductive pattern 111 for electrical connection with the package component for signal transmission and processing. The composite material layer 12 is located between the conductive layer 11 and the metal substrate 13 and has opposite and parallel first surfaces 1201 and second surfaces 1202. The first surface 1201 is in contact with the metal substrate 13, and the second surface 1202 is in contact with the conductive layer 11. The composite material layer 12 is used to conduct heat from the first surface 1201 to the second surface 1202 faster, thereby transferring heat from the conductive pattern 111 and the package component to the metal substrate 13 faster. The metal substrate 13 is made of a metal material having good thermal conductivity such as aluminum or copper, and is used for quickly dissipating the heat conducted by the composite material layer 12 to the outside.

具體地,該複合材料層12包括聚合物基體121與奈米碳管陣列122。該聚合物基體121可為絕緣之硬性樹脂,如環氧、玻纖布等,亦可為絕緣之柔性樹脂,例如聚醯亞胺(Polyimide,PI)、聚乙烯對苯二甲酸乙二醇酯(Polyethylene Terephtalate,PET)、聚四氟乙烯(Polytetrafluoroethylene,PTFE)、聚硫胺(Polyamide)、聚甲基丙烯酸甲酯(Polymethyl-methacrylate)、聚碳酸酯(Polycarbonate)或聚 醯亞胺-聚乙烯-對苯二甲酯共聚物(Polyamide polyethylene-terephthalate copolymer)等。該奈米碳管陣列122包括多根平行排列之奈米碳管,該多根奈米碳管之軸向與第一表面1201之夾角為80~100度之間。亦即,奈米碳管陣列122之生長方向基本垂直於第一表面1201與第二表面1202。 Specifically, the composite layer 12 includes a polymer matrix 121 and a carbon nanotube array 122. The polymer matrix 121 may be an insulating hard resin such as epoxy, fiberglass cloth, or the like, or an insulating flexible resin such as Polyimide (PI) or polyethylene terephthalate. (Polyethylene Terephtalate, PET), Polytetrafluoroethylene (PTFE), Polyamide, Polymethyl-methacrylate, Polycarbonate or Poly Polyamide polyethylene-terephthalate copolymer, and the like. The carbon nanotube array 122 includes a plurality of carbon nanotubes arranged in parallel, and the axial direction of the plurality of carbon nanotubes is between 80 and 100 degrees from the first surface 1201. That is, the growth direction of the carbon nanotube array 122 is substantially perpendicular to the first surface 1201 and the second surface 1202.

奈米碳管陣列122具有相對之第一端部1221與第二端部1222,該第一端部1221與第二端部1222之間距小於第一表面1201與第二表面1202之間距,即,奈米碳管陣列122之高度小於複合材料層12之厚度。優選地,該奈米碳管陣列之高度為複合材料層厚度之2/3~4/5之間。 The carbon nanotube array 122 has a first end portion 1221 and a second end portion 1222. The distance between the first end portion 1221 and the second end portion 1222 is smaller than the distance between the first surface 1201 and the second surface 1202, that is, The height of the carbon nanotube array 122 is less than the thickness of the composite layer 12. Preferably, the height of the carbon nanotube array is between 2/3 and 4/5 of the thickness of the composite layer.

該奈米碳管陣列122埋設於聚合物基體121。本實施例中,該第一端部1221與第二端部1222均埋設於聚合物基體121內。該第一端部1221靠近第一表面1201且不與第一表面1201相接觸,該第二端部1222靠近第二表面1202且不與第二表面1202相接觸。並且,該第一端部1221與第一表面1201之間距等於第二端部1222與第二表面1202之間距,第一端部1221與第一表面1201之間距可為奈米碳管陣列122高度之1/4~1/8。 The carbon nanotube array 122 is embedded in the polymer matrix 121. In this embodiment, the first end portion 1221 and the second end portion 1222 are embedded in the polymer matrix 121. The first end portion 1221 is adjacent to the first surface 1201 and is not in contact with the first surface 1201. The second end portion 1222 is adjacent to the second surface 1202 and is not in contact with the second surface 1202. Moreover, the distance between the first end portion 1221 and the first surface 1201 is equal to the distance between the second end portion 1222 and the second surface 1202. The distance between the first end portion 1221 and the first surface 1201 may be the height of the carbon nanotube array 122. 1/4~1/8.

由於奈米碳管陣列122不與第一表面1201接觸,因此奈米碳管陣列122與導電圖形111之間絕緣。亦即,導電圖形111與金屬基板13之間並不電導通。另外,由於奈米碳管陣列122之第一端部1221與第一表面1201之間距、第二端部1222與第二表面1202之間距均較小,而奈米碳管陣列122之生長方向即多根奈米碳管之軸向具有良好導熱性能,因此,複合材料層12於奈米碳管陣列122之生長方向上具有良好導熱性能,可較快地將導電圖形111以及電連接於導電圖形111之封裝元件之熱量傳導至金屬基板13,並進一步由金屬基板13散發至外界。 Since the carbon nanotube array 122 is not in contact with the first surface 1201, the carbon nanotube array 122 is insulated from the conductive pattern 111. That is, the conductive pattern 111 and the metal substrate 13 are not electrically connected. In addition, since the distance between the first end portion 1221 of the carbon nanotube array 122 and the first surface 1201 and the distance between the second end portion 1222 and the second surface 1202 are small, the growth direction of the carbon nanotube array 122 is The axial direction of the plurality of carbon nanotubes has good thermal conductivity. Therefore, the composite layer 12 has good thermal conductivity in the growth direction of the carbon nanotube array 122, and the conductive pattern 111 and the electrically conductive pattern can be electrically connected relatively quickly. The heat of the package component of 111 is conducted to the metal substrate 13, and is further radiated to the outside by the metal substrate 13.

本技術方案第一實施例提供之封裝基板10可採用如下步驟製備: The package substrate 10 provided by the first embodiment of the present technical solution can be prepared by the following steps:

第一步,請參閱圖2,提供基底100。基底100可為銅層、鋁層或鎳層等金屬層。基底100之厚度可為2~200微米之間。 In the first step, referring to Figure 2, a substrate 100 is provided. The substrate 100 may be a metal layer such as a copper layer, an aluminum layer, or a nickel layer. The thickness of the substrate 100 can be between 2 and 200 microns.

第二步,請參閱圖3,以電鍍、蒸鍍、濺鍍或者氣相沉積方法於基底100上形成催化劑層14,催化劑層14為鐵、鈷、鎳或及合金等可生長奈米碳管陣列之材料。 In the second step, referring to FIG. 3, a catalyst layer 14 is formed on the substrate 100 by electroplating, evaporation, sputtering or vapor deposition. The catalyst layer 14 is a growthable carbon nanotube such as iron, cobalt, nickel or alloy. The material of the array.

第三步,請參閱圖4,於催化劑層14上生長奈米碳管陣列122。 In the third step, referring to FIG. 4, a carbon nanotube array 122 is grown on the catalyst layer 14.

製備奈米碳管陣列122之方法不限。以化學氣相沈積法製備時,可將形成有催化劑層14之基底100放入反應爐中,於700~1000攝氏度下,通入乙炔、乙烯等碳源氣,從而於催化劑層14上生長出奈米碳管陣列122。奈米碳管陣列122之生長高度可藉由生長時間控制,一般生長高度為1~30微米。奈米碳管陣列122中多根奈米碳管之排列方向較為一致,均基本垂直於催化劑層14。亦即,多根奈米碳管之軸向與催化劑層14之夾角均大致於80~100度之間。 The method of preparing the carbon nanotube array 122 is not limited. When the chemical vapor deposition method is used, the substrate 100 on which the catalyst layer 14 is formed can be placed in a reaction furnace, and a carbon source gas such as acetylene or ethylene is introduced at 700 to 1000 degrees Celsius to grow on the catalyst layer 14. Nano carbon tube array 122. The growth height of the carbon nanotube array 122 can be controlled by growth time, and the growth height is generally 1 to 30 microns. The arrangement of the plurality of carbon nanotubes in the carbon nanotube array 122 is relatively uniform, and is substantially perpendicular to the catalyst layer 14. That is, the angle between the axial direction of the plurality of carbon nanotubes and the catalyst layer 14 is approximately between 80 and 100 degrees.

第四步,形成複合材料層12。 In the fourth step, a composite material layer 12 is formed.

首先,請參閱圖5,以浸塗、塗佈、壓合或其他方式將聚合物基體121施加於奈米碳管陣列122中,使聚合物基體121充分填充奈米碳管陣列122中複數奈米碳管之間之空隙,並包覆奈米碳管陣列122之第二端部1222。 First, referring to FIG. 5, the polymer matrix 121 is applied to the carbon nanotube array 122 by dip coating, coating, pressing or other means, so that the polymer matrix 121 fully fills the plurality of carbon nanotube arrays 122. The gap between the carbon nanotubes covers the second end 1222 of the carbon nanotube array 122.

其次,請參閱圖6,去除基底100以及催化劑層14,從而露出奈米碳管陣列122之第一端部1221。 Next, referring to FIG. 6, the substrate 100 and the catalyst layer 14 are removed to expose the first end portion 1221 of the nanotube array 122.

去除基底100及催化劑層14之方法可為蝕刻法。例如當基底100為銅、催化劑層14為三氧化二鐵時,可用三氯化鐵溶液蝕刻基底100及催化劑層14,從而露出奈米碳管陣列122之第一端部1221。當然,採用其他之基底材料及催化劑層材料時採用相應之蝕刻劑即可。 The method of removing the substrate 100 and the catalyst layer 14 may be an etching method. For example, when the substrate 100 is copper and the catalyst layer 14 is ferric oxide, the substrate 100 and the catalyst layer 14 may be etched with a ferric chloride solution to expose the first end portion 1221 of the carbon nanotube array 122. Of course, when using other base materials and catalyst layer materials, the corresponding etchant can be used.

再次,請參閱圖7,以浸塗、塗佈、壓合或其他方式使聚合物基體121包覆奈米碳管陣列122之第一端部1221,從而獲得奈米碳管陣列122埋設於聚合物基體121內之複合材料層12。 Again, referring to FIG. 7, the polymer substrate 121 is coated with the first end portion 1221 of the carbon nanotube array 122 by dip coating, coating, pressing or otherwise, thereby obtaining the carbon nanotube array 122 buried in the polymerization. Composite layer 12 within substrate 121.

第五步,將導電層11、金屬基板13分別壓合於複合材料層12之第二表面1202、第一表面1201,從而獲得封裝基板10,如圖1所示。 In the fifth step, the conductive layer 11 and the metal substrate 13 are respectively pressed against the second surface 1202 of the composite material layer 12 and the first surface 1201, thereby obtaining the package substrate 10, as shown in FIG.

當然,將導電層11、金屬基板13壓合於複合材料層12之前或之後,還可包括將導電層11形成導電圖形111之步驟。將導電層11形成導電圖形111之步驟可藉由圖像轉移法以及蝕刻工序實現。 Of course, before or after the conductive layer 11 and the metal substrate 13 are pressed against the composite material layer 12, the conductive layer 11 may be further formed into a conductive pattern 111. The step of forming the conductive layer 11 into the conductive pattern 111 can be realized by an image transfer method and an etching process.

請參閱圖8,本技術方案第二實施例提供之封裝基板20與第一實施例提供之封裝基板10大致相同,其不同之處在於:該奈米碳管陣列222之第一端部2221與第一表面2201相齊平,而第二端部2222則埋設於聚合物基體221內且與第二表面2202有一定間距。從而,導電圖形211與金屬基板23之間絕緣並具有良好之導熱性能。 Referring to FIG. 8 , the package substrate 20 provided by the second embodiment of the present invention is substantially the same as the package substrate 10 provided by the first embodiment, except that the first end portion 2221 of the carbon nanotube array 222 is The first surface 2201 is flush and the second end 2222 is embedded in the polymer matrix 221 and spaced from the second surface 2202. Thereby, the conductive pattern 211 is insulated from the metal substrate 23 and has good thermal conductivity.

另外,亦可使得奈米碳管陣列222中之第二端部2222與第二表面2202齊平,而第一端部2221埋設於聚合物基體221內且與第一表面2201有一定間距,同樣可獲得良好之絕緣與導熱效果。 In addition, the second end portion 2222 of the carbon nanotube array 222 may be flush with the second surface 2202, and the first end portion 2221 is embedded in the polymer base 221 and spaced apart from the first surface 2201. Good insulation and thermal conductivity are obtained.

請參閱圖9,本技術方案第三實施例提供之封裝基板30與第一實施例提供之封裝基板20大致相同,其不同之處在於:該封裝基板30還包括位於導電層31與複合材料層32之間之絕緣層35,該複合材料層32之第一表面3201與金屬基板33相接觸,第二表面3202與絕緣層35相接觸。該絕緣層35具有一與導電圖形311相對應之通孔351,該通孔351用於放置封裝元件,以便於封裝基板30上封裝封裝元件。 Referring to FIG. 9 , the package substrate 30 provided by the third embodiment of the present invention is substantially the same as the package substrate 20 provided by the first embodiment, except that the package substrate 30 further includes a conductive layer 31 and a composite material layer. An insulating layer 35 between 32, the first surface 3201 of the composite material layer 32 is in contact with the metal substrate 33, and the second surface 3202 is in contact with the insulating layer 35. The insulating layer 35 has a through hole 351 corresponding to the conductive pattern 311 for placing a package component to package the package component on the package substrate 30.

本技術方案還提供一種包括上述封裝基板之封裝結構。 The technical solution also provides a package structure including the above package substrate.

請參閱圖10,本技術方案提供之封裝結構4包括如第三實施例所示之封裝基板30、封裝元件36以及封裝樹脂37。 Referring to FIG. 10, the package structure 4 provided by the technical solution includes a package substrate 30, a package component 36, and a package resin 37 as shown in the third embodiment.

該封裝元件36為用於實現特定處理功能之器件,其可為積體電路晶片,亦可為電容電感元件,還可為記憶體或其他器件。 The package component 36 is a device for implementing a specific processing function, and may be an integrated circuit chip, a capacitive inductor component, or a memory or other device.

將封裝元件36封裝於封裝基板30之方法亦不限。本實施例中,該封裝元件36藉由封裝樹脂37固定於通孔351內,與複合材料層32接觸,並藉由金屬導線361與導電圖形311電連接,從而實現封裝元件36與封裝基板30間之訊號傳輸與處理。 The method of packaging the package component 36 on the package substrate 30 is not limited. In this embodiment, the package component 36 is fixed in the through hole 351 by the encapsulation resin 37, is in contact with the composite material layer 32, and is electrically connected to the conductive pattern 311 by the metal wire 361, thereby implementing the package component 36 and the package substrate 30. Signal transmission and processing.

該封裝元件36工作時,封裝元件36以及導電圖形311產生之熱量可藉由複合材料層32中之奈米碳管陣列較快地傳輸至金屬基板33,並由金屬基板33快速散發至外界。 When the package component 36 is in operation, the heat generated by the package component 36 and the conductive pattern 311 can be quickly transferred to the metal substrate 33 by the carbon nanotube array in the composite material layer 32, and quickly dissipated to the outside by the metal substrate 33.

當然,封裝結構4除如本實施例所示包括如圖9所示之封裝基板30外,亦可包括如圖1或圖8所示之封裝基板,同樣可具有較好散熱效果。 Of course, the package structure 4 includes the package substrate 30 as shown in FIG. 9 as shown in FIG. 9 , and may also have a better heat dissipation effect.

綜上所述,本發明確已符合發明專利之要件,遂依法提出專利申請。惟,以上所述者僅為本發明之較佳實施方式,自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士爰依本發明之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。 In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

10‧‧‧封裝基板 10‧‧‧Package substrate

11‧‧‧導電層 11‧‧‧ Conductive layer

12‧‧‧複合材料層 12‧‧‧Composite layer

13‧‧‧金屬基板 13‧‧‧Metal substrate

111‧‧‧導電圖形 111‧‧‧Electrical graphics

1201‧‧‧第一表面 1201‧‧‧ first surface

1202‧‧‧第二表面 1202‧‧‧ second surface

121‧‧‧聚合物基體 121‧‧‧ polymer matrix

122‧‧‧奈米碳管陣列 122‧‧‧Nano Carbon Tube Array

1221‧‧‧第一端部 1221‧‧‧ first end

1222‧‧‧第二端部 1222‧‧‧second end

Claims (10)

一種封裝基板,其依次包括導電層、複合材料層以及金屬基板,該導電層具有導電圖形,該複合材料層具有第一表面與第二表面,該第一表面與金屬基板接觸,該第二表面與第一表面相對,複合材料層包括聚合物基體以及埋設於聚合物基體之奈米碳管陣列,該奈米碳管陣列中奈米碳管之軸向與第一表面之夾角為80~100度之間。 A package substrate, which in turn comprises a conductive layer, a composite material layer and a metal substrate, the conductive layer having a conductive pattern, the composite material layer having a first surface and a second surface, the first surface being in contact with the metal substrate, the second surface Opposite the first surface, the composite layer comprises a polymer matrix and an array of carbon nanotubes embedded in the polymer matrix, wherein the angle between the axial direction of the carbon nanotubes and the first surface is 80-100 Between degrees. 如申請專利範圍第1項所述之封裝基板,其中,該奈米碳管陣列之高度為複合材料層厚度之2/3~4/5之間。 The package substrate according to claim 1, wherein the height of the carbon nanotube array is between 2/3 and 4/5 of the thickness of the composite layer. 如申請專利範圍第1項所述之封裝基板,其中,該奈米碳管陣列具有相對之第一端部與第二端部,該第一端部與第二端部均位於第一表面與第二表面之間。 The package substrate of claim 1, wherein the carbon nanotube array has opposite first and second ends, the first end and the second end being located on the first surface and Between the second surfaces. 如申請專利範圍第3項所述之封裝基板,其中,該第一端部與第二端部均埋設於聚合物基體內,該第一端部靠近第一表面,該第二端部靠近第二表面。 The package substrate of claim 3, wherein the first end portion and the second end portion are embedded in the polymer matrix, the first end portion is adjacent to the first surface, and the second end portion is adjacent to the first end portion. Two surfaces. 如申請專利範圍第3項所述之封裝基板,其中,該第一端部與第一表面相齊平,該第二端部埋設於聚合物基體內。 The package substrate of claim 3, wherein the first end portion is flush with the first surface, and the second end portion is embedded in the polymer matrix. 如申請專利範圍第3項所述之封裝基板,其中,該第二端部與第二表面相齊平,該第一端部埋設於聚合物基體內。 The package substrate according to claim 3, wherein the second end portion is flush with the second surface, and the first end portion is embedded in the polymer matrix. 如申請專利範圍第1項所述之封裝基板,其中,該封裝基板還包括一個絕緣層,該絕緣層設置於導電層與複合材料層之間,該第二表面與該絕緣層接觸。 The package substrate of claim 1, wherein the package substrate further comprises an insulating layer disposed between the conductive layer and the composite layer, the second surface being in contact with the insulating layer. 如申請專利範圍第7項所述之封裝基板,其中,該絕緣層具有一通孔,該通孔用於放置封裝元件。 The package substrate of claim 7, wherein the insulating layer has a through hole for placing the package component. 一種封裝結構,包括封裝元件以及如申請專利範圍第1項所述之封裝基板,該封裝元件電連接於該導電圖形。 A package structure comprising a package component and a package substrate as described in claim 1 , the package component being electrically connected to the conductive pattern. 如申請專利範圍第9項所述之封裝結構,其中,該封裝元件藉由封裝樹脂固定於封裝基板,並藉由金屬導線與導電圖形電連接。 The package structure of claim 9, wherein the package component is fixed to the package substrate by a sealing resin and electrically connected to the conductive pattern by a metal wire.
TW097134098A 2008-09-05 2008-09-05 Packaging substrate and packaging structure TWI419274B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200517042A (en) * 2003-11-04 2005-05-16 Hon Hai Prec Ind Co Ltd Heat sink
US20060118791A1 (en) * 2004-03-12 2006-06-08 Hon Hai Precision Industry Co., Ltd. Thermal interface material and method for manufacturing same
TW200637475A (en) * 2005-04-15 2006-10-16 Hon Hai Prec Ind Co Ltd Thermal interface material and method of making the same
TW200637469A (en) * 2005-04-08 2006-10-16 Hon Hai Prec Ind Co Ltd Thermal interface material and method of making the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200517042A (en) * 2003-11-04 2005-05-16 Hon Hai Prec Ind Co Ltd Heat sink
US20060118791A1 (en) * 2004-03-12 2006-06-08 Hon Hai Precision Industry Co., Ltd. Thermal interface material and method for manufacturing same
TW200637469A (en) * 2005-04-08 2006-10-16 Hon Hai Prec Ind Co Ltd Thermal interface material and method of making the same
TW200637475A (en) * 2005-04-15 2006-10-16 Hon Hai Prec Ind Co Ltd Thermal interface material and method of making the same

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