TWI405256B - Wafer bevel etching apparatus and the related method of flatting a wafer - Google Patents

Abstract

The wafer bevel etching apparatus of the present invention includes a wafer-protecting mask to cover parts of a wafer. A central region and a wafer bevel region surrounding the central region are defined on the wafer. The wafer-protecting mask includes a center sheltering region and at least one wafer bevel sheltering region. The center sheltering region can completely shelter the central region of the wafer, and the wafer bevel sheltering region extends from the outside edge of the center sheltering region, shelters parts of the wafer bevel region, and exposes the other parts of the wafer bevel region.

Description

Edge etching machine and related wafer planarization method

The present invention relates to an edge etching machine and related wafer planarization method, and more particularly to a wafer planarization method using an edge etching machine.

In the fabrication of semiconductor devices, it is often necessary to use a plurality of materials such as a polysilicon layer, a metal interconnect layer, and a low dielectric material layer to form a desired semiconductor device or integrated circuit. However, in general, the film deposited on the wafer often has the problem of uneven thickness or the difference in surface level, so that the surface of the integrated circuit exhibits a steep topography, which increases the follow-up. Difficulties in performing a pattern transfer process, a chemical mechanical polishing (CMP) process, or other film deposition processes. Therefore, after entering the deep submicron semiconductor process, the semiconductor industry mostly uses a CMP process with better planarization effect to uniformly polish a target thin film having an irregular surface on a semiconductor wafer, so that the semiconductor wafer is After the CMP process, it can have a flat and regular surface to achieve full planarization of the surface of the semiconductor wafer to ensure the yield of subsequent processes.

In the conventional process, the problem of uneven thickness of the film is particularly noticeable near the wafer bevel, and tends to cause the wafer near the crystal edge to be particularly thick. Even if the CMP process can be performed after the deposition process, the thick film at the edge of the crystal can hinder the distribution of the polishing slurry in the CMP process and affect the stress distribution when the pad is in contact. Cloth, and the conventional CMP machine itself has its limitations, so the CMP process can not effectively control the edge topography of the wafer edge, so that the edge of the wafer still presents a steep side profile. Profile).

Please refer to FIG. 1 , which is a schematic diagram showing the relationship between the film thickness of a wafer formed by a conventional method. Wherein, the horizontal coordinate of the schematic diagram indicates the distance from each part of the wafer to the center of the wafer. The full scale of the schematic diagram indicates the thickness of the film layer of the wafer, and the wafer shown in FIG. 1 passes through an inner dielectric layer ( Inter-layer dielectric, ILD) film deposition process, a CMP process and a wafer edge cleaning (WBR) film thickness. As shown in Fig. 1, the film thickness of the crystal edge and the film thickness of the central region may differ by 800 angstroms. Thicker crystal edges not only affect the CMP process, but also many edge defects near the edge of the wafer. These edge defects may affect the subsequent process, making the subsequent fabrication of the device or structure also defective. For example, for the formation process of the contact plug, when the etching process of the contact window is performed, since the film thickness at the crystal edge is deep, the contact window at the crystal edge is insufficiently etched, so that the contact plug is not Will be electrically connected to the underlying components to form an open defect. On the other hand, edge defects near the edge of the wafer may directly affect subsequent etching processes or other deposition processes. For example, when the film thickness at the edge of the crystal is deeper, the etching process usually produces more undesired nodules (nodule). )phenomenon.

In view of this, the conventional film layer manufacturing method may cause the product wafer to be difficult to pass the wafer acceptance test (WAT) to reduce the yield (yield). Still to be further improved. How to make a film with good thickness and surface topography is still a major issue in the field.

Therefore, one of the main objects of the present invention is to provide an edge etching machine to improve product yield and avoid the problem of unclear mark recognition during etching.

In accordance with an embodiment of the present invention, the present invention provides an edge etching machine that includes a wafer-protecting mask that covers a portion of a surface of a wafer. A central region and a crystal edge region surrounding the central region are defined on the wafer. The wafer shield mask includes a central masking region and at least one crystal edge masking region. The central masking area completely covers the central area of the wafer, and the crystal edge shielding area extends outward from the outer edge of the central shielding area, covers a part of the crystal edge area of the wafer, and exposes the rest of the crystal edge area. .

In accordance with another preferred embodiment of the present invention, the present invention further provides a method of planarizing a wafer. First, at least one wafer is provided. The wafer includes a substrate and at least one dielectric layer on the substrate, and the wafer defines a central region and a crystal edge region surrounding the central region. Then, an edge etching process is performed. The edge etching process does not etch the central region and a portion of the edge region of the wafer, but etches the dielectric layer located in the remaining portion of the edge region. Then, a chemical mechanical polishing process is performed on the wafer.

In order to further understand the features and technical contents of the present invention, please refer to the following A detailed description of the invention and the accompanying drawings. However, the drawings are for reference only and are not intended to limit the invention.

2 to 8 are schematic views showing a method of planarizing a wafer 10 according to a first preferred embodiment of the present invention, wherein the same elements or portions are denoted by the same reference numerals. It should be noted that the drawings are for illustrative purposes only and are not drawn to the original dimensions. Referring first to Figure 2, a bottom schematic view of wafer 10 is shown. As shown in FIG. 2, at least one wafer 10 is provided. A central region 16 is defined on the wafer 10, and a bevel region 18 surrounding the central region 16 at the edge of the wafer 10 and having a width of about several millimeters. Taking a 12-inch wafer as an example, the width of the crystal edge region 18 is between about 1 mm and 3 mm, for example 2 mm. The wafer 10 includes a substrate 12, and the substrate 12 may include at least one semiconductor component (not shown), such as some components of the integrated circuit, and a plurality of wafer marks 20 may be disposed in the crystal edge region 18 of the substrate 12. For example, the wafer mark 20 may include a laser code 22, a positioning notch 24, a positioning mark (not shown), an alignment mark (not shown), or any element to be protected. The laser code 22 can be used by an identification device to identify the wafer 10, and can include information such as the batch number of the wafer and the wafer identification number, which is usually laser-sintered on the surface of the wafer 10, and the positioning gap 24 can be used to coordinate the coordinates of the wafer 10 in various semiconductor processes.

FIG. 3 is a cross-sectional view of the wafer 10. As shown in FIG. 3, at least the deposition process, the coating process, or the spin coating process may be used to form at least the substrate 12 on the substrate 12. A dielectric layer 14. The wafer 10 has a top surface 10a and a bottom surface 10b according to the overall outline of the wafer 10. The semiconductor component of the wafer 10 is generally disposed adjacent to the upper surface 10a of the wafer 10 to define a plurality of crystal grains, and the wafer mark 20 may be disposed on the lower surface 10b of the wafer 10 without the dielectric layer 14. Covered. In this embodiment, the dielectric layer 14 is a layer of material to be ground, and the dielectric layer 14 in the edge region 18 may be thicker than the dielectric layer 14 located in the central region 16. In addition, the dielectric layer 14 can be an ILD layer directly covering the semiconductor device of the wafer 10. However, the edge etching method of the present invention is not limited to etching the ILD layer, but can be applied to any crystal edge. The etched material layer, such as dielectric layer 14, may also be an intermetal dielectric (IMD) layer.

Please refer to FIG. 4, FIG. 5 and FIG. 6 together. FIG. 4 is a schematic cross-sectional view showing an edge etching process, and FIG. 5 is a crystal edge etching shown in FIG. A bottom view of the process, and FIG. 6 is a schematic view of the masking process of the edge etching process shown in FIG. As shown in FIG. 4, wafer 10 can be loaded into one of the edge etching machines 40 provided by the present invention to perform an edge etching process. The edge etching machine 40 includes a first wafer-protecting mask 44 for covering a portion of the lower surface 10b of the wafer 10. The first wafer protection mask 44 can include a first stopper 50, a first guard ring 52 and at least one first protrusion 54 disposed in an etching reaction chamber 42. In this embodiment, the first stopper 50 can be a pedestal for mounting the wafer 10. For example, the first stopper 50 can be an electrostatic chuck (E-chuck). The wafer 10 is adsorbed and fixed. The first guard ring 52 can surround the first block 50 and the first guard ring The top level of 52 may be lower than or equal to the level of the bearing surface 50a of the first block 50 such that the first guard ring 52 may properly cover a portion of the lower surface 10b of the wafer 10. The first protrusion 54 can extend outward from the outer edge of the first guard ring 52 to the circumference of the wafer 10. The first retaining ring 52 and the first protruding portion 54 may be integrally formed and may be collectively referred to as a bottom pedestal ring.

Referring to FIG. 4, FIG. 5 and FIG. 6, the first block 50 and the first guard ring 52 of FIG. 4 can form a central shield of the first wafer guard mask 44 of FIGS. 5 and 6. The region 46, and the first protrusion 54 of FIG. 4, can form the edge masking region 48 of the first wafer guard mask 44 of FIGS. 5 and 6. As shown in FIGS. 5 and 6, the first wafer shield mask 44 includes a central masking region 46 and at least one crystal edge masking region 48. The central shielding region 46 can cover the central region 16 of the wafer 10, and the crystal edge shielding region 48 can extend outward from the outer edge of the central shielding region 46 to the circumference of the wafer 10, covering a portion of the crystal edge region 18, And the remaining crystal edge regions 18 to be etched are exposed. Therefore, the edge etching process does not etch into the central region 16 of the wafer 10 and the portion of the edge region 18, while etching the dielectric layer (not shown) located in the remainder of the edge region 18. For example, the crystal edge masking region 48 of the first wafer shield mask 44 can cover the laser code 22 of the wafer edge region 18 of the wafer 10. The size, shape and position of the central shielding area 46 may be arranged corresponding to the central area 16. Preferably, the edge of the central shielding area 46 has a relative distance from the edge of the central area 16 of 0.25 mm or less, but is not limited thereto.

In addition, referring to FIG. 4, the edge etching machine 40 further includes a second stopper 60, a second guard ring 62, a first electrode 64, a second electrode 66, and an etching gas supply line 68. And disposed in the etching reaction chamber 42. The second stopper 60 may be disposed above the first stopper 50 and spaced apart from the first stopper 50 by a predetermined interval to cover a portion of the upper surface 10a of the wafer 10. The second guard ring 62 can surround the second block 60, and the bottom level of the second guard ring 62 can be equal to the bottom level of the second block 60, so that the second guard ring 62 can properly cover the wafer 10. Upper surface 10a. The second stopper 60 and the second guard ring 62 can completely cover the upper surface 10a of the wafer 10 located in a central region (not shown). The first stopper 50, the first retaining ring 52, the first protruding portion 54, the second stopper 60 or the second retaining ring 62 may all comprise a ceramic material, and a part of the surface thereof may be further covered with a metal film. For example, yttrium oxide (Y ₂ O ₃ ) is used to increase the etching resistance. The first retaining ring 52 and the second retaining ring 62 are detachably disposed around the first stopper 50 and the second stopper 60. The etching gas supply line 68 may provide an etching gas 70 to etch the dielectric layer 14, and the first electrode 64 and the second electrode 66 may provide a voltage difference to perform the aforementioned edge etching process.

FIG. 7 is a schematic cross-sectional view of the wafer 10 after the edge etching process. As shown in Fig. 7, the present invention can reduce the thickness of the dielectric layer 14 at the edge region 18, reduce the edge defects of the crystal region 18, and also protect a specific region of the wafer. For example, the crystal edge masking region 48 of the first wafer guard mask 44 can cover the laser encoding 22 of the wafer 10, thereby preventing the laser encoding 22 from being etched and unrecognizable. It should be noted that after the intergranular etching process, the dielectric layer 14 in the intergranular region 18 may be similar to the thickness of the dielectric layer 14 located in the central region 16, and may be larger than the dielectric layer 14 located in the central region 16. Thinner, can also be located in the center Dielectric layer 14 in region 16 is thicker and is not limited by the illustration. In addition, the crystal edge masking region 48 of the first wafer guard mask 44 is not limited to masking only the wafer mark 20, but can be used to mask any portion of the wafer 10 that does not require a process reaction.

Then, as shown in FIG. 8, a chemical mechanical polishing (CMP) process is performed on which a slurry (slurry, not shown) is added to the upper surface 10a of the wafer 10, and then polished according to the specifications of the product. The dielectric layer 14 on the surface 10a is of a predetermined thickness. Then, deionized water (DI water) can be used as a cleaning liquid (not shown), and a surface cleaning process is performed on the upper surface 10a of the wafer 10 to completely remove the upper surface of the wafer 10. The residue of the dielectric layer 14 on 10a and the residual slurry.

Since the edge etching process of the present invention can effectively reduce the thickness of the dielectric layer 14 of the edge region 18, the dielectric layer 14 of the edge region 18 can be prevented from obstructing the distribution of the polishing slurry of the CMP process, and the edge region 18 is avoided. The dielectric layer 14 affects the stress distribution when the pads are in contact to enhance the planarization effect of the CMP process. In addition, since the present invention can reduce the thickness of the dielectric layer 14 of the intergranular region 18, subsequent CMP processes can use more abrasive slurry and/or provide greater under-drawing pressure, thereby shortening the CMP process. Process time. In this way, the invention can not only improve the planarization effect of the CMP process, effectively control the edge topography of the wafer edge, but also reduce the edge defects of the crystal edge region 18, thereby improving the product yield and avoiding etching. Mark the problem of unclear identification.

The first wafer guard mask 44 of the foregoing embodiment covers a portion of the lower surface 10b of the wafer 10, but is not limited thereto. In other embodiments, the wafer shield of the present invention may also cover a portion of the upper surface of the wafer. 9 and 10, FIG. 9 and FIG. 10 are schematic views showing a method of planarizing a wafer 10 according to a second preferred embodiment of the present invention, wherein the same elements or portions are denoted by the same reference numerals. FIG. 9 is a cross-sectional view showing a process of performing an edge etching process, and FIG. 10 is a schematic view showing a state of shielding of the edge etching process shown in FIG. As shown in FIGS. 9 and 10, after the dielectric layer 14 is deposited, the wafer 10 can be loaded into one of the edge etching machines 140 provided by the present invention to perform an edge etching process. The main difference in the foregoing embodiment is that one wafer mark 20 of the wafer 10 can be disposed in the crystal edge region 18 of the upper surface 10a of the wafer 10, and the edge etching machine 140 includes a second crystal. A circular shield 144 is provided to cover a portion of the upper surface 10a of the wafer 10.

As shown in FIG. 9 , the second wafer protection mask 144 can include a second stopper 160 , a second guard ring 162 and at least one second protrusion 154 disposed in an etching reaction chamber 42 . In this embodiment, the second stopper 160 is disposed above the wafer 10 to cover a portion of the upper surface 10a of the wafer 10. The second guard ring 162 can surround the second block 160, and the bottom level of the second guard ring 162 can be equal to the bottom level of the second block 160, so that the second guard ring 162 can properly cover the wafer 10. Upper surface 10a. The second stop 160 and the second guard ring 162 can completely cover the upper surface 10a of the wafer 10 located in the central region 16. The second protrusion 154 may extend outward from the outer edge of the second guard ring 162 to the circumference of the wafer 10. Second guard ring 162 and second The protrusion 154 can be an integrally formed design and can be collectively referred to as a top pedestal ring.

In addition, the edge etching machine 140 further includes a first stopper 150, a first guard ring 152, a first electrode 64, a second electrode 66 and an etching gas supply line 68 disposed in the etching reaction chamber 42. Inside. The first stopper 150 may be disposed under the second stopper 160 and spaced apart from the second stopper 160 by a predetermined interval. The first stopper 150, the first retaining ring 152, the second retaining block 160, the second retaining ring 162 or the second protruding portion 154 may all comprise a ceramic material, and a part of the surface thereof may be further covered with a metal film. The first stop 150 and the first guard ring 152 may cover a portion of the lower surface 10b of the wafer 10.

As shown in FIG. 10, the central masking region 146 can cover the central region 16 of the upper surface 10a of the wafer 10, and the crystal edge masking region 148 can extend outwardly from the outer edge of the central masking region 146 to the wafer 10. The circumference of the cover portion is located at the edge region 18 of the upper surface 10a of the wafer 10 and exposes the remaining edge regions 18 of the upper surface 10a. For example, the edge masking region 148 of the second wafer shield 144 can cover at least one wafer mark 20 of the upper surface 10a of the wafer 10. In the case of a positioned wafer 10, the wafer mark 20 at this time may be at a 90 degree angle, a 180 degree angle, and/or a 270 degree angle with the positioning notch 24 of the wafer 10. The two protrusions 154 may be disposed corresponding to the position of the wafer mark 20 to be protected, and may even directly cover the positioning notch 24 of the wafer 10. Referring to FIG. 9 and FIG. 10, the second block 160 and the second guard ring 162 of FIG. 9 can form the central shielding area 146 of the second wafer shield 144 of FIG. 10, and FIG. 9 The second protrusion 154 can form the 10th The crystal edge shielding area 148 of the second wafer guard mask 144 is shown.

It should be noted that one of the main features of the wafer protective mask of the present invention is that it can shield the central region and a portion of the crystal edge region of the wafer, and expose the remaining crystal edge regions, but does not need to be subjected to the aforementioned first crystal. Limitations of the circular shield 44 and the second wafer shield 144. In other embodiments, the shape, position, width, length, level, thickness, angle, or number of the guard ring and the protrusion may be adjusted according to the process requirements, and the protrusion may extend beyond the circumference of the wafer, or It is also possible not to touch the circumference of the wafer. For example, in the same edge etching process, a plurality of protrusions may be simultaneously used to shield a portion of the upper surface and a portion of the lower surface of the wafer. Alternatively, the shape of the wafer shield can include a wafer having a circular central masking region and an outwardly extending crystal edge masking region, or a wafer having a substantially circular and exposed edge. Protective cover. Please refer to FIG. 11. FIG. 11 is a schematic view showing the shielding state of the edge etching process according to the third preferred embodiment of the present invention. As shown in FIG. 11, the wafer guard mask 244 of the third embodiment is disposed substantially corresponding to the entire wafer 10, and can shield the upper surface 10a or the lower surface 10b of the wafer 10. The wafer shield 244 has at least one edge exposed 274, for example, located above the locating notch 24 of the wafer 10, at a 90 degree angular position of the wafer 10, at an angular position of 180 degrees, and/or at an angular position of 270 degrees. and many more. In addition, it should be noted that the crystal edge exposed notch 274 does not have to have a concave shape as shown in FIG. 11 , as long as it is retracted relative to the edge of the wafer, the degree of retraction may need to be adjusted according to the process, for example, a partial arc may be used. Replace with an arc with a large radius of curvature.

In addition, the present invention can also be protected by a non-etching fluid that does not erode wafer 10. The specific area of the wafer 10 is not etched. Referring to FIG. 12, there is shown a schematic diagram of a method for planarizing a wafer 10 according to a fourth preferred embodiment of the present invention, wherein the same elements or portions are denoted by the same reference numerals. As shown in FIG. 12, the main difference in the foregoing embodiment is that the edge etching machine 240 herein may include at least one nozzle 202 disposed toward a portion of the crystal grain region 18 of the wafer 10. At least one non-etching fluid 204 is provided and the non-etching fluid 204 is contacted with the crystal edge region 18 of the wafer 10. The edge etching machine 240 can further include a first block 50, a first guard ring 52, a second block 60, a second guard ring 62, a first electrode 64, a second electrode 66 and a first An etching gas supply line 68 is provided in the etching reaction chamber 42. In the present embodiment, the nozzle 202 can be disposed toward the laser code 22 located within the crystal edge region 18 of the lower surface 10b of the wafer 10. As such, the present invention can adjust the flow rate of the nozzle 202 and the non-etching fluid 204 such that the non-etching fluid 204 can cover the surface of the laser encoding 22 such that the etching gas 70 does not contact the laser encoding 22. Therefore, the present invention can reduce the thickness of the dielectric layer 14 at the edge region 18, reduce the edge defects of the edge region 18, and also protect a specific region of the wafer. It should be noted that the nozzle 202 of the third embodiment may also be incorporated into the edge etching machine 40 or the edge etching machine 140 as an aid to the edge etching process.

In summary, the present invention has the following advantages. First, the edge etching process of the present invention can effectively reduce the thickness of the dielectric layer in the edge region. Therefore, the present invention can not only reduce the edge defects of the crystal edge region 18, but also prevent the material layer thickness of the crystal edge region from hindering the operation effect of the subsequent process. In addition, the present invention can also protect a specific area of the wafer while etching, and avoid etching of wafer marks such as laser coding. Unrecognizable. In view of this, the present invention can effectively control the shape of the edge of the wafer, improve the yield of the product, and avoid the problem of unclear mark recognition during etching.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧ wafer

10a‧‧‧ upper surface

10b‧‧‧ lower surface

12‧‧‧Base

14‧‧‧Dielectric layer

16‧‧‧Central area

18‧‧‧ crystal edge area

20‧‧‧ Wafer Marking

22‧‧‧Laser coding

24‧‧‧ Positioning gap

40‧‧‧Edge etching machine

42‧‧‧etching reaction chamber

44‧‧‧First wafer protective mask

46‧‧‧Central shelter area

48‧‧‧ crystal edge shelter

50‧‧‧First stop

50a‧‧‧bearing surface

52‧‧‧First guard ring

54‧‧‧First protrusion

60‧‧‧second stop

62‧‧‧second guard ring

64‧‧‧First electrode

66‧‧‧second electrode

68‧‧‧etching gas supply pipeline

70‧‧‧etching gas

140‧‧‧Edge etching machine

144‧‧‧Second wafer protective mask

146‧‧‧Central shelter area

148‧‧‧ crystal edge shelter

150‧‧‧First stop

152‧‧‧ first guard ring

154‧‧‧Second protrusion

160‧‧‧second stop

162‧‧‧second guard ring

202‧‧‧Nozzles

204‧‧‧Non-etching fluid

240‧‧‧Edge etching machine

244‧‧‧Watt protective mask

FIG. 1 is a schematic diagram showing the relationship between the film thickness of a wafer formed by a conventional method.

2 to 8 are schematic views showing a method of planarizing a wafer according to a first preferred embodiment of the present invention.

9 and 10 are schematic views showing a method of planarizing a wafer according to a second preferred embodiment of the present invention.

Figure 11 is a schematic view showing the shielding state of the edge etching process of the third preferred embodiment of the present invention.

FIG. 12 is a schematic view showing a method of planarizing wafer 10 according to a fourth preferred embodiment of the present invention.

10‧‧‧ wafer

10b‧‧‧ lower surface

12‧‧‧Base

16‧‧‧Central area

18‧‧‧ crystal edge area

22‧‧‧Electrical coding

24‧‧‧ Positioning gap

44‧‧‧First wafer protective mask

46‧‧‧Central shelter area

48‧‧‧ crystal edge shelter

Claims (19)

An edge etching machine includes: a wafer-protecting mask covering a portion of a surface of a wafer, wherein the wafer defines a central region and a crystal edge region surrounding the central region The wafer protection mask includes: a central shielding area covering the central area of the wafer; and at least one crystal edge shielding area extending outward from the outer edge of the central shielding area to cover the A portion of the wafer region of the wafer and exposing the remainder of the intergranular region. The edge etching machine according to claim 1, wherein the crystal edge region has a width of between 1 mm and 3 mm. The edge etching machine of claim 1, wherein the edge shielding region of the wafer shielding mask extends outward from the outer edge of the central shielding region to a circumference of the wafer. The edge etching machine according to claim 1, wherein the wafer has at least one wafer mark disposed on a lower surface of the wafer and located in the crystal edge region. The edge etching machine of claim 4, wherein the edge shielding area of the wafer shielding mask covers the wafer mark of the wafer. The edge etching machine of claim 5, wherein the wafer mark comprises a laser code. The edge etching machine according to claim 1, wherein the wafer comprises at least one semiconductor component and at least one wafer mark, the semiconductor component being located in the central region and adjacent to the upper surface of the wafer, And the wafer mark is disposed on the upper surface of the wafer and is located in the crystal edge region. The edge etching machine of claim 7, wherein the edge shielding area of the wafer shielding mask covers the wafer mark of the wafer. The edge etching apparatus according to claim 1, wherein the wafer protection mask comprises a stopper, a guard ring and at least one protrusion, and the guard ring surrounds the stopper, and the guard ring surrounds the stopper The protruding portion extends outwardly from the outer edge of the grommet. The edge etching machine according to claim 9, wherein the central shielding area of the wafer shielding mask is formed by the stopper and the guard ring, and the crystal of the wafer shielding mask The edge shielding area is composed of the protruding portion. The edge etching machine according to claim 10, wherein the stopper comprises a pedestal for loading the wafer. An edge etching machine includes: a pedestal having a bearing surface for mounting a pedestal a wafer having a central region and a crystal edge region surrounding the central region; at least one nozzle disposed toward the portion of the wafer region for providing at least one non-etching fluid, And contacting the non-etching fluid with a portion of the edge region of the wafer; and an etching gas supply line for providing an etching gas to etch a portion of the edge region of the wafer. The edge etching machine according to claim 12, wherein the crystal edge region has a width of between 1 mm and 3 mm. The edge etching machine of claim 12, wherein the wafer has at least one wafer mark disposed on a lower surface of the wafer and located in the crystal edge region. The edge etching machine of claim 12, wherein the nozzle is disposed toward the wafer mark of the wafer. A method of planarizing a wafer, comprising: providing at least one wafer comprising a substrate and at least one dielectric layer on the substrate, and defining a central region on the wafer and surrounding the central region a crystal edge region; performing an edge etching process using a wafer mask The cover covers the central region of the wafer and a portion of the intergranular region, and the dielectric layer located in the remaining portion of the intergranular region is etched by a gas; and a chemical mechanical polishing process is performed on the wafer. The method of claim 16, wherein the width of the intergranular region is between 1 mm and 3 mm. The method of claim 16, wherein the wafer has at least one wafer mark disposed on a lower surface of the wafer and located in the crystal edge region. The method of claim 16, wherein the edge etching process does not etch the wafer mark of the wafer.