201001512 布’而且習知CMP機台本身也有其作用的限制，因此這時的cMp _實際上無法有效控偏_緣的频（__。§响），使 得晶圓邊緣仍舊會呈現出陡崎的侧視輪摩（profiie)。 。月參知第1圖’其緣示的是習知方法所形成之—晶圓的膜層 厚度關係以、ϋ。其中’示意@之橫座標表示的是晶圓各部分至 晶圓圓心的距離，示意圖之綜座標係表示晶圓的膜層厚度，而第】 圖所不之晶圓係經過—内層介電（inter妨erdie㈣ic，iLD)層 儿牙貝A私 CMP製程與一晶邊清洗（wafer bevei rinse，WBR ) 後之膜厚狀况。如第i圖所不，晶邊的膜厚與中央區域的膜厚可 能會相差_埃（angst_)。較厚的晶邊不但會影響製程 的作用，而且晶圓邊緣附近容易產生許多邊緣缺陷（defect)。這 二邊、·彖缺可此會!^響後續製程的進行，使得後續所製作的裝置 或結構也具有缺陷。糊來說’對於接觸減的形成製程而言， 當進行接觸窗的餘刻製程時，由於晶邊處的膜厚較深，因此會導 致晶邊處的接觸窗敍刻不足，使得接觸插塞不會與下方元件電連 接，而形成斷路（Gpen)缺陷。另—方面，晶圓邊緣附近的邊緣 缺陷也可能會直接影響後續的钱刻製程或其他沉積製程，例如當 晶邊處的膜厚越深時，蝕刻製程通常會產生越多不理想的結核 (nodule )現象。 有鑑於此，習知膜層製作方法會導致產品晶圓不易通過晶圓 "T接受度測3式（wafer acceptance test，WAT )而降低產率（一丨廿）， 201001512 仍待進i改善。如何製作出财良好厚度與表面雜的膜 是該領域所致力解決之一大課題。 【發明内容】 以 β因此本發明之主要目的之一在於提供—種晶邊酬機台， 提升產品良率並避免蝕刻時產生標記辨識不清的問題。 根據本發明之一實施例’本發明提供—種晶邊侧機台，其 包奸-晶®崎遮罩（wa㈣她etlng mask)，且晶圓防護遮罩 覆盍一晶圓之部分表面。晶圓上定義有—中央區域與-環繞該中 倾=晶邊區域。前述晶_護遮罩包含有—中央遮蔽區^及 至少-晶邊遮蔽區。中央遮蔽區係全面覆蓋晶圓之中央區域，而 晴中央遮蔽區之外緣向外延伸而出，覆蓋晶圓之部 曰曰邊區域，並且暴露出晶邊區域之其餘部分。 圓之=本=之另—較佳實補，本發㈣提供—種平坦化晶 位於該基;J之介ίΓ少—晶圓。晶圓包含有—基底與至少一 中央區域之晶sr之；：晶圓上定義有—央區域與一環繞該 不钱刻晶圓之中央區域心晶邊綱製程，晶箱刻製程 之其餘部分的接低日日賴域，犠彳位_晶邊區域 玲接者，再對晶圓進行一化學機械研磨製程。 為了更近一步 解本务明之特徵及技術内容，請參閱以下有 201001512 關本發明之詳細說明與附圖。然而所附圖式僅供參考與輔助說明 用，並非用來對本發明加以限制者。 【實施方式】 請參閱第2圖至第8圖，第2圖至第8圖係為本發明第一較佳實 轭例平坦化晶圓10之方法示意圖，其中相同的元件或部位沿用相 同的符號來表示。需注意的是圖式僅以說明為目的，並未依照原 尺寸作圖。首先參考第2圖，其緣示的是晶圓1〇之底視示意圖。如 第2圖所示，提供至少一晶圓10。晶圓10上定義有一中央區域16, 、及％、、堯中央區域16、位於晶圓1〇之邊緣且寬約數毫米之晶邊 區域（bevel regi〇n) 18。以一 12忖晶圓為例，晶邊區域18之寬度 、、’勺”於1¾米至3毫米（mm)之間，例如為2毫米。晶圓1〇包含有 一基底12,基底12内可包含有至少一半導體元件（未顯示），例如 積體電路之部份元件，且基底12之晶邊區域18中可設置有複數個 ，曰曰圓標記20，例如晶圓標記20可包含有一雷射編碼（lasercode) 22、一定位缺口24、一定位記號（未顯示）、一對準標記（未顯示） 或是任何待保護之元件。雷射編碼22可供一辨識裝置來辨識晶圓 10，可包含晶圓的批次編號以及晶圓身份辨識號碼等訊息，其通 丰疋以雷射方式燒結在晶圓1〇的表面，而定位缺口％可用於各式 半導體製程中固定晶圓10之座標。 第3圖繪示的是晶圓10之剖視示意圖。如第3圖所示，接著可 利用沉積製程、賴製程或旋塗製程等方式於基底12上形成至少 8 201001512 -介電層14。根據晶_之整體_，晶_具有—上表面⑽ ㈣face)他與-下表面（b〇tt⑽―）服。晶圓ι〇之半導體元 件通常係設置於晶圓10之上表面1〇a鄰近處’以定義出複數個晶 粒丄而晶_記20可設置於晶圓1〇之下表面，未被介電層_ 覆蓋。於此實施例中’介電層14係為—待研磨之材料層，而位於 晶邊區域18中的介電層14可能比位於中央區域16中的介電層财 厚。此外，介電層Μ可為-ILD層，直接覆蓋於晶圓ι〇之半導體元 件上’穌發明之晶邊侧方法並未侷限於麟侧仙層，而可 應用於任何需進行晶邊細之材料層，例如介電層Μ亦可為一金 屬層間介電（intermetal dielectric，IMD)層。 凊-併參考第4圖、第5圖與第6圖，第4圖繪示的是進行 -晶邊侧製程之剖視示意圖，第5圖繪示的是第4圖所示之晶 虫刻衣私的底視示意圖，而第6圖繪示的是第$圖所示之晶邊 侧製程的遮蔽狀況示意圖。如第4圖所示，其後可以把晶圓1〇 載入本發明所提供之一晶邊關機台4〇，以進行—晶邊_製 程。晶絲刻機台40包含有一第一晶圓防護遮罩（wafer_pr〇tectmg mask) 44 ’用以覆蓋晶圓1〇之部分下表面。第一晶圓防護遮 罩44可包含有一第一擋塊50、一第一護環52與至少一第一突出 部54，設置於一蝕刻反應室42内。於本實施例中，第一擋塊知 可以為一承載基座（pedestai)，用以載置晶圓1〇，例如第一擋塊 50可為一靜電吸盤（dectr〇staticchuck，匕沾滅），藉以吸附並固 定曰曰圓10。第一護環52可環繞於第一擋塊5〇周圍，且第一護環 201001512 ==：^!^料綱—嫩蝴表面地的 JC千同又使侍弟—護環52可以適當地覆蓋 面10b。第一突出部5 之邛刀下表 門川…- 弟一_52之外緣向外延伸而出至晶 g人摇兔-π. ^大出# 54可為—體成形之設計， ° ’、下基環(bottom pedestal ring)。 請對照第4圖、塗s闰& &(π ^ 奶… 圖與弟6圖，第4圖之第-擋塊50與第 可形成第5圖與第6圖之第-晶圓防護遮罩44的中央 遮欧區46,而第4圖之第„突出部_ 、 第-晶圓防護遮罩44的晶邊奸£48々圖⑼6圖之 J日日瓊‘虹區48。如弟5圖鱼繁6岡 第1曰__44包含有,賴區46以及至少二二’ 蔽區48。中央遮蔽區46可全面覆蓋晶圓ω之中央區域： =蔽區48可從中央遮蔽區46之外緣 、 圆周，覆蓋部分之晶邊區域18 出至曰曰囫10之 邊區域。因此，曰各出位於待1虫刻之其餘晶 !㈣份曰：: 不會_到晶圓1〇之中央區域 0 ”晶0日邊£域18，而侧位於 電層(未顯示）。舉·n ^之其餘部分的介 伽圓1〇晶邊區域18之雷射編碼22。斗中=8 的大小、形狀與位置可恰好對應至中央區域Μ而設置、^地 46 16 5 0‘25毫米’但不限於此。 哥、 另外，請再參閱第4 圖’晶邊餘刻機台4〇更可包含有一第二 10 201001512 才田塊60曰—第二護環62、-第一電極64、-第二電極66與_蝕 J氣肢^^、笞線68，設置於触刻反應室42内。第二擋塊6〇可& ，於第—擋塊50上方，且與第-擋塊50相距-預定間距，用以 復盍晶圓10之部分上表面1〇a。第二護環62可環繞於第二擋塊 6〇周圍’且第二護環62之底面水平高度可以等於第二擋塊6〇之 底面水平高度，使得第二護環62可以適當地覆蓋晶圓1〇之上表 面l〇a。第二擋塊6〇與第二護環62可全面覆蓋位於中央區域 ’’、、貝不)之曰曰圓1〇上表面1〇a。其中，前述第—擋塊5〇、第—護環 52 '第一突出部54、第二擋塊60或第二護環62皆可包含有一ζ 究材料’而其部分表面係可再覆蓋有—金屬膜，例如氧化紀 (^2〇3)，用以增加抗蝕刻效果。第一護環52與第二護環62係以 可拆卸之方式設置於第—魏％與第二馳⑹之關 奴提供官'線68可提供侧氣體70來触刻介電層Η，而第 ，、弟一電極66可以提供電壓差以進行前述晶邊蝕刻製程。201001512 cloth 'and the conventional CMP machine itself also has its role limit, so at this time cMp _ can not effectively control the frequency of the edge (__. § ring), so that the edge of the wafer will still show the side of the steep Look at the wheel (profiie). . The monthly reference to Fig. 1 shows the relationship between the thickness of the film layer formed by the conventional method and the thickness of the wafer. The 'signal @ y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y Inter erdie (four) ic, iLD) layer of gingival A private CMP process and a wafer edge cleaning (wafer bevei rinse, WBR) after the film thickness. As shown in Figure i, the film thickness of the crystal edge and the film thickness of the central region may differ by angstroms (angst_). Thicker crystal edges not only affect the process, but also many edge defects near the edge of the wafer. The two sides, the lack of this can be met! ^ The subsequent process is carried out, so that the subsequent device or structure is also defective. For the contact reduction process, when the contact window is formed, the film thickness of the crystal edge is deep, so the contact window at the crystal edge is insufficiently etched, so that the contact plug is made. It does not electrically connect to the underlying components and forms a GSP defect. On the other hand, edge defects near the edge of the wafer may directly affect the subsequent engraving process or other deposition processes. For example, when the film thickness at the edge of the crystal is deeper, the etching process usually produces more undesired tuberculosis ( Nodule) phenomenon. In view of this, the conventional film layer manufacturing method may cause the product wafer to be difficult to pass the wafer "Twafer acceptance test (WAT) to reduce the yield (a glimpse), 201001512 still to be improved . How to make a film with good thickness and surface miscellaneous is one of the major issues in this field. SUMMARY OF THE INVENTION Therefore, one of the main purposes of the present invention is to provide a kind of crystal edge compensation machine, which improves product yield and avoids the problem of unclear mark recognition during etching. According to an embodiment of the present invention, the present invention provides a seed side side machine having a wafer mask (wa) and a wafer guard mask covering a portion of a surface of a wafer. The wafer is defined with a central region and a surrounding center = crystal edge region. The crystal shield includes a central shielding region and at least a crystal edge shielding region. The central masking area covers the entire central area of the wafer, while the outer edge of the clear central masking area extends outwardly, covering the marginal area of the wafer and exposing the rest of the intergranular area. The circle = the other = better complement, the hair (4) provides - a flattened crystal is located in the base; J is less than - wafer. The wafer includes a substrate and at least one central region of the crystal sr; the wafer defines a central region and a central region surrounding the wafer, the remainder of the crystal engraving process After the low-day Lai domain, the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In order to further understand the features and technical contents of the present invention, please refer to the following 201001512 for a detailed description and drawings of the present invention. However, the drawings are for illustrative purposes only and are not intended to limit the invention. [Embodiment] Please refer to FIG. 2 to FIG. 8 . FIG. 2 to FIG. 8 are schematic diagrams showing a method for planarizing a wafer 10 according to a first preferred embodiment of the present invention, wherein the same components or parts follow the same Symbol to indicate. It should be noted that the drawings are for illustrative purposes only and are not drawn to the original dimensions. Referring first to Figure 2, the bottom view is a bottom view of the wafer. As shown in Fig. 2, at least one wafer 10 is provided. The wafer 10 defines a central region 16, and a central portion 16, a central region 16, and a bevel reed 18 located at the edge of the wafer 1 and having a width of about several millimeters. Taking a 12-inch wafer as an example, the width of the crystal-edge region 18, the 'spoon' is between 13⁄4 meters and 3 millimeters (mm), for example, 2 mm. The wafer 1 〇 includes a substrate 12, and the substrate 12 can be At least one semiconductor component (not shown) is included, such as some components of the integrated circuit, and a plurality of embossed marks 20 may be disposed in the crystal edge region 18 of the substrate 12. For example, the wafer mark 20 may include a ray. A laser code 22, a positioning notch 24, a positioning mark (not shown), an alignment mark (not shown) or any component to be protected. The laser code 22 can be used by an identification device to identify the wafer 10. The information may include the batch number of the wafer and the wafer identification number. The Tongfeng 烧结 is laser-sintered on the surface of the wafer, and the positioning gap % can be used for fixing the wafer 10 in various semiconductor processes. Figure 3 is a cross-sectional view of the wafer 10. As shown in Figure 3, at least 8 201001512 - dielectric can be formed on the substrate 12 by a deposition process, a Lay process, or a spin coating process. Layer 14. According to the overall _ of the crystal _, the crystal _ has - Surface (10) (4) face) He and the lower surface (b〇tt(10)-). The semiconductor component of the wafer is usually disposed adjacent to the surface 1〇a of the wafer 10 to define a plurality of crystal grains. The _ 20 can be disposed on the lower surface of the wafer 1 , and is not covered by the dielectric layer _. In this embodiment, the dielectric layer 14 is the material layer to be polished, and the dielectric layer 14 is located in the crystal edge region 18 . The electrical layer 14 may be thicker than the dielectric layer located in the central region 16. In addition, the dielectric layer may be an -ILD layer that directly covers the semiconductor component of the wafer. It is limited to the Linxianxian layer, and can be applied to any material layer that needs to be finely grained. For example, the dielectric layer can also be an intermetal dielectric (IMD) layer. 凊 - and refer to Fig. 4, 5 and 6 , FIG. 4 is a cross-sectional view showing a process of performing a crystal side process, and FIG. 5 is a bottom view showing a crystal insect inscription shown in FIG. 4 . Figure 6 is a schematic view showing the shielding state of the crystal side process shown in Fig. $. As shown in Fig. 4, the wafer can be wafer 1 thereafter. Loading a crystal edge shutdown station 4〇 provided by the present invention to perform a crystal edge process. The crystal engraving machine stage 40 includes a first wafer protection mask (wafer_pr〇tectmg mask) 44' for covering the crystal A portion of the lower surface of the first wafer protection mask 44 may include a first stopper 50, a first guard ring 52 and at least one first protrusion 54 disposed in an etching reaction chamber 42. In this embodiment, the first block may be a pedestal for mounting the wafer 1 , for example, the first block 50 may be an electrostatic chuck ( 匕 〇 ch 〇 , , , , , , , , Thereby adsorbing and fixing the round 10 . The first retaining ring 52 can surround the first retaining block 5〇, and the first retaining ring 201001512 ==:^!^Material--the JC thousand of the surface of the tender butterfly can make the waiter-guard ring 52 properly Covering surface 10b. The first protruding part 5 is the same as the top of the file...- 弟一_52 The outer edge extends outward to the crystal g human shake rabbit-π. ^大出# 54 can be the body-shaped design, ° ', Bottom pedestal ring. Please refer to Figure 4, s 闰 amp && (π ^ milk ... Figure and Figure 6 Figure 4, the first block - block 50 and the first to form the fifth and sixth map - wafer protection The central occlusion area 46 of the mask 44, and the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The fifth __44 contains a lag zone 46 and at least a two quarantine zone 48. The central occlusion zone 46 can cover the central area of the wafer ω: = the occlusion zone 48 can be removed from the central occlusion zone 46 outer edge, circumference, covering part of the crystal edge area 18 out to the side of the 曰曰囫10. Therefore, each of the remaining crystals located in the worm's engraving! (four) 曰:: will not _ to wafer 1 The central region of the crucible is 0" crystal 0 on the side of the field 18, and the side is on the electric layer (not shown). The rest of the n ^ the remainder of the gamma circle 1 crystal edge region 18 of the laser code 22. The size, shape and position of the 8 can be set to correspond to the central area, and the ground is 46 16 5 0'25 mm 'but not limited to this. Brother, in addition, please refer to Figure 4 'The crystal edge engraving machine 4 The change can also include a second 10 2010015 12, the field block 60曰—the second guard ring 62, the first electrode 64, the second electrode 66 and the 蚀J J limb, the 笞 line 68 are disposed in the etch reaction chamber 42. The second block 6 〇可及amp; above the first block 50, and spaced apart from the first block 50 by a predetermined distance for tamping a portion of the upper surface 1a of the wafer 10. The second guard ring 62 may surround the second The height of the bottom surface of the second retaining ring 62 may be equal to the horizontal level of the bottom surface of the second retaining ring 62, so that the second retaining ring 62 can properly cover the upper surface l〇a of the wafer 1〇. The second stopper 6 〇 and the second guard ring 62 can completely cover the upper surface 1 〇 a of the circle 1 、 in the central region '', 别别). Wherein, the first block 5 〇, the first retaining ring 52 ′, the first protrusion 54 , the second block 60 or the second guard ring 62 may include a sturdy material and some of the surface may be covered again. - Metal film, such as oxidized (^2〇3), to increase the etching resistance. The first retaining ring 52 and the second retaining ring 62 are detachably disposed on the first and second passers (6) to provide a side gas 70 to the dielectric layer. First, the first electrode 66 can provide a voltage difference to perform the aforementioned edge etching process.
第7圖緣示的是晶邊蝕刻製程之後的晶圓1〇剖視示意圖。如 η圖所不’本發明不但可以減少位於晶邊區域18之介電層Μ 減少晶邊區域18之邊緣缺陷，同時也可以保護晶圓_定 Γ: °舉例來說’第—晶圓防護遮罩44之晶邊遮蔽區48可覆蓋 二圓^之雷射編碼22 ’因此可以避免雷射編碼22受到酬而無 φΐΐ ^ f注意的是’經過晶邊侧製程之後，位於晶邊區域18 、）ι电層14可以與位於中央區域16中的介電層μ厚度相近， °以比位於中央區域16中的介電層14更薄，也可以比位於中央 11 201001512 二t的；1电層14更厚’而不需受到圖示所侷限。此外，第 ★罩44之晶邊遮蔽區48實際上不限於僅遮蔽晶圓標 5 ’而可用於遮蔽晶圓H)之任何不需接受製程反應的部位。 K f著如第8圖所示，進行—化學機械研磨（ehem-讎hanicai Γ: rg ’CMP)製程，在於晶圓10之上表面衞上加入一研磨 水^ry ’未顯示）後’依據產品要求之規格研磨上表面伽上 之層14至―歉厚度。隨後可利用去離子水（—d _ ’ WW齡）作為—清洗液（未顯示），於晶圓Η)之上表面 ^上進彳了—表面清洗（surfaeedeaning)製程，崎底去除位於 曰曰圓H)上表面H)a上之介電層14的殘渣（歸e)以及殘餘之研 由於本發明之晶雜郷程可以有效輯晶輕域㈣介電 層Η厚度’因此可以防止晶邊區域18的介電層14阻礙cMp製 私的研磨水料分布，亚且避免晶邊區域Μ的介電層Μ影響研磨 墊接觸時的應力分布，以提升CMp製程的平坦纽果。此3外，因 為本發明可削減晶邊區域18的介電層14厚度，所以其後所進行 之CMP製程的可贿収乡研磨_且/紐供更大的研磨下壓 力，進而縮短CMP製程的製程時間。如此—來，本發明不何以 提升CMP製程的平坦化效果、有效控制晶圓邊緣的形貌（响 ㈣响）’且可減少晶邊區域18之邊緣缺陷，藉以提升產品 良率並避免蝕刻時產生標記辨識不清的問題。 ° 12 201001512 實施例之第—晶圓防護遮罩44簡蓋晶㈣之部分下 «亦可限於此。於其他實施财，本發明之晶圓防護 、為柄明弟二較佳實施例平坦化晶圓10之方法示 〜Θ /、相同的TL件或部位沿用相同的符號來表示。第9圖給 示的是進行-晶邊_製程的剖視示意圖，而第㈣繪示的是曰第 9圖所不之㈤邊飿刻製程的遮蔽狀況示意圖。如第9圖與第⑺圖 所不，於介電層14沉積之後，可以把晶圓ω載人本發明所提供 之日叫I虫刻機台H0 ’以進行一晶邊银刻製程。於前述實施例之 主要不同之處在於，此處晶圓1〇之—晶圓標記2()可設置於晶圓 10上表面10a之晶邊區域18中，而晶邊蝕刻機台〗4〇包含有—第 二晶圓防護遮罩144，用以覆蓋晶® 10之部分上表面10a。 如第9圖所不，第二晶圓防護遮罩144可包含有一第二擒塊 、一第二護環162與至少一第二突出部154，設置於一飾刻反 應至42内。於本實施例中，第二擋塊]6〇係設置於晶圓】〇上方， 用以覆蓋晶圓ίο之部分上表面i〇a。第二護環162可環繞於第二 松塊160周圍，且第二護環162之底面水平高度可以等於第二幹 塊160之底面水平高度i得第二護環162可以適當地覆蓋晶圓 10之上表面10a。第二擋塊160與第二護環162可全面覆蓋位於 中央區域〗6之晶圓1〇上表面i〇a。第二突出部154可從第二護環 162之外緣向外延伸而出至晶圓1〇之圓周。第二護環162與第二、 13 201001512 突出部154可為一體成形之設計，且可合稱為一上基環(t〇p pedestal ring) ° 另外’晶邊#刻機台140更可包含有一第一擋塊ι5〇、一第一 護環152、一第一電極64、一第二電極66與一蝕刻氣體提供管線 68’設置於|虫刻反應室42内。第一擋塊150可設置於第二擔塊16〇 下方’且與第二擋塊160相距一預定間距。其中，第一擔塊I%、 第一 δ蔓環152、第二擔塊160、第二護環162或第二突出部154皆 可包含有一陶瓷材料，而其部分表面係可再覆蓋有一金屬膜。第 一擋塊150與第一護環152可覆蓋晶圓之部分下表面丨〇b。 如第10圖所示，中央遮蔽區146可全面覆蓋位於晶圓1〇上 表面10a之中央區域16，而晶邊遮蔽區148可從中央遮蔽區146 之外緣向外延伸而出至晶圓10之圓周，覆蓋部分位於晶圓1〇上 表面l〇a之晶邊區域18，並且暴露出位於上表面丨加之其餘晶邊 區域18。舉例來說’第二晶圓防護遮罩144之晶邊遮蔽區148可 覆蓋晶圓10上表面10a之至少—晶圓標記2〇。以一個已定位之晶 圓10而言’而此時的晶圓標記20約可與於晶圓1〇之定位缺口 24 夹一 90度角…180度角且/或—27〇度角，而第二突出部154 可對應於所欲保護之晶圓標記2〇的位置而設置，甚至可能直接覆 蓋晶圓1G之雜缺口 24。請對照帛9圖與第1()目，第9圖之第 二擒塊160與第二護環162可形成第1〇目之第二晶圓防護遮罩 144之中央遮蔽區146’而第9圖之第二突出部154即可形成第ι〇 201001512 圖之第 晶圓防護遮罩144之晶邊遮蔽區148。 而特別左意的是’本發明之晶圓防言^ 晶圓之中央區域與部分晶邊區域，且暴露=== Γ144'、、Γ不需制前述第—晶圓防護遮罩44與第二晶圓防護遮 1 =限。於其他實施例中，護環與突出部的形狀、位置、 =調=且===度、設置角度或數量皆可根據製程需 =二Γ ’同—晶邊爛製程中亦可同時利用複數個突出 =分上表面與部分下表面。或者，晶圓防護遮罩 蔽巴之外^包含—81形巾央遮蔽區與—向外延伸的晶邊遮 形且具有晶邊暴露缺口 — 皁。月多閱弟Η圖，弟11圖係為本發明第二 貫施例晶_馳的賴狀況示賴。如㈣騎示，—乂一命 =之晶圓防護遮罩244本質上對應整個晶 = :〇似面1〇a或下表面10b。其中 J: 3少:=暴露缺口 274，例如可位於晶圓IQ之定位缺口以 置等二二'__且/或，度角位Figure 7 is a schematic cross-sectional view of the wafer after the edge etching process. As the η diagram does not, the invention can not only reduce the dielectric layer located in the crystal edge region 18, but also reduce the edge defects of the crystal edge region 18, and also protect the wafer _ Γ: °, for example, 'the first wafer protection The crystal edge shielding area 48 of the mask 44 can cover the laser coding 22' of the two circles. Therefore, the laser encoding 22 can be prevented from being compensated without φ ΐΐ ^ f. Note that after the edge side process, the crystal edge region 18 is located. The dielectric layer 14 may be similar to the thickness of the dielectric layer μ located in the central region 16, which is thinner than the dielectric layer 14 located in the central region 16, or may be located at the center 11 201001512 two times; Layer 14 is thicker' without being limited by the illustration. In addition, the crystal edge masking region 48 of the second cover 44 is not limited to being shielded only by the wafer mark 5' and can be used to shield the wafer H) from any portion that does not require a process reaction. K f is as shown in Fig. 8, and the process of chemical mechanical polishing (ehem-雠hanicai Γ: rg 'CMP) is performed on the surface of the wafer 10 after adding a grinding water ^ry 'not shown'. The specification of the product is required to grind the layer 14 on the upper surface to the thickness of the apology. Deionized water (-d _ 'WW age) can then be used as the cleaning liquid (not shown) on the surface of the wafer Η) - surface cleaning (surfaeedeaning) process, the bottom removal is located in 曰曰Circle H) The residue of the dielectric layer 14 on the upper surface H)a (returned to e) and the residual research can effectively dissolve the light domain (four) dielectric layer Η thickness by the crystal enthalpy of the present invention, thus preventing the crystal edge The dielectric layer 14 of the region 18 hinders the distribution of the abrasive water material of the cMp, and avoids the dielectric layer of the edge region of the crystal edge to affect the stress distribution when the polishing pad contacts, thereby improving the flatness of the CMp process. In addition, since the thickness of the dielectric layer 14 of the crystal edge region 18 can be reduced by the present invention, the subsequent CMP process can be used to provide a larger grinding pressure, thereby shortening the CMP process. Process time. In this way, the present invention does not improve the planarization effect of the CMP process, effectively controls the topography of the wafer edge (resonance), and can reduce edge defects of the crystal edge region 18, thereby improving product yield and avoiding etching. Produce a problem that the mark is unclear. ° 12 201001512 The first part of the embodiment - wafer protection mask 44 under the cover (4) part of the word «may be limited to this. For other implementations, the wafer protection of the present invention, the method of planarizing the wafer 10 by the preferred embodiment of the present invention, is shown in the following paragraphs, and the same TL elements or portions are denoted by the same reference numerals. Fig. 9 is a cross-sectional view showing the process of performing the crystal edge _ process, and the fourth figure is a schematic view showing the occlusion condition of the (5) side etch process of Fig. 9 . As shown in Fig. 9 and Fig. 7 (7), after the dielectric layer 14 is deposited, the wafer ω can be loaded with the day of the present invention to call the machine H0' for a crystal edge silver etching process. The main difference in the foregoing embodiment is that the wafer 1 - wafer mark 2 () can be disposed in the crystal edge region 18 of the upper surface 10a of the wafer 10, and the edge etching machine is 4" A second wafer shield 144 is included to cover a portion of the upper surface 10a of the wafer 10. As shown in FIG. 9, the second wafer shield 144 may include a second block, a second guard ring 162 and at least one second protrusion 154 disposed in a decorative response 42. In this embodiment, the second stopper is disposed above the wafer to cover a portion of the upper surface i〇a of the wafer ίο. The second retaining ring 162 can surround the second loose block 160, and the bottom surface of the second retaining ring 162 can be equal to the bottom surface level i of the second dry block 160. The second retaining ring 162 can properly cover the wafer 10. Upper surface 10a. The second stopper 160 and the second retaining ring 162 can completely cover the upper surface i〇a of the wafer 1 in the central region. The second protrusion 154 may extend outward from the outer edge of the second guard ring 162 to the circumference of the wafer 1〇. The second retaining ring 162 and the second, 13 201001512 protruding portion 154 may be integrally formed, and may be collectively referred to as an upper base ring (t〇p pedestal ring). A first block ι5 〇, a first guard ring 152, a first electrode 64, a second electrode 66 and an etching gas supply line 68' are disposed in the insect chamber 42. The first stopper 150 may be disposed under the second weight 16 〇 and spaced apart from the second stopper 160 by a predetermined distance. The first load block I%, the first δ vine ring 152, the second load block 160, the second guard ring 162 or the second protrusion 154 may all comprise a ceramic material, and part of the surface may be covered with a metal. membrane. The first stop 150 and the first guard ring 152 may cover a portion of the lower surface 丨〇b of the wafer. As shown in FIG. 10, the central shielding region 146 can completely cover the central region 16 of the upper surface 10a of the wafer 1 , and the crystal shielding region 148 can extend outward from the outer edge of the central shielding region 146 to the wafer. The circumference of 10 covers a portion of the crystal edge region 18 on the upper surface 10a of the wafer 1 and exposes the remaining crystal edge regions 18 on the upper surface. For example, the crystal edge masking region 148 of the second wafer guard mask 144 may cover at least the wafer mark 2' of the upper surface 10a of the wafer 10. In the case of a positioned wafer 10, the wafer mark 20 at this time can be approximately 90 degrees from the positioning notch 24 of the wafer 1 ... 180 degrees and / or - 27 degrees, and The second protrusion 154 may be disposed corresponding to the position of the wafer mark 2〇 to be protected, and may even directly cover the impurity gap 24 of the wafer 1G. Please refer to FIG. 9 and FIG. 1(). The second block 160 and the second guard ring 162 of FIG. 9 can form the central shielding area 146 ′ of the second wafer protective mask 144 of the first item. The second protrusion 154 of FIG. 9 can form the edge masking area 148 of the wafer protective mask 144 of the first embodiment of FIG. The special left is that the wafer of the present invention has a central region and a portion of the crystal edge region, and the exposure === Γ 144 ′, and the first wafer protective mask 44 and the Two wafer protection cover 1 = limit. In other embodiments, the shape, position, ====== degree, setting angle or quantity of the guard ring and the protrusion may be according to the process requirement=two Γ 'the same-crystal edge rot process can also use the plural at the same time Highlights = upper surface and partial lower surface. Alternatively, the wafer protective mask is covered with a mask, and the -81-shaped towel shielding area and the outwardly extending crystal edge are occluded and have a grain edge exposed notch - soap. In the month of reading more than the younger brother, the 11th figure is the second example of the invention. For example, (4) riding, 乂一命 = wafer protection mask 244 essentially corresponds to the entire crystal = : 〇 like face 1 〇 a or lower surface 10b. Where J: 3 less: = exposure gap 274, for example, can be located in the wafer IQ positioning gap to set a second two '__ and / or degree angle
注病是，晶邊暴露缺口別並不—定要如第U 只要相對於晶圓邊緣内縮，内縮的程度可視 而要1’例如可以將部分圓弧以較大曲率半徑的圓弧取代。 體來保護 此外’本發明村彻不會侵m⑽非钱刻流 15 201001512 晶圓ίο之特定區域不受蝕刻。請參閱第12圖，其繪示的是本發明 第四較佳實施例平坦化晶圓10之方法示意圖，其中相同的元件或 部位沿用相同的符號來表示。如第12圖所示，於前述實施例主要 之不同之處在於’此處之晶邊蝕刻機台240可包含有至少一喷嘴 2〇2，朝向晶圓10之部份晶邊區域18而設置，用於提供至少一非蝕 刻流體2〇4 ’並使該非钮刻流體2〇4接觸晶圓1〇之晶邊區域18。晶 邊侧機台240可另包含有-第-擔塊50、-第-護環52、-第二 私塊60、-第二護環62、—第一電極64、一第二電極的與一侧 氣體提供管線68 ’設置於敍刻反應室42内。於本實施例中，喷嘴 202可朝向位於晶圓丨〇下表面丨％之晶雜域1納的雷射編碼^而 设^。如此-來，本發明可調整喷嘴2〇2與非敍刻流體撕的流速， 使得非綱流體204可以覆蓋雷射編碼22表面而使得侧氣體％ 不會接_雷㈣碼22。因此，本發明不但可以減少位於晶邊區 域18之介電糾厚度’減少晶雜賴之邊緣缺陷，同時也可以 (保護晶_特定區域。需注意的是，第三實施例之倾搬亦可姓 ^晶邊蝴幾台如或晶邊蝴_时’作為晶_製程的 τ w々开为卜列幾項優點。 但可以減少晶邊_8之邊_ 柄月不 料層厚度阻礙彳_um操作絲。糾日邊區域的材 的同時保護晶圓的特定區域， X月也可Μ於蝕刻 π 2 ’（免每射編碼等晶圓標記受到敍刻 16 201001512 j辨4。有鑑於此，本發明可有效控制晶圓邊緣的形貌 品良率並避免侃㈣產生標記辨識*清的問題。 耗 【圖式簡單說明】 第1圖 '纟會示的是習知古土 α 第2圖至第㈣料杯成之—晶__厚度_示意圖。 意圖。 ^明弟一較佳實施例平坦化晶圓之方法示 第9圖與第10圖传 意圖。為本發明弟二較佳實施例平坦化晶圓之方法示 $ 11圖係為本發日月笛二+ 圖。 父土貫施例晶邊餘刻製程的遮蔽狀況示意 第12圖繪示的是太旅nn# 意圖。 x細較佳實施例平坦化晶圓10之方法示 【主要元件符號說明】 10 曰_ J 晶圓 l〇b π 主 下表面 10a -面 14 人+ 介電層 12 基底 18 曰、真r 曰曰邊區域 16 中央區域 22 〜 雷射編碼 20 晶圓標記 24 定位缺口 201001512 40 晶邊钱刻機台 44 第一晶圓防護遮罩 48 晶邊遮蔽區 50a 承載表面 54 第一突出部 62 第二護環 66 第二電極 70 蝕刻氣體 144 第二晶圓防護遮罩 148 晶邊遮蔽區 152 第一護環 160 第二擋塊 202 喷嘴 240 晶邊蝕刻機台 42 触刻反應室 46 中央遮叙區 50 第一擋塊 52 第一護環 60 第二擋塊 64 第一電極 68 蝕刻氣體提供管線 140 晶邊1虫刻機台 146 中央遮蔽區 150 第一擋塊 154 第二突出部 162 第二護環 204 非蝕刻流體 244 晶圓防護遮罩 18The disease is that the edge of the crystal edge is not exposed—it must be as long as the U is retracted relative to the edge of the wafer. The degree of retraction can be 1'. For example, a part of the arc can be replaced by a circular arc with a larger radius of curvature. . Body protection In addition, the invention of the invention will not invade m (10) non-money engraving 15 201001512 The specific area of the wafer ίο is not etched. Referring to Fig. 12, there is shown a schematic diagram of a method of planarizing a wafer 10 in accordance with a fourth preferred embodiment of the present invention, wherein like elements or parts are denoted by the same reference numerals. As shown in FIG. 12, the main difference in the foregoing embodiment is that 'the edge etching machine 240 herein may include at least one nozzle 2〇2 disposed toward a portion of the crystal edge region 18 of the wafer 10. And for providing at least one non-etching fluid 2〇4′ and contacting the non-buttoning fluid 2〇4 to the crystal edge region 18 of the wafer 1〇. The crystal side machine 240 may further include a - a first-load block 50, a - a guard ring 52, a second block 60, a second guard ring 62, a first electrode 64, and a second electrode. A side gas supply line 68' is disposed in the sculpting reaction chamber 42. In the present embodiment, the nozzle 202 can be oriented toward a laser code of 1 Å in the crystal domain of the lower surface of the wafer. As such, the present invention can adjust the flow rate of the nozzle 2〇2 and the non-synchronized fluid tear so that the non-standard fluid 204 can cover the surface of the laser code 22 such that the side gas % is not connected to the _Ray (4) code 22. Therefore, the present invention can not only reduce the dielectric thickness of the crystal edge region 18 to reduce the edge defects of the crystal, but also protect the crystal_specific region. It should be noted that the tilting of the third embodiment can also be The surname ^ crystal edge butterfly, such as or crystal edge butterfly _ when 'as the crystal _ process τ w 々 open several advantages. But can reduce the edge of the edge _8 _ handle month thickness is not blocked 彳 _um Manipulating the wire. While protecting the material of the edge area while protecting the specific area of the wafer, X month can also be etched by π 2 ' (free of wafer mark such as per-shot coding is recognized by the quotation 16 201001512 j. In view of this, The invention can effectively control the topography product yield of the wafer edge and avoid the problem that the mark identification is clear. (The simple description of the figure) The first figure '纟 shows the conventional ancient soil α. To the fourth (four) cup into - crystal__thickness_schematic. Intent. ^ Mingdi a preferred embodiment of the method of planarizing the wafer showing the figure 9 and 10 is intended to be the preferred implementation of the second embodiment of the present invention For example, the method of flattening the wafer shows that the $11 image is the same as the whistle and whistle two + figure. The masking condition of the process is shown in Fig. 12, which is the intention of the TB#. The preferred embodiment of the method for flattening the wafer 10 is shown in the following [Mathematical Symbols] 10 曰_ J Wafer l〇b π Mainly Surface 10a - face 14 person + dielectric layer 12 substrate 18 曰, true r 曰曰 edge region 16 central region 22 ~ laser code 20 wafer mark 24 positioning gap 201001512 40 crystal edge money machine table 44 first wafer protection Mask 48 edge shielding area 50a bearing surface 54 first protrusion 62 second guard ring 66 second electrode 70 etching gas 144 second wafer shielding mask 148 crystal edge shielding area 152 first guard ring 160 second block 202 Nozzle 240 Edge etching machine 42 Touching reaction chamber 46 Central blocking area 50 First stop 52 First guard ring 60 Second stop 64 First electrode 68 Etching gas supply line 140 Crystal edge 1 insect machine 146 central shielding area 150 first stop 154 second protruding part 162 second guard ring 204 non-etching fluid 244 wafer protective mask 18