經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（^ ) 發明昔長 本發明係闋於一種具有多層相互遽接结構之半導醱装 ! 置及其‘製造方法。 該多層相互連接技術僳用以整合較高密度之半導體稹 髅電路，對於此多層相互連接技術，接線層須形成在較 平坦的绝续層之上，如要獲得一平坦的绝緣層，可利用 化學機械研磨法（CHP)。 例如，當要形成兩層相互連接結構畤，先在形成第一 電棰接線層之後，形成一層間绝綠膜，然後在該層間绝 狳瞑上形成第二電槿接線層，由於該第二電棰接線層， 所以會在其上形成一步階，而使得該層間绝緣膜的表面 不平，因此，該層間绝線膜的表面可以藉由上述之CMP 法平坦化，然後再將第二電槿接線層形成在已平坦化的 層間絶錁膜之上》 電極接線層你利用撤彩製程，蝕刻及類似之製程步》 形成，對於撤影製程，由晶籲眉邊部分的光粗剝落所産 生的外在因素會導致半導醱元件的製造良率降低，因而 提出此一問題。Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (^) The invention is long This invention relates to a semiconducting device having a multilayer interconnection structure and its manufacturing method. This multilayer interconnection technology is used to integrate higher density semiconductor crossbond circuits. For this multilayer interconnection technology, the wiring layer must be formed on a flatter insulation layer. If a flat insulation layer is to be obtained, Using chemical mechanical polishing (CHP). For example, when two layers of interconnected structures are to be formed, an interlayer insulation film is formed after the first electrical connection layer is formed, and then a second electrical connection layer is formed on the interlayer insulation layer. The electrical wiring layer will form a step on it, so that the surface of the interlayer insulating film is uneven. Therefore, the surface of the interlayer insulating film can be planarized by the CMP method described above, and then the second electrical layer is planarized. The hibiscus wiring layer is formed on the flattened interlayer insulation film. "The electrode wiring layer is formed by using the color removal process, etching and similar process steps." For the removal process, the light is peeled off by the eyebrows. This problem is raised because of the external factors that can cause the manufacturing yield of semiconductor devices to be reduced.
此處將會簡述光阻剝落的間題，在製造半導龌積體電 辂時，圖案之形成像利用塗著在晶國上之光阻的微彩製 程，及利用形成之麵案當作遮罩，蝕刻在其下之金屬材 料，因此形成一電極接線層。 V 在此独刻期間，該晶圖傺利用夾具将晶圏的邊線部分 夾在蝕刻設備之中，尤其是嘗晶國塗著光阻畤，夾具和 -3- 本紙張A度適用中國國家標準（CNS )人4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 經本部中央標準局貝工消費合作社印製 __B7__ 五、發明説明（> ) ' 晶國邊線部分的光阻膜會在晶圏邊緣彼此相互接梅，在 此情形下，當夾具與光阻膜接觸時，在晶鬮邊嫌部分的 I . 光阻膜會剝落而産生一異物》 晶圆搬蓮或暫時性堆放，就如同其存放在晶圔裝承器 之中一樣，在此情形下，晶圏邊線部分的光阻會剝落， 正如其輿晶圔裝承器接觸的部分，因而産生一異物β 在此情形下，在晶圔邊錄部分的光阻膜會産生一導致 降低半導釀元件製造良率之異物，即使在晶矚邊錄部分 的光阻膜没有剝落而仍保留著，直到分離步驥為止，其 對半導體元件良率的改善也沒有多大的貢獻。 如上所述，在晶國邊縐部分的光阻膜在微影製程時， 軍單只會造成良率的降低，因此，在蝕刻之前，可藉由 下面或類似的方法改善》 例如，對於正光粗的橄影製程，在顯影之前，晶圔的 邊錁部分會先曝光，然後在黷彩時，晶磨邊錄部分的光 阻會因顳影而除去，在此情形下，因為自晶國邊錄部分 除去了光阻，所以在光阻之下的層，如金颶膜，也會在 會會不在轚 刻都行了之 蝕，實為樣 . 和刻之是目 β 程蝕除也刻除 製和移，蝕移 影程膜〜孔作分 撖裂阻穿當部 。為影光貫，緣 去因微此一此邊 除 ，成 ，成因的 分中完除形，圓 部程次移中孔晶 緣製每咀層穿自 邊件以光線貫偽 國元所的接一緣 晶體，分棰成绝 自導上部電形間 驟半以緣在中層 步的或邊 了膜或 刻常次圔為緣層 蝕正10晶是绝線 一在禊成僅間接 下 重完僅靥棰 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨0Χ297公釐） A7 B7 五、發明説明（ 假設第一到第三層你依序形成在晶圔之上，也假設第 二層的最外邊緣端像位在第一雇的最外邊線端内部，即 (請先Μ讀背面之注$項再填寫本頁)The problem of photoresistance peeling will be briefly described here. In the manufacture of semiconductor photoresistors, the pattern is formed like a micro-color process using a photoresist coated on a crystal country, and the formed surface is used as a cover. The cover is etched with the metal material underneath, thereby forming an electrode wiring layer. V During this single engraving period, the crystal picture 傺 used a clamp to clamp the edge of the crystal 在 in the etching equipment, especially when Jinguo was coated with photoresist 畤. The fixture and the -3- degree of this paper are in accordance with Chinese national standards. (CNS) Person 4 Specifications (210X297 mm) (Please read the notes on the back before filling out this page) Printed by the Central Standards Bureau of the Bureau of Shellfish Consumer Cooperatives __B7__ V. Description of the Invention (>) Part of the photoresist film will meet each other at the edge of the crystal film. In this case, when the fixture is in contact with the photoresist film, the part of the photoresist film at the edge of the crystal film will peel off and produce a foreign object. Moving the lotus or temporarily stacking it is as if it is stored in the crystal holder. In this case, the photoresistance on the side line of the crystal holder will peel off, just like the part in contact with the crystal holder. A foreign object β In this case, the photoresist film on the side recording portion of the crystal will produce a foreign object that will reduce the manufacturing yield of the semiconductor device. Even if the photoresist film on the side recording portion is not peeled off, it remains. Until the separation step Piece yield improvement is not much contribution. As mentioned above, during the photolithography process of the photoresist film on the edge of the crystal country, the military order will only reduce the yield. Therefore, before etching, it can be improved by the following or similar methods. For example, for Zhengguang In the rough olive film manufacturing process, before the development, the edges of the crystallites are exposed, and then the photoresistance of the edges of the crystallites is removed by the temporal shadows during the coloring process. In this case, since the crystal The photoresist is removed in the side recording, so the layers under the photoresist, such as the gold hurricane film, will also be etched at the meeting or not. It is the same. Etch removal and shift, etch shift film ~ hole for splitting and blocking through the part. In order to affect the light, the cause of the cause is removed one by one, and the cause of the cause is removed. The round part is moved to the center of the hole. Connected with a crystal, it is divided into a self-conducting upper part of the electric shape. The edge is stepped in the middle layer, or the film is cut or engraved, and the edge is etched. At the end, only the paper size applies to the Chinese National Standard (CNS) A4 specification (2 丨 0 × 297 mm) A7 B7 V. Description of the invention (assuming that the first to third layers are formed on the crystal in order, also assume that the The outermost edge of the second layer is located inside the outermost edge of the first hire, that is, (please read the note on the back before filling this page)
I 第一層的最外邊緣端表面係曝露在晶圔邊緣部分之上的 情形。 若晶鬮邊緣部分的第三層光阻膜移除匾域位在第二層 最外邊緣端的外部，則第三層的最外邊緣蜴會變成在第 二層最外邊緣端的外部，因此，在晶鼷邊綠部分的最邊 緣端之上，不希望第一和第三層彼此相互接觸。 在此情形下，若第一和第三層之間的黏著性很差，則 在晶國邊緣部分之第三層的邊緣端會自第一層剝落，而 産生一外在因素，若在第一和第三靥形成一霄極接線層 ，刖在其間會有猶II流流過》 第3圈為沒有此問題之日本專利公報第8-31710號的 傳統半導體元件，第一層間绝緣膜2,電極接線層3和第 二層間絶緣膜4依序形成在矽基板1之上，參考第3圖 ，設計在微影製程時的光粗膜移除區域，使得稍後形成 在晶圈邊部分上之層的最外邊緣端會位在更裡面》 經濟命中央標準局貝工消費合作社印褽 在示於第3圓之傅統半導醱元件中，因為電極接線層 3的末端曝露在晶圖的邊緣部分，所以，如果第二層間 絶錁膜4的表面係利用CM P法研磨，則不希望第二層間 絶緣膜4接地而産生破碎，逭些破的碎片可以會進入研 磨表面而造成傷杳。 $ 邸使當電極接線層3並没有形成在晶圓邊緣部分的最 外邊緣端，而是由第二層間绝緣膜4覆蓋時，在較接近 -5 - 本紙張尺度通用中國國家標準（CNS ) Α4規格（210X297公釐） 經濟部中央標準局貝工消費合作社印製 A7 ___ B7____ 五、發明说明（4 ) 晶圖邊緣處，晶圚邊緣部分的厚度較薄，尤其是三或更 多饜中的較低層部分，其邊緣的厚度較薄。 基於1此原因，若在電掻接線層3上之第二牖間绝緣膜 4偽用CMP法研磨，則在晶圖邊緣部分已變薄的第二層 間絶緣膜4會更接地進而消失，然後會露出電搔接線靨 3的末端，在此情形下，當持鑛使用CMP法時，霉出的 電保接線層3就會接地，接著其破的碎Η會進入層間绝 緣膜的研磨表面，使其受到傷害》 m m m m 本發明之目的僳要提供一種具有多層相互連接结構之 半導體裝置及其製造方法，其中層間絶緣膜的表面不會 因化學機械研磨而受到傷害。 為了要完成上述之目的，本發明提供一種製造半導髖 元件的方法，其包含之步驟為：在半導醱基板上形成一 第一絶緣層，在該第一绝緣層上形成一導電膜，處理該 導電膜，以在半導龌基板邊線部分，形成一末端位在第 一絶緣層末端内部之電棰接線層，在包含第一绝緣層和 電探接線層之半導體基板上形成一絶緣膜，及藉由處理 該绝緣膜，在半導體基板的邊緣部分之上，形成一末端 位在電搔接線層末端的外部之第二絶緣層》 阃式簡述 第1圖為根據本發明實施例之半導普晶1_的平面圖； 第2A-2L圖為示於第1圏之半導羼晶圈製造方法的步 驟，顯示晶画邊緣部分的横截面國；及 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公釐） (讀先聞讀背面之注$項再填寫本頁) ih. -T -* 經濟部中央標準局負工消費合作社印製 A7 _B7_______ 五、發明説明（ί ) 第3圖為傅統半導龌晶圔之邊緣部分的横截面圖。 ff雄奮）ife例說明 本發1明將參考附圏詳細説明。 第]圖為根據本發明實施例之半導釅晶圏，參考第1 圖，許多其有半導饉積體霄路形成在其中之半導鑤晶片 20排列在一半導體晶圆10上（多表面焊接），在晶圏邊線 部分30之上，並未有形成晶H20,因為晶鬪在蓮送期間， 可能會輿晶國箝夾裝置，如夾具接觸，而光阻會在蝕刻 之前，自晶國邊緣部分3 0移除，因此層間绝緣膜和電棰 接線層會自晶鬮邊緣部分30移除。 半導髅元件製造方法之説明將取晶國邊緣部分3(1沿A-A’線的横截面參考。 首先，如第2A圖所示，由氧化矽製成之绝緣膜1〇2係形 成在延鑲第1圏之半導體晶國1〇的矽晶國1〇1之上，在砂 晶圓101的晶片成形匾域，半導鱧零件，如M0S(金氧半） 電晶體，僳形成在绝緣膜102之下。 為了要在绝緣膜10 2的設定位置形成一接觸孔（未顬示） ，如第2B國所示，在絶緣膜102上形成一光阻國案1〇3,晶 國邊緣部分30之光阻圆案103的末端傜位在矽晶國末 端的内部，之後，利用光阻圏案1〇 3當作遮罩，選擇性 蝕刻絶緣膜102，因而形成一第一層間絶緣膜l〇2a(參見 第2C國）。 、 移除光阻画案103，然後在包含第一層間绝緣膜l〇2a 之晶圖101的表面匾域形成一金腸膜如第2C圖所示， 本紙張尺度逡用中國國家標準（CNS > A4規格（210X297公釐） (請先閲讀背面之注f項再填寫本頁) 訂 --终 經濟部中央標率局員工消费合作社印m A7 B7 五、發明説明（t ) 接著，在金颶膜1M上形成一用以形成接線圖案之光阻圍 案105,在晶鬮邊緣部分30之光阻圈案105的末端部分你 位在第1 一層間絶緣膜102a末端的内部，換言之，可以設 為Ϊ1，其中W1為晶圓101末端和金靨膜104末端之間的 距離，而W2則為晶國101末端和光阻團案1〇5之間的距離❶ 使用光阻圈案10 5當作遮罩，遘擇性蝕刻金饜膜1〇4， 因而會在第一層間絶緣膜1〇2 a上形成一第一鬣棰接線層 l〇4a，如第2D國所示，因此，晶圜遴绦部分30之第一電 搐接線層l〇4a末端僳位在第一層間绝緣膜1〇2 a末端的内 部，在形成第一電棰接線層11H a之後，就要移除光阻圖 案 105〇 如第2E圓所示，在包含第一電棰接線層l〇4a和第一層 間絶線膜102a之晶圓101的表面匾域上，形成一绝緣膜 106，因為在晶國邊綠部分30上只有形成兩層，所以在 第一電搔接線層l〇4a末端上之絶緣膜1〇 &並不會變的很 薄。 如第2F画所示，藉由CMP法平坦化絶緣膜的表面， 因為在晶國邊緣部分30上之绝緣膜106並不是非常薄，所 以加上所述，第一電榷接線層l〇4a末端不會因藉由CMP 法實行平坦化而曝霉出來。 為了要形成接觸孔，以連接到第一轚極接線層104»或 零件，如第2G圏所示，要在平坦化的绝緣膜上形成 一光阻圃案107,在晶圖邊緣部分30上之光阻圈案107的 末端位置與第一層間絶緣膜1 0 2 a末端相同或位在其外销 -8 - 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） (請先閲讀背面之注$項再填寫本頁) 、tr 镇 經濟部中央標率局負工消費合作社印製 A7 __B7 __ 五、發明説明（7 ) ，換言之，設定W2SW3,其中W3為晶圖101末端和光阻 國案107末端和光阻國案107末端之間的距離。 利用1光阻國案1 Η當作遮罩，選擇性蝕刻絶緣膜1 0 6， 因而可以形成一第二層間絶緣膜l〇6a,如第2Β圓所示，在 形成第二層間絶緣膜106a之後，移除光阻國案1〇7。 如第21画所示，在包含第二層間绝緣膜1〇 6a之晶園101 的表ffi匾域上，形成一金屬膜108,如第2J圖所示，再在 金臑膜108上形成一用以形成接線圏案之光粗_案109,在 晶圚邊緣部分30上之光阻國案109的末端係位在第二層間 絶緣膜l〇6a末端的内饍，換言之，醮設定W4SW3,其中 W4為晶圓101末端和光阻圈案109末端之間的距離。 然後利用光阻圏案109當作遮罩，遘擇性蝕刻金颶膜 108,而形成一第二電極接線層l〇8a,如第2K_所示，在 形成第二電樺接線層10 8 a之後，再移除光阻圖案109,然 後在包含第二電棰接線層l〇8a和第二層間绝緣膜106a之 晶圖1 0 1的表面區域上，形成一絶錁膜11 〇 <» 如上所述，在晶圖邊緣部分30上之第一和第二電播接 線層104&和1〇8«1末端的形成位置幾乎相同，即：在晶國 _ ............ - · · · ·· · .. ----- , 邊緣位30上，第二接線層108_a末端並不是位在第一 電榷接線雇丄〇4a末端的内傅。 因此，在晶圖邊緣部分30上，在第一電棰接線層104a 末端上之絶緣膜U 0的厚度，並不會變得b其他匾域薄， 卽使當使用CMP法平坦化絶線膜11〇時，如第2L豳所示， 在晶圓邊緣部分30上，第一電棰接線層l〇4a末端也有第 -9- 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） {請先聞讀背面之注$項再填寫本頁) 訂 A7 B7 五、發明説明（^ ) 二層間絶緣膜l〇6a和絶緣膜110覆蓋，因此不會曝露出 來，同理，第二電棰接線層108a末端有絶緣膜110覆蓋， ( 也不會曝靄出來。 在相同情形下，在晶圓邊緣部分上，形成一上電極接 線層，使得其末端不會位在下電極接線層末端的内榭， 而且形成一延伸到下電棰接線層外倒之層間絶緣膜，結 果，如上述相同的情形，當藉由CM P法平坦化絶緣膜表 面時，在晶圖邊緣部分之電楠接線層末端可以避免會曝 露出來。 如上所逑，根據本發明，當藉由CMP法平坦化層間相 互連接結構之層間絶緣層時，在晶圓邊緣部分上已形成 之下電槿接線層末端不會曝露出來，結果，不會産生電 極接線層的碎H,因此不會傷害到研磨的表面。 (請先閲讀背面之注意事項再填寫本頁) 訂 铲 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐〉 經濟部中央標率局員工消費合作社印製 A7 B7 五、發明説明（？） 參考符號說明 10... .•半 導 體 晶 國 2 0... ..半 導 體 晶 Η 30… .•邊 緣 部 分 10 1.. ..矽 晶 圓 10 2.. .•绝 緣 膜 102a . • •第 一 層 間 絶 緣 膜 103 .. .•光 阻 團 案 104 .. ..金 羼 膜 104a . ..第 - 電 極 接 線 層 10 5.. .•光 阻 圖 案 106.. • · Μ)〇 緣 膜 106a. .•第 二 靥 間 絶 緣 膜 1 0 8 . · •-金 騰 膜 109.. .•光 阻 圖 案 110·. .•絶 緣 膜 1 .… ..矽 基 板 2 .… ..第 一 層 間 絶 緣 膜 3 .… ..電 極 接 線 層 4 ·… •.第 二 層 間 絶 緣 膜 107.. ..光 阻 圖 案 108a . .•第 二 電 掻 接 線 層 -11- (請先聞讀背面之注意事項再填寫本頁) 訂 济 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）I The outermost edge end surface of the first layer is exposed on the edge portion of the wafer. If the third layer of photoresist film on the edge of the crystal core is removed outside the outermost edge of the second layer, the outermost edge lizard of the third layer will become outside of the outermost edge of the second layer. Therefore, Above the outermost end of the green portion of the crystal edge, the first and third layers are not expected to contact each other. In this case, if the adhesion between the first and third layers is poor, the edge end of the third layer at the edge of the crystal country will peel off from the first layer, and an external factor will be generated. The first and third electrodes form a pole electrode wiring layer, and there will still be a flow of "II" in the middle. "The third circle is a conventional semiconductor device of Japanese Patent Gazette No. 8-31710 without this problem. The first layer is insulated. The film 2, the electrode wiring layer 3, and the second interlayer insulating film 4 are sequentially formed on the silicon substrate 1. Referring to FIG. 3, the light coarse film removal area during the lithography process is designed so that it is formed later on the crystal ring The outermost edge of the layer above the edge part will be located further inside. "The Central Bureau of Standards and Economics, Bureau of Labor and Engineering Cooperatives, is printed on the fusible semiconductor element shown in the third circle because the end of the electrode wiring layer 3 is exposed. At the edge of the crystal pattern, if the surface of the second interlayer insulating film 4 is ground using the CMP method, it is not desirable that the second interlayer insulating film 4 is grounded and broken, and some broken fragments may enter the polished surface Causes injury. When the electrode wiring layer 3 is not formed on the outermost edge of the edge portion of the wafer, but is covered by the second interlayer insulating film 4, it is closer to -5-This paper standard is commonly used by China National Standards (CNS ) Α4 size (210X297mm) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative A7 ___ B7____ V. Description of the invention (4) The thickness of the edge of the crystal ridge is thinner at the edge of the crystal picture, especially three or more 餍In the lower layer part, the thickness of the edge is thinner. For this reason, if the second interlayer insulating film 4 on the electric wiring layer 3 is pseudo-polished using the CMP method, the second interlayer insulating film 4 that has been thinned at the edge of the crystal pattern will be more grounded and disappear, Then, the end of the electric wire connection 3 will be exposed. In this case, when the CMP method is used to hold the mine, the electric wire connection layer 3 that is moldy will be grounded, and then the broken pieces will enter the grinding of the interlayer insulation film. Damage to the surface》 mmmm The object of the present invention is to provide a semiconductor device having a multilayer interconnection structure and a manufacturing method thereof, in which the surface of the interlayer insulating film is not damaged by chemical mechanical polishing. In order to achieve the above object, the present invention provides a method for manufacturing a semiconducting hip element, which includes the steps of: forming a first insulating layer on a semiconducting gill substrate, and forming a conductive film on the first insulating layer Processing the conductive film to form an electrical wiring layer whose end is located inside the end of the first insulating layer on the edge portion of the semiconductor substrate, and forming a semiconductor substrate including the first insulating layer and the electrical wiring layer on the semiconductor substrate. An insulating film, and by processing the insulating film, a second insulating layer whose end is located outside the end of the electric wiring layer is formed on the edge portion of the semiconductor substrate. A plan view of the semiconducting crystal 1_ of the embodiment; FIGS. 2A-2L are the steps shown in the method of manufacturing the semiconducting crystal ring of the first frame, showing the cross-section of the edge portion of the crystal painting; and this paper scale applies to China National Standards (CNS) A4 Specification (210X297mm) (Read the first note on the back and fill in this page) ih. -T-* Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _B7_______ V. Invention Explanation (ί) Figure 3 is Fu Semiconductive cross-sectional view of the edge portion of filthy crystal Ya. ff Xiong Fen) ife example explanation The present invention will be described in detail with reference to the attached text. FIG. 1 is a semiconducting semiconductor wafer according to an embodiment of the present invention. Referring to FIG. 1, many semiconductor wafers 20 having semiconductor semiconductor integrated circuits formed therein are arranged on a semiconductor wafer 10 (multiple Surface welding), there is no crystal H20 formed on the edge part 30 of the crystal wafer, because the crystal wafer may be clamped by the crystal clamping device, such as a clamp, during contact, and the photoresist will be The wafer edge portion 30 is removed, so the interlayer insulating film and the electrical wiring layer are removed from the wafer edge portion 30. The description of the manufacturing method of the semiconductor cross element will be based on the cross section of the crystal edge portion 3 (1 along the AA 'line. First, as shown in FIG. 2A, an insulating film 102 made of silicon oxide is used. It is formed on the silicon wafer 10 of the semiconductor wafer 10 which is set on the first wafer, and the wafer formation plaque area of the sand wafer 101 is made of semiconductor wafers, such as M0S (metal oxide semiconductor) transistors. It is formed under the insulating film 102. In order to form a contact hole (not shown) at a set position of the insulating film 102, as shown in country 2B, a photoresist national case 1 is formed on the insulating film 102. 3. The end of the photoresist pattern 103 in the edge part 30 of the crystal country is located inside the end of the silicon crystal. Then, the photoresist pattern 103 is used as a mask to selectively etch the insulating film 102, thereby forming a The first interlayer insulating film 102a (see country 2C). Remove the photoresist pattern 103, and then form a gold intestine on the surface plaque area of the crystal map 101 containing the first interlayer insulating film 102a. The film is as shown in Figure 2C. This paper uses the Chinese national standard (CNS > A4 size (210X297 mm)) (please read the note f on the back before filling this page). Order- Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs m A7 B7 V. Description of the Invention (t) Next, a photoresist enclosure 105 for forming a wiring pattern is formed on the golden hurricane film 1M, and the light at the edge portion 30 of the crystal The end part of the circle 105 is located inside the end of the first interlayer insulating film 102a. In other words, it can be set to Ϊ1, where W1 is the distance between the end of the wafer 101 and the end of the gold film 104, and W2 is The distance between the end of Jinguo 101 and the photoresist case 105. Using the photoresist case 105 as a mask, the gold film 10 is selectively etched, so it will be the first interlayer insulating film 10. A first iguana wiring layer 104a is formed on 2a, as shown in country 2D. Therefore, the end of the first electroconvection wiring layer 104a of the crystal unit 30 is insulated between the first layers. Inside the end of the film 102a, after the first electrical wiring layer 11Ha is formed, the photoresist pattern 105 is removed. As shown in circle 2E, the first electrical wiring layer 104a and An insulating film 106 is formed on the surface plaque of the wafer 101 of the interlayer insulating film 102a, because only two layers are formed on the green part 30 of the crystal edge Therefore, the insulating film 10 & on the end of the first electrical wiring layer 104a will not become very thin. As shown in Figure 2F, the surface of the insulating film is planarized by the CMP method, because The insulating film 106 on the edge portion 30 is not very thin, so as mentioned, the end of the first electrical wiring layer 104a will not be exposed due to flattening by the CMP method. In order to form a contact Hole to connect to the first electrode wiring layer 104 »or part, as shown in 2G 圏, to form a photoresist box 107 on the planarized insulating film, and a photoresist on the edge portion 30 of the crystal pattern The end position of circle 107 is the same as the end of the first interlayer insulating film 1 0 2 a or it is located in the export -8-This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) (Please read the back Note the $ item and fill in this page), tr printed by the Central Standards Bureau of the Ministry of Economic Affairs, Consumers Cooperative of A7 __B7 __ 5. Description of the invention (7), in other words, set W2SW3, where W3 is the end of the crystal picture 101 and the country of photoresistance The distance between the 107 end and the 107 end of the photoresist case. Using 1 photoresist case 1 Η as a mask, the insulating film 106 is selectively etched, so a second interlayer insulating film 106a can be formed. As shown in the second circle B, a second interlayer insulating film 106a is formed. After that, the National Photoresist Case 107 was removed. As shown in picture 21, a metal film 108 is formed on the surface of the wafer 101 including the second interlayer insulating film 106a, as shown in FIG. 2J, and then formed on the gold film 108 A thick light case 109 is used to form the wiring case. The end of the photoresist case 109 on the edge portion 30 of the crystal is located at the end of the second interlayer insulating film 106a. In other words, W4SW3 is set. Where W4 is the distance between the end of the wafer 101 and the end of the photoresist ring 109. Then, a photoresist pattern 109 is used as a mask to selectively etch the gold hurricane film 108 to form a second electrode wiring layer 108a. As shown in 2K_, a second electric birch wiring layer 10 8 is formed. After a, the photoresist pattern 109 is removed, and then an insulating film 11 is formed on the surface area of the crystal pattern 101 including the second electric wiring layer 108a and the second interlayer insulating film 106a. ; »As mentioned above, the formation positions of the first and second telecast wiring layers 104 & and 108« 1 on the edge portion 30 of the crystal pattern are almost the same, that is, in the crystal country _... ...-· · · · · · .. -----, On the edge position 30, the end of the second wiring layer 108_a is not the inner fu at the end of the first electrical wiring 丄 〇4a. Therefore, the thickness of the insulating film U 0 on the end of the first electrical wiring layer 104a on the edge portion 30 of the crystal pattern does not become thinner than other plaques, so that when the CMP method is used to planarize the insulating film At 11:00, as shown in 2L, on the wafer edge portion 30, the end of the first electrical connection layer 104a also has a -9th. This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 mm) ) {Please read the note on the back before filling in this page) Order A7 B7 V. Description of the invention (^) The two-layer interlayer insulating film 106a and the insulating film 110 are covered, so they will not be exposed. Similarly, the second The end of the electrical wiring layer 108a is covered with an insulating film 110, and will not be exposed. In the same situation, an upper electrode wiring layer is formed on the edge portion of the wafer so that its end is not located at the end of the lower electrode wiring layer In addition, an interlayer insulating film extending to the outside of the lower wiring layer is formed. As a result, when the surface of the insulating film is flattened by the CM P method as in the same situation as above, the electric film on the edge portion of the crystal pattern The end of the wiring layer can be prevented from being exposed. According to the present invention, when the interlayer insulating layer of the interlayer interconnection structure is planarized by the CMP method, the end of the lower electric wiring layer that has been formed on the edge portion of the wafer will not be exposed, and as a result, no electrode wiring layer will be generated. Broken H, so it will not hurt the polished surface. (Please read the precautions on the back before filling out this page) Ordering paper printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Cooperatives The paper is printed in accordance with Chinese National Standard (CNS) A4 specifications ( 210X297mm> Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (?) Reference symbol description 10 .... • Semiconductor Crystal Country 2 0 ... ..Semiconductor Crystalline 30…. • Edge part 10 1.... Silicon wafer 10 2.. • Insulation film 102 a. • • First interlayer insulation film 103... • Photoresist case 104... Au film 104a... The first-electrode wiring layer 10 5... • photoresist pattern 106 .. • • M) 〇 edge film 106 a.. • second interlayer insulating film 1 0. Photoresist pattern 11 0 · .. • Insulating film 1 .. .. Silicon substrate 2 .. .. First interlayer insulating film 3... .. electrode wiring layer 4... • Second interlayer insulating film 107... Pattern 108a. .. • The second electrical wiring layer -11- (Please read the notes on the back before filling this page) The paper size applies to the Chinese National Standard (CNS) A4 (210X297 mm)