TWI402015B - Integration of surface mount components of the packaging structure - Google Patents
Integration of surface mount components of the packaging structure Download PDFInfo
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- TWI402015B TWI402015B TW098117698A TW98117698A TWI402015B TW I402015 B TWI402015 B TW I402015B TW 098117698 A TW098117698 A TW 098117698A TW 98117698 A TW98117698 A TW 98117698A TW I402015 B TWI402015 B TW I402015B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明為一種將表面黏著型元件經由真空熱壓合技術所進行之整合封裝結構,提供承載與結構保護的功能,並確保訊號與能量的傳遞。The invention provides an integrated package structure for surface-adhesive components through vacuum thermocompression bonding technology, provides functions of bearing and structure protection, and ensures signal and energy transmission.
隨著半導體產業的高度發展,未來電子產品強調輕薄短小、高速、高腳數等特性,以導線架為基礎的傳統封裝型態將漸不適用,因此在封裝製程上亦面臨諸多挑戰,諸如封裝材料的選用、封裝製程中金線數目的高密度集積化,以及模流充填時所產生的金線偏移與薄形封裝翹曲變形等問題,都是產業界目前所遭遇,而需投入研究的範疇。With the development of the semiconductor industry, future electronic products emphasize the characteristics of light and thin, high speed, high pin count, etc. The traditional package type based on lead frame will gradually become unsuitable, so there are also many challenges in the packaging process, such as packaging. The selection of materials, the high-density accumulation of the number of gold wires in the packaging process, and the gold wire migration caused by the mold filling and the warping deformation of the thin package are all encountered in the industry, and need to be invested in research. The scope.
在習知的半導體晶片封裝方面,打線接合封裝(Wire Bonding)或覆晶接合封裝(Flip-Chip)是一般常見的封裝技術。Wire bonding or Flip-Chip is a common packaging technology in the conventional semiconductor chip package.
打線接合封裝係將晶片直接黏貼於介電基板表面,採用打線接合製程將晶片之接點與介電基板表面之焊墊(Pad)形成電性連接,應用壓模灌膠技術(Molding)將環氧樹脂材料(Epoxy)加以封裝,以保護晶片避免受到化學或機械外力的破壞,再藉由植球陣列(Ball Grid Array)技術提供介電基板與外界裝置之電性連接。The wire bonding package directly adheres the wafer to the surface of the dielectric substrate, and electrically connects the contacts of the wafer to the pads of the dielectric substrate by a wire bonding process, and applies a mold filling technique (Molding) to form a ring. The epoxy resin material (Epoxy) is encapsulated to protect the wafer from chemical or mechanical external forces, and the ball grid array technology (Ball Grid Array) technology is used to provide electrical connection between the dielectric substrate and the external device.
至於覆晶封裝則是將錫鉛凸塊或錫球之金屬導體,應用迴焊(Reflow)製程使金屬導體黏著於晶片接點表面,接著將晶片上的金屬導體對應匹配放置於介電基板之焊墊上,再經迴焊製程形成電性接合,接著採用底膠填充(Underfill Dispensing)製程,讓封膠流體佈滿晶片與介電基板之間隙,再藉由植球陣列技術提供介電基板與外界裝置之電性連接。As for the flip chip package, the tin-lead bump or the metal ball of the solder ball is applied to the surface of the wafer contact by a reflow process, and then the metal conductor on the wafer is matched and placed on the dielectric substrate. The bonding pad is electrically connected by a reflow process, and then an underfill dispensing process is performed to allow the sealing fluid to fill the gap between the wafer and the dielectric substrate, and then the dielectric substrate is provided by the ball placement array technology. Electrical connection of external devices.
在覆晶封裝底膠填充的製程中,因採單邊填膠方式所以必須花費一段時間才能讓封膠流體佈滿介電基板與覆晶片之間隙。此外,晶片、介電基板、金屬導體和充填材料的熱膨脹係數有相當大的差異性。In the process of filling the flip chip package, it takes a period of time for the sealant fluid to fill the gap between the dielectric substrate and the wafer due to the unilateral filling method. In addition, there are considerable differences in the thermal expansion coefficients of wafers, dielectric substrates, metal conductors, and filler materials.
其中晶片的熱膨脹係數大約為百萬分之2.3/度(2.3ppm/℃),FR-4介電基板的熱膨脹係數則為百萬分之18/度(18ppm/℃),銲錫凸塊的熱膨脹係數為百萬分之24/度(24ppm/℃),而環氧樹脂的膨脹係數為百萬分之70/度(70ppm/℃)。尤其是晶片與介電基板的熱膨脹係數差異最大,當溫度出現變化時,會產生不一致的熱膨脹效應而使得整個封裝出現變形的現象,並且會在覆晶與基板的銲錫連接上出現剪應力,一般銲錫熔點約在攝氏180~400度之間,容易達到其降服點而對整體封裝的結構產生破壞性。另外,在傳統的打線接合封裝的製程中,於進行灌膠製程後,有時會因為黏度強度不足而出現分層的現象。The thermal expansion coefficient of the wafer is about 2.3/kWh (2.3 ppm/°C), and the thermal expansion coefficient of the FR-4 dielectric substrate is 18/kWh (18 ppm/°C). Thermal expansion of the solder bumps. The coefficient is 24/kWh (24 ppm/°C) and the expansion coefficient of the epoxy resin is 70/kWh (70 ppm/°C). In particular, the difference in thermal expansion coefficient between the wafer and the dielectric substrate is the greatest. When the temperature changes, an inconsistent thermal expansion effect occurs, causing deformation of the entire package, and shear stress occurs on the solder connection of the flip chip and the substrate. The solder has a melting point of about 180 to 400 degrees Celsius, and it is easy to reach its drop point and destructive to the overall package structure. In addition, in the conventional wire bonding package process, after the potting process, delamination sometimes occurs due to insufficient viscosity strength.
目前在電路佈設方面,線路載板是經常使用的構裝元件,該線路載板大多是印刷電路板或晶片載板等線路載板。一般的線路載板主要是由多層圖案化線路層及多層介電層交替疊合所構成,其中介電層配置於任二相鄰之圖案化線路層之間,而這些圖案化線路層可藉由貫穿介電層之鍍通孔道或導電孔道而彼此電性連接。At present, in terms of circuit layout, the line carrier is a commonly used component, and the line carrier is mostly a circuit carrier such as a printed circuit board or a wafer carrier. A general line carrier is mainly composed of a plurality of patterned circuit layers and a plurality of dielectric layers alternately stacked, wherein the dielectric layer is disposed between any two adjacent patterned circuit layers, and the patterned circuit layers can be borrowed Electrically connected to each other by plated through holes or conductive vias through the dielectric layer.
由於線路載板具有佈線細密、組裝緊密以及良好的性能等優勢,因此線路載板已廣泛應用於電子封裝結構中,特別是植球陣列技術的封裝體。當訊號在線路載板傳遞時,可藉由被動元件(例如電阻、電容、電感等)消除雜訊以及穩定電路來改善訊號傳輸的品質,另外在天線線路的佈線方面,亦可藉由被動元件的設置作為電性阻抗匹配及頻率調整之目的,但該被動元件係設置在線路載板的表面,使得線路載板體積增大而無法達到縮小體積的目的。此外,隨著電子產品功能性的多樣化,將使得線路載板的體積變大,同樣地無法達到輕薄短小之目的。Due to the advantages of fine wiring, tight assembly and good performance of the line carrier, the line carrier has been widely used in electronic packaging structures, especially the package of the ball placement technology. When the signal is transmitted on the line carrier, the noise can be improved by passive components (such as resistors, capacitors, inductors, etc.) to eliminate noise and stabilize the circuit. In addition, in the wiring of the antenna line, passive components can also be used. The setting is for the purpose of electrical impedance matching and frequency adjustment, but the passive component is disposed on the surface of the line carrier, so that the line carrier is increased in volume and cannot achieve the purpose of reducing the volume. In addition, with the diversification of the functionality of electronic products, the volume of the line carrier will be increased, and the same purpose cannot be achieved.
本發明整合表面黏著型元件之封裝結構的主要目的在於將晶片天線與被動元件封裝結構模組化,藉由改變被動元件值的大小,得以調整頻率範圍的自由度以及性能,提高天線特性阻抗與系統端阻抗匹配,以達符合電性特性之要求,並且減少佔用印刷電路板面積,來縮小整體的體積,俾增加印刷電路板之利用空間。The main purpose of the package structure of the surface-adhesive component of the present invention is to modularize the chip antenna and the passive component package structure. By changing the value of the passive component value, the degree of freedom and performance of the frequency range can be adjusted, and the characteristic impedance of the antenna is improved. The system-side impedance is matched to meet the requirements of electrical characteristics, and the occupation of the printed circuit board area is reduced, thereby reducing the overall volume and increasing the utilization space of the printed circuit board.
本發明之次要目的在於改善結構封膠與介電基板之結合強度,提供承載與結構保護的功能,避免物理性質的破壞和化學性質的侵蝕,確保訊號與能量的傳遞,並發展出一種全新不同的半導體封裝製程,且能降低生產成本。The secondary objective of the present invention is to improve the bonding strength between the structural sealant and the dielectric substrate, to provide the function of bearing and structure protection, to avoid physical property damage and chemical corrosion, to ensure signal and energy transmission, and to develop a brand new Different semiconductor packaging processes can reduce production costs.
本發明之另一目的在於將不同的晶片或已封裝完成的疊層晶片或其他電子組件整合於同一封裝模組內(例如射頻模組或其他整合型系統晶片)成為複合式的封裝體,提供承載與結構保護的功能,確保訊號與能量的傳遞。Another object of the present invention is to integrate different wafers or packaged stacked wafers or other electronic components into a package module (such as a radio frequency module or other integrated system chip) into a composite package. The function of carrying and structure protection ensures the transmission of signals and energy.
為達上揭目的,本發明係提供一種整合表面黏著型元件之封裝結構,其包含:一介電基板;一設於介電基板上表面的第一表面金屬層,該第一表面金屬層形成一預定之線路圖案及有複數個焊墊;一設於介電基板下表面的第二表面金屬層;複數個設於介電基板內部的鍍通孔道,用以電性連接第一表面金屬層及第二表面金屬層;複數個黏著於第一表面金屬層表面的被動元件;以及一覆蓋於介電基板上表面的封裝膠板,該封裝膠板密封第一表面金屬層及其表面黏著的被動元件。In order to achieve the above object, the present invention provides a package structure for integrating a surface-adhesive component, comprising: a dielectric substrate; a first surface metal layer disposed on an upper surface of the dielectric substrate, the first surface metal layer being formed a predetermined circuit pattern and a plurality of pads; a second surface metal layer disposed on the lower surface of the dielectric substrate; and a plurality of plated through holes disposed inside the dielectric substrate for electrically connecting the first surface metal layer And a second surface metal layer; a plurality of passive components adhered to the surface of the first surface metal layer; and a sealing rubber plate covering the upper surface of the dielectric substrate, the sealing rubber plate sealing the first surface metal layer and the surface thereof adhered Passive components.
本發明進一步揭露一種整合表面黏著型元件之封裝結構,其包含:一介電基板;一第一表面金屬層,係設於該介電基板之上表面形成一預定之線路圖案以及有複數個焊墊;一第二表面金屬層,係設置於該介電基板之下表面;複數個鍍通孔道,設置於該介電基板內部,並電性連接該第一表面金屬層及第二表面金屬層;複數個被動元件,係黏著於第一表面金屬層之表面;一晶片,係設置於第一表面金屬層表面,並具有複數個晶片接點;複數條金屬接線,係搭接於該等晶片接點,並與第一表面金屬層的焊墊表面連接;一封裝膠板,係覆蓋於該介電基板之上表面,用以密封該第一表面金屬層、複數個被動元件、複數個金屬接線及晶片;以及複數個錫球,係設置於第二表面金屬層之表面。The invention further discloses a package structure for integrating a surface-adhesive component, comprising: a dielectric substrate; a first surface metal layer disposed on the upper surface of the dielectric substrate to form a predetermined circuit pattern and having a plurality of soldering a second surface metal layer is disposed on the lower surface of the dielectric substrate; a plurality of plated through holes are disposed in the dielectric substrate and electrically connected to the first surface metal layer and the second surface metal layer a plurality of passive components attached to the surface of the first surface metal layer; a wafer disposed on the surface of the first surface metal layer and having a plurality of wafer contacts; a plurality of metal wires lapped to the wafers a contact and is connected to the surface of the pad of the first surface metal layer; a sealing rubber plate covering the upper surface of the dielectric substrate for sealing the first surface metal layer, the plurality of passive components, and the plurality of metals Wiring and wafer; and a plurality of solder balls are disposed on the surface of the second surface metal layer.
該封裝結構可進一步於封裝膠板上方設置一第三表面金屬層,並由鍍通孔道貫通介電基板及封裝膠板內部,使第一表面金屬層、第二表面金屬層與第三表面金屬層電性連接。The package structure may further be provided with a third surface metal layer above the package rubber plate, and penetrate the dielectric substrate and the interior of the package rubber plate through the plated through holes, so that the first surface metal layer, the second surface metal layer and the third surface metal layer Layer electrical connection.
本發明更進一步揭露一種整合表面黏著型元件之封裝結構,係由一介電基板、一設於介電基板上表面的第一表面金屬層、一設於介電基板下表面的第二表面金屬層、複數個設於介電基板內部連通的鍍通孔道、一黏著於第一表面金屬層表面的電子組件以及一覆蓋於介電基板上表面的封裝膠板所構成,該第一表面金屬層具有一預定線路圖案以及複數個焊墊,該鍍通孔道用以電性連接第一及第二表面金屬層,該封裝膠板用以密封該第一表面金屬層及其表面黏著的電子組件。The present invention further discloses a package structure for integrating a surface mount component, comprising a dielectric substrate, a first surface metal layer disposed on the upper surface of the dielectric substrate, and a second surface metal disposed on the lower surface of the dielectric substrate a layer, a plurality of plated through holes provided in the interior of the dielectric substrate, an electronic component adhered to the surface of the first surface metal layer, and an encapsulant plate covering the upper surface of the dielectric substrate, the first surface metal layer The device has a predetermined circuit pattern and a plurality of solder pads for electrically connecting the first and second surface metal layers, and the package rubber plate is used for sealing the first surface metal layer and the electronic components adhered to the surface.
本發明再進一步揭露一種整合表面黏著型元件之封裝結構,係包含複數個介電基板;複數個表面金屬層,設置於該各個介電基板之上表面及下表面;複數個鍍通孔道,設置於該介電基板內部連通各個表面金屬層,使彼此電性連接;一電子組件,係黏著於表面金屬層上;複數個封裝膠板,係覆蓋於介電基板之表面,用以包覆密封該表面金屬層及其表面黏著之電子組件。其中,該封裝膠板亦可作為多層介電基板間的黏合層,達到多疊層封裝的結構體。The invention further discloses a package structure for integrating a surface-adhesive component, comprising a plurality of dielectric substrates; a plurality of surface metal layers disposed on the upper surface and the lower surface of the respective dielectric substrates; and a plurality of plated through holes, The inner surface of the dielectric substrate is connected to each other to electrically connect to each other; an electronic component is adhered to the surface metal layer; and a plurality of sealing rubber sheets are coated on the surface of the dielectric substrate for covering and sealing The surface metal layer and the electronic components to which the surface is adhered. The package rubber board can also be used as an adhesive layer between the multilayer dielectric substrates to achieve a multi-layer package structure.
上述介電基板採用由介電樹脂與玻璃纖維所構成的複合材料或介電樹脂與陶瓷板材或陶瓷粉末所構成的複合材料,上述第一與第二表面金屬層之線路採用曝光、顯影與蝕刻銅箔、電鍍、噴塗、印刷、網印燒結或其組合方式將線路建構在介電基板表面,上述電子組件係為一個以上的電子元件、主動元件、被動元件、射頻模組、積體電路晶片組、晶片天線或其他表面黏著型元件之組合,上述晶片、元件、模組是藉由表面黏著技術將其黏著於第一表面金屬層之表面。The dielectric substrate adopts a composite material composed of a dielectric resin and glass fibers or a composite material composed of a dielectric resin and a ceramic plate or ceramic powder, and the lines of the first and second surface metal layers are exposed, developed and etched. Copper foil, electroplating, spray coating, printing, screen printing sintering or a combination thereof to form a circuit on the surface of a dielectric substrate, the above electronic component is more than one electronic component, active component, passive component, radio frequency module, integrated circuit chip A combination of a group, a wafer antenna or other surface-mounting component, the wafer, component, and module are adhered to the surface of the first surface metal layer by surface adhesion techniques.
於一較佳實施例中,該介電基板的介電常數介於2至50之間,該被動元件係採用電阻、電容或電感或其組合的任一種方式構成;上述封裝膠板採用介電樹脂與陶瓷材料所構成之熱固性複合材料,以真空熱壓合製程(Hot Press Lamination)加熱與加壓,使其軟化並均勻地流動於介電基板的上表面。In a preferred embodiment, the dielectric substrate has a dielectric constant of between 2 and 50. The passive component is formed by using any one of a resistor, a capacitor or an inductor, or a combination thereof. The package board is dielectric. The thermosetting composite material composed of the resin and the ceramic material is heated and pressurized by a vacuum press lamination process to soften and uniformly flow on the upper surface of the dielectric substrate.
本發明最後揭露一種整合表面黏著型元件之封裝結構,其應用於天線結構包含:一介電基板;一第一表面金屬層,係設置於該介電基板上表面並形成一預定之線路圖案;一第二表面金屬層,係設置於該介電基板之下表面;複數個被動元件,係黏著於第一表面金屬層之表面;一晶片,係設置於介電基板之上表面,並與第一表面金屬層電性連接;一封裝膠板,係覆蓋於該介電基板之上表面,用以包覆密封該第一表面金屬層及其表面黏著之複數個被動元件與晶片;一第三表面金屬層,係設置於該封裝膠板之上表面;以及複數個鍍通孔道。The invention finally discloses a package structure for integrating a surface-adhesive component, wherein the antenna structure comprises: a dielectric substrate; a first surface metal layer disposed on the upper surface of the dielectric substrate and forming a predetermined circuit pattern; a second surface metal layer is disposed on the lower surface of the dielectric substrate; a plurality of passive components are adhered to the surface of the first surface metal layer; and a wafer is disposed on the upper surface of the dielectric substrate, and a surface metal layer is electrically connected; a sealing rubber plate covers the upper surface of the dielectric substrate for covering and sealing the first surface metal layer and a plurality of passive components and wafers adhered to the surface thereof; The surface metal layer is disposed on the upper surface of the encapsulant sheet; and a plurality of plated through holes.
其中一部分鍍通孔道設於該介電基板內部連通該第一表面金屬層及第二表面金屬層,而另一部分鍍通孔道設於該介電基板與封裝膠板內部連通第一與第二及第三表面金屬層,使彼此電性連接,且該第三表面金屬層的鍍通孔道位置可電性連接一外界裝置或一增加天線輻射效果的導線或其他可導電結構。a part of the plated through hole is disposed in the inner surface of the dielectric substrate to communicate with the first surface metal layer and the second surface metal layer, and another portion of the plated through hole is disposed in the inner surface of the dielectric substrate and the package rubber plate. The third surface metal layer is electrically connected to each other, and the plated through hole position of the third surface metal layer is electrically connected to an external device or a wire or other electrically conductive structure that increases the radiation effect of the antenna.
本發明的功效在於透過晶片天線與被動元件封裝結構模組化,提高天線特性阻抗與系統端阻抗匹配,同時增加印刷電路板之利用空間,並改善結構封膠與介電基板之結合強度,以提供承載與結構保護的功能。The effect of the invention is to modularize the chip antenna and the passive component package structure, improve the antenna characteristic impedance and the system end impedance matching, increase the utilization space of the printed circuit board, and improve the bonding strength between the structural sealant and the dielectric substrate, Provides bearing and structural protection.
茲為便於更進一步對本發明之構造及其特徵有更深一層明確、詳實的認識與瞭解,現舉出較佳實施例說明本發明的新穎性及其他特點,並配合圖式詳細說明如下:請配合參閱第1圖及第2圖,係本發明之第一較佳實例,該整合表面黏著型元件之封裝結構(100)包括有:一介電基板(10a)、一第一表面金屬層(11a)、一第二表面金屬層(12a)、複數個鍍通孔道(13a)、複數個被動元件(30)、一封裝膠板(20a)。In order to facilitate further understanding and understanding of the structure and features of the present invention, the preferred embodiments of the present invention will be described with reference to the accompanying drawings. Referring to FIG. 1 and FIG. 2, a first preferred embodiment of the present invention, the package structure (100) of the integrated surface mount component comprises: a dielectric substrate (10a) and a first surface metal layer (11a) a second surface metal layer (12a), a plurality of plated through holes (13a), a plurality of passive components (30), and a sealing rubber plate (20a).
該介電基板(10a)係採用介電樹脂與玻璃纖維所構成之複合材料或介電樹脂與陶瓷板材或陶瓷粉末所構成的複合材料,該介電基板(10a)的介電常數介於2至50之間。The dielectric substrate (10a) is a composite material composed of a dielectric resin and glass fibers or a composite material composed of a dielectric resin and a ceramic plate or ceramic powder. The dielectric substrate (10a) has a dielectric constant of 2 Between 50.
該第一與第二表面金屬層(11a)(12a)之線路係採用曝光、顯影與蝕刻銅箔、電鍍、噴塗、印刷、網印燒結或其組合方式將線路建構在介電基板(10a)的上、下表面;該第一表面金屬層(11a)係設置於該介電基板(10a)之上表面形成一預定之線路圖案以及有複數個焊墊;該第二表面金屬層(12a)係設置於該介電基板(10a)之下表面。The lines of the first and second surface metal layers (11a) (12a) are formed on the dielectric substrate (10a) by exposure, development and etching of copper foil, electroplating, spraying, printing, screen printing sintering or a combination thereof. The upper surface and the lower surface; the first surface metal layer (11a) is disposed on the upper surface of the dielectric substrate (10a) to form a predetermined circuit pattern and has a plurality of pads; the second surface metal layer (12a) It is disposed on the lower surface of the dielectric substrate (10a).
該等鍍通孔道(13a)貫通於該介電基板(10a)內部與該第一表面金屬層(11a)及第二表面金屬層(12a)連接,讓該第一表面金屬層(11a)及第二表面金屬層(12a)可藉由貫穿介電基板(10a)的鍍通孔道(13a)彼此電性連接。The plated through holes (13a) are connected to the first surface metal layer (11a) and the second surface metal layer (12a) through the dielectric substrate (10a) to allow the first surface metal layer (11a) and The second surface metal layer (12a) may be electrically connected to each other by a plated through via (13a) penetrating through the dielectric substrate (10a).
該被動元件(30)藉由表面黏著技術將其黏著於第一表面金屬層(11a)之表面,用於串聯或並聯之電性連接,而該被動元件(30)係採用電阻、電容或電感或其中任兩者之組合,具有低成本取得、標準化規格的優點。The passive component (30) is adhered to the surface of the first surface metal layer (11a) by surface adhesion technology for electrical connection in series or in parallel, and the passive component (30) is made of a resistor, a capacitor or an inductor. Or a combination of both, with the advantages of low cost acquisition and standardized specifications.
該封裝膠板(20a)係覆蓋於該介電基板(10a)之上表面,以包覆密封該第一表面金屬層(11a)及其表面黏著之被動元件(30),該封裝膠板(20a)係採用介電樹脂與陶瓷材料所構成之熱固性複合材料,該封裝膠板(20a)係以真空熱壓合製程加熱與加壓,使其軟化並均勻地流動於介電基板(10a)之上表面,當封裝膠板(20a)持續地吸收能量後會產生聚合反應,而能均勻地黏合固化封裝該介電基板(10a)表面上的第一表面金屬層(11a)、被動元件(30),且藉由真空熱壓合製程能達到受熱均勻、受壓均勻、穩定流動,降低溫差所造成各材質熱膨脹效應而產生整體封裝出現翹曲變形的現象。藉由封裝膠板(20a)的保護,可避免物理性質的破壞和化學性質的侵蝕,確保訊號與能量的傳遞,使其發揮功能。The encapsulating sheet (20a) covers the upper surface of the dielectric substrate (10a) to encapsulate the first surface metal layer (11a) and the passive component (30) adhered to the surface thereof, the encapsulating sheet ( 20a) is a thermosetting composite material composed of a dielectric resin and a ceramic material, and the encapsulating rubber sheet (20a) is heated and pressurized by a vacuum thermocompression bonding process to soften and uniformly flow on the dielectric substrate (10a). The upper surface, when the encapsulating rubber sheet (20a) continuously absorbs energy, generates a polymerization reaction, and uniformly bonds and cures the first surface metal layer (11a) and the passive component on the surface of the dielectric substrate (10a). 30), and by the vacuum thermocompression bonding process, uniform heating, uniform pressure, and stable flow can be achieved, and the thermal expansion effect of each material caused by the temperature difference can be reduced to cause warpage deformation of the entire package. By protecting the encapsulating sheet (20a), physical properties and chemical attack can be avoided, and signal and energy transmission can be ensured to function.
請參閱第3圖所示,在習知印刷電路板(200)的天線電路佈線示意圖中,藉由設置數個被動元件(30)來達到天線電性阻抗匹配及頻率調整之目的,惟限定之被動元件(30)係設置於習知天線(40)周圍的線路佈線面積上,其缺點係降低電路基板(50)佈線的靈活性,及不符合無線通訊裝置輕薄短小的趨勢。Referring to FIG. 3, in the antenna circuit wiring diagram of the conventional printed circuit board (200), by setting a plurality of passive components (30) to achieve the purpose of antenna electrical impedance matching and frequency adjustment, but limited The passive component (30) is disposed on the wiring area around the conventional antenna (40), and has the disadvantage of reducing the flexibility of the wiring of the circuit substrate (50) and not conforming to the tendency of the wireless communication device to be light, thin and short.
請參閱第4圖所示,在印刷電路板(300)整合表面黏著型元件之封裝結構的天線電路佈線示意圖中,藉由減少設置於整合電子元件之封裝天線(41)周圍之線路佈線面積,進而增加電路基板(51)佈線的靈活性,達到無線通訊裝置輕薄短小之目的。Referring to FIG. 4, in the antenna circuit wiring diagram of the package structure of the printed circuit board (300) incorporating the surface-adhesive component, by reducing the wiring area around the package antenna (41) of the integrated electronic component, Furthermore, the flexibility of the circuit board (51) wiring is increased, and the wireless communication device is light, thin and short.
請配合參閱第5圖及第6圖,係本發明之第二較佳實例,該整合表面黏著型元件之封裝結構(400)包括有:一介電基板(10b)、一第一表面金屬層(11b)、一第二表面金屬層(12b)、一散熱金屬層(16)、複數個鍍通孔道(13b)、複數個被動元件(30)、一晶片(60)、複數個金屬接線(61)、一封裝膠板(20b)以及複數個錫球(63)。Referring to FIG. 5 and FIG. 6 , a second preferred embodiment of the present invention, the package structure ( 400 ) of the integrated surface mount component includes: a dielectric substrate (10b) and a first surface metal layer (11b), a second surface metal layer (12b), a heat dissipation metal layer (16), a plurality of plated through holes (13b), a plurality of passive components (30), a wafer (60), and a plurality of metal wires ( 61), a package rubber plate (20b) and a plurality of solder balls (63).
該介電基板(10b)係採用介電樹脂與玻璃纖維所構成之複合材料或或介電樹脂與陶瓷板材或陶瓷粉末所構成的複合材料,該介電基板(10b)的介電常數介於2至50之間。The dielectric substrate (10b) is a composite material composed of a dielectric resin and glass fibers or a composite material composed of a dielectric resin and a ceramic plate or ceramic powder, and the dielectric constant of the dielectric substrate (10b) is between Between 2 and 50.
該第一與第二表面金屬層(11b)(12b)線路係採用曝光、顯影與蝕刻銅箔、電鍍、噴塗、印刷、網印燒結或其組合方式將線路建構在介電基板(10b)的上、下表面;該第一表面金屬層(11b)係將複數個金屬片設於該介電基板(10b)之上表面形成一預定之線路圖案以及複數個焊墊;該第二表面金屬層(12b)係設置於該介電基板(10b)之下表面。The first and second surface metal layer (11b) (12b) lines are formed on the dielectric substrate (10b) by exposure, development and etching of copper foil, electroplating, spraying, printing, screen printing sintering or a combination thereof. The upper surface metal layer (11b) is formed by disposing a plurality of metal sheets on the upper surface of the dielectric substrate (10b) to form a predetermined line pattern and a plurality of pads; the second surface metal layer (12b) is disposed on the lower surface of the dielectric substrate (10b).
該等鍍通孔道(13b)貫通於該介電基板(10b)內部與該第一表面金屬層(11b)及第二表面金屬層(12b)連接,讓該第一表面金屬層(11b)及第二表面金屬層(12b)可藉由貫穿介電基板(10b)的鍍通孔道(13b)彼此電性連接。The plated through holes (13b) are connected to the first surface metal layer (11b) and the second surface metal layer (12b) through the dielectric substrate (10b) to allow the first surface metal layer (11b) and The second surface metal layer (12b) may be electrically connected to each other by a plated through via (13b) penetrating through the dielectric substrate (10b).
該被動元件(30)藉由表面黏著技術將其黏著於第一表面金屬層(11b)之表面,用於串聯或並聯之電性連接,該被動元件(30)係採用電阻、電容或電感或其中任兩者之組合,具有低成本取得、標準化規格的優點。The passive component (30) is adhered to the surface of the first surface metal layer (11b) by surface adhesion technology for electrical connection in series or in parallel. The passive component (30) is made of a resistor, a capacitor or an inductor or The combination of the two has the advantages of low cost acquisition and standardized specifications.
該晶片(60)係設置於第一表面金屬層(11b)的上表面,並具有複數個晶片接點(62),而於一實施例中,該晶片(60)採用銀膠或表面黏著技術使其黏貼於第一表面金屬層(11b)的上表面。The wafer (60) is disposed on the upper surface of the first surface metal layer (11b) and has a plurality of wafer contacts (62). In one embodiment, the wafer (60) is formed by silver paste or surface adhesion technology. It is adhered to the upper surface of the first surface metal layer (11b).
該金屬接線(61)採用金線或鋁線之材料,該金屬接線(61)係連線搭接於晶片接點(62)與第一表面金屬層(11b)之焊墊表面,採用打線接合製程將晶片接點(62)與介電基板(10b)的第一表面金屬層(11b)焊墊進行銲接而使彼此電性連接。The metal wiring (61) is made of a gold wire or an aluminum wire, and the metal wire (61) is connected to the surface of the pad of the wafer contact (62) and the first surface metal layer (11b) by wire bonding. The process solders the wafer contacts (62) to the first surface metal layer (11b) pads of the dielectric substrate (10b) to electrically connect each other.
該封裝膠板(20b)係覆蓋於該介電基板(10b)之上表面,用以包覆密封該第一表面金屬層(11b)及其表面黏著之複數個被動元件(30)、金屬接線(61)與晶片(60),該封裝膠板(20b)係採用介電樹脂與陶瓷材料所構成之熱固性複合材料;該封裝膠板(20b)係以真空熱壓合製程加熱與加壓,使其軟化並均勻地流動於介電基板(10b)之上表面,當封裝膠板(20b)持續地吸收能量後會產生聚合反應,而能均勻地黏合固化封裝該介電基板(10b)上表面的第一表面金屬層(11b)、被動元件(30)、晶片(60)及金屬接線(61),且藉由真空熱壓合製程能達到受熱均勻、受壓均勻、穩定流動,降低溫差所造成各材質熱膨脹效應而產生整體封裝翹曲變形的現象。藉由封裝膠板(20b)的保護,可避免物理性質的破壞和化學性質的侵蝕,確保訊號與能量的傳遞,使其發揮功能。The encapsulating sheet (20b) covers the upper surface of the dielectric substrate (10b) for covering and sealing the first surface metal layer (11b) and a plurality of passive components (30) and metal wiring adhered on the surface thereof. (61) and a wafer (60), the encapsulant sheet (20b) is a thermosetting composite material composed of a dielectric resin and a ceramic material; the encapsulant sheet (20b) is heated and pressurized by a vacuum thermocompression bonding process. Softening and uniformly flowing on the upper surface of the dielectric substrate (10b), and when the encapsulating rubber sheet (20b) continuously absorbs energy, a polymerization reaction occurs, and the dielectric substrate (10b) can be uniformly bonded and cured. The first surface metal layer (11b) of the surface, the passive component (30), the wafer (60) and the metal wiring (61), and by the vacuum thermocompression bonding process, uniform heating, uniform pressure, stable flow, and reduced temperature difference can be achieved. The phenomenon of thermal expansion of each material causes warpage of the entire package. By protecting the encapsulating sheet (20b), physical properties and chemical attack can be avoided, and signal and energy transmission can be ensured to function.
該錫球(63)係設置於第二表面金屬層(12b)之下表面,藉由植球陣列技術將錫球(63)陣列銲接成形於第二表面金屬層(12b)之焊墊表面,作為介電基板(10b)與外界裝置電性連接之介面。The solder ball (63) is disposed on the lower surface of the second surface metal layer (12b), and the solder ball array (63) is soldered to the surface of the solder pad of the second surface metal layer (12b) by a ball placement array technique. As an interface between the dielectric substrate (10b) and the external device.
上述整合表面黏著型元件之封裝結構(400)進一步於封裝膠板(20b)上方設置一散熱金屬層(16),並由部份鍍通孔道(13b)貫通於該介電基板(10b)及封裝膠板(20b)內部,使該第一表面金屬層(11b)、第二表面金屬層(12b)與散熱金屬層(16)電性連接,其中該散熱金屬層(16)用以將晶片(60)運作時產生的熱量傳輸至該散熱金屬層(16),幫助晶片(60)快速散熱。The package structure (400) for integrating the surface-adhesive component further includes a heat dissipation metal layer (16) disposed over the package rubber plate (20b), and a portion of the plated through hole (13b) penetrates the dielectric substrate (10b) and The first surface metal layer (11b) and the second surface metal layer (12b) are electrically connected to the heat dissipation metal layer (16), wherein the heat dissipation metal layer (16) is used to transfer the wafer. (60) The heat generated during operation is transferred to the heat dissipation metal layer (16) to help the wafer (60) to dissipate heat rapidly.
請配合參閱第7圖及第8圖,係本發明之第三較佳實例,該整合表面黏著型元件之封裝結構(500),其包括有:一介電基板(10c)、一第一表面金屬層(11c)、一第二表面金屬層(12c)、複數個鍍通孔道(13c)、電子組件(35)、一封裝膠板(20)。Referring to FIG. 7 and FIG. 8 , a third preferred embodiment of the present invention, the integrated surface mount component package structure (500) includes: a dielectric substrate (10c), a first surface a metal layer (11c), a second surface metal layer (12c), a plurality of plated through holes (13c), an electronic component (35), and an encapsulating plate (20).
該介電基板(10c)係採用介電樹脂與玻璃纖維所構成之複合材料或介電樹脂與陶瓷板材或陶瓷粉末所構成的複合材料,該介電基板(10c)的介電常數介於2至50之間。The dielectric substrate (10c) is a composite material composed of a dielectric resin and a glass fiber or a composite material of a dielectric resin and a ceramic plate or a ceramic powder. The dielectric substrate (10c) has a dielectric constant of 2 Between 50.
該第一與第二表面金屬層(11c)(12c)之線路係採用曝光、顯影與蝕刻銅箔、電鍍、噴塗、印刷、網印燒結或其組合方式將線路建構在介電基板(10c)的表面;該第一表面金屬層(11c)係設置於該介電基板(10c)之上表面;該第二表面金屬層(12c)係設置於該介電基板(10c)之下表面。The lines of the first and second surface metal layers (11c) (12c) are formed on the dielectric substrate (10c) by exposure, development and etching of copper foil, electroplating, spraying, printing, screen printing sintering or a combination thereof. The first surface metal layer (11c) is disposed on the upper surface of the dielectric substrate (10c); the second surface metal layer (12c) is disposed on the lower surface of the dielectric substrate (10c).
該等鍍通孔道(13c)貫通於該介電基板(10c)內部與該第一表面金屬層(11c)及第二表面金屬層(12c)連接,讓該第一表面金屬層(11c)及第二表面金屬層(12c)可藉由貫穿介電基板(10c)的鍍通孔道(13c)彼此電性連接。The plated through holes (13c) are connected to the first surface metal layer (11c) and the second surface metal layer (12c) through the dielectric substrate (10c) to allow the first surface metal layer (11c) and The second surface metal layer (12c) may be electrically connected to each other by a plated through hole (13c) penetrating through the dielectric substrate (10c).
該電子組件(35)藉由表面黏著技術將其黏著於第一表面金屬層(11c)之表面彼此電性連接,而於一實施例中,該電子組件(35)可以為複數個電子元件、主被動元件、射頻模組、積體電路晶片組、晶片天線或其他表面黏著型元件之組合。The electronic component (35) is electrically connected to the surface of the first surface metal layer (11c) by surface adhesion technology. In an embodiment, the electronic component (35) may be a plurality of electronic components, A combination of active and passive components, RF modules, integrated circuit chipsets, wafer antennas, or other surface-adhesive components.
該封裝膠板(20c)係覆蓋於該介電基板(10c)之上表面,用以包覆密封該第一表面金屬層(11c)及其表面黏著之電子組件(35),該封裝膠板(20c)係採用介電樹脂與陶瓷材料所構成之熱固性複合材料;而於一實施例中,該封裝膠板(20c)係以真空熱壓合製程加熱與加壓,使其軟化並均勻地流動於介電基板(10)之上表面,當封裝膠板(20c)持續地吸收能量後會產生聚合反應,而能均勻地黏合固化封裝該介電基板(10c)上表面的第一表面金屬層(11c)、電子組件(35),且藉由真空熱壓合製程能達到受熱均勻、受壓均勻、穩定流動,降低溫差所造成各材質熱膨脹效應而產生整體封裝翹曲變形的現象,並藉由封裝膠板(20c)的保護,可避免物理性質的破壞和化學性質的侵蝕,確保訊號與能量的傳遞,使其發揮功能。The encapsulating sheet (20c) covers the upper surface of the dielectric substrate (10c) for encapsulating the first surface metal layer (11c) and the surface of the electronic component (35) adhered thereto. (20c) is a thermosetting composite material composed of a dielectric resin and a ceramic material; and in one embodiment, the encapsulating rubber sheet (20c) is heated and pressurized by a vacuum thermocompression process to soften and uniformly Flowing on the upper surface of the dielectric substrate (10), when the encapsulating rubber sheet (20c) continuously absorbs energy, a polymerization reaction occurs, and the first surface metal which encapsulates the upper surface of the dielectric substrate (10c) can be uniformly bonded and cured. Layer (11c), electronic component (35), and by the vacuum thermocompression bonding process, the phenomenon of uniform heating, uniform pressure, and stable flow can be achieved, and the thermal expansion effect of each material caused by the temperature difference is reduced to cause warpage deformation of the whole package, and By the protection of the encapsulating sheet (20c), the destruction of physical properties and the erosion of chemical properties can be avoided, and the transmission of signals and energy can be ensured to function.
請配合參閱第9圖,係本發明之第四較佳實例,如圖所示,本發明整合表面黏著型元件之封裝結構(600),其包括有:複數個介電基板(10)、複數個表面金屬層(15)、複數個鍍通孔道(13)、電子組件(35)、複數個封裝膠板(20)。Please refer to FIG. 9 , which is a fourth preferred embodiment of the present invention. As shown in the figure, the package structure ( 600 ) of the integrated surface-adhesive component of the present invention comprises: a plurality of dielectric substrates (10), plural a surface metal layer (15), a plurality of plated through holes (13), an electronic component (35), and a plurality of package rubber plates (20).
該介電基板(10)係採用介電樹脂、玻璃纖維所構成之複合材料或介電樹脂與陶瓷板材或陶瓷粉末所構成的複合材料,該介電基板(10)的介電常數介於2至50之間。The dielectric substrate (10) is a composite material composed of a dielectric resin or a glass fiber or a composite material of a dielectric resin and a ceramic plate or ceramic powder. The dielectric substrate (10) has a dielectric constant of 2 Between 50.
該表面金屬層(15)之線路係採用曝光、顯影與蝕刻銅箔、電鍍、噴塗、印刷、網印燒結或其組合方式將線路建構在介電基板(10)的表面;該表面金屬層(15)係設置於該介電基板(10)之上表面及下表面。The surface metal layer (15) is formed by exposing, developing and etching copper foil, electroplating, spraying, printing, screen printing sintering or a combination thereof to the surface of the dielectric substrate (10); the surface metal layer ( 15) is disposed on the upper surface and the lower surface of the dielectric substrate (10).
該等鍍通孔道(13)貫通於該介電基板(10)及封裝膠板(20)內部,讓該表面金屬層(15)可藉由貫穿介電基板(10)的鍍通孔道(13)彼此電性連接。The plated through holes (13) penetrate through the dielectric substrate (10) and the inside of the encapsulating plate (20), so that the surface metal layer (15) can pass through the plated through holes (13) penetrating the dielectric substrate (10). ) Electrically connected to each other.
該電子組件(35)藉由表面黏著技術將其黏著於表面金屬層(15)之表面彼此電性連接,而於一實施例中,該電子組件(35)可以為複數個電子元件、主被動元件、射頻模組、積體電路晶片組、晶片天線或其他表面黏著型元件之組合。The electronic component (35) is electrically connected to the surface of the surface metal layer (15) by surface adhesion technology. In an embodiment, the electronic component (35) can be a plurality of electronic components, active and passive. A combination of components, RF modules, integrated circuit chipsets, wafer antennas, or other surface-adhesive components.
該封裝膠板(20)係覆蓋於該介電基板(10)之表面,用以包覆密封該表面金屬層(15)與其表面黏著之電子組件(35),該封裝膠板(20)係採用介電樹脂與陶瓷材料所構成的熱固性複合材料;而於一實施例中,該封裝膠板(20)係以真空熱壓合製程加熱與加壓,使其軟化並均勻地流動於介電基板(10)之上表面,當封裝膠板(20)持續地吸收能量後會產生聚合反應,而能均勻地黏合固化封裝該介電基板(10)之表面金屬層(15)、電子組件(35),且藉由真空熱壓合製程能達到受熱均勻、受壓均勻、穩定流動,降低溫差所造成各材質熱膨脹效應而產生整體封裝翹曲變形的現象,並藉由封裝膠板(20)的保護,可避免物理性質的破壞和化學性質的侵蝕,確保訊號與能量的傳遞,使其發揮功能。The encapsulating sheet (20) covers the surface of the dielectric substrate (10) for covering and sealing the electronic component (35) of the surface metal layer (15) adhered to the surface thereof, the encapsulating sheet (20) A thermosetting composite material composed of a dielectric resin and a ceramic material; and in one embodiment, the encapsulating rubber sheet (20) is heated and pressurized by a vacuum thermocompression process to soften and uniformly flow to the dielectric. The upper surface of the substrate (10) generates a polymerization reaction when the encapsulating sheet (20) continuously absorbs energy, and uniformly bonds and cures the surface metal layer (15) and the electronic component of the dielectric substrate (10). 35), and by the vacuum thermocompression bonding process, the phenomenon that the heat is uniform, the pressure is uniform, the flow is stable, the thermal expansion effect of each material caused by the temperature difference is reduced, and the warpage deformation of the whole package is generated, and the rubber sheet is encapsulated (20) The protection can avoid the destruction of physical properties and the erosion of chemical properties, ensuring the transmission of signals and energy to make it function.
此外,該封裝膠板(20)亦可作為多層介電基板(10)間的黏合層,達到多疊層封裝的結構體。In addition, the encapsulating sheet (20) can also be used as an adhesive layer between the multilayer dielectric substrates (10) to achieve a multi-layer package structure.
請配合參閱第10圖,係本發明之第五較佳實例,該整合表面黏著型元件之天線封裝結構(700),其包括有:一介電基板(10d)、一第一表面金屬層(11d)、一第二表面金屬層(12d)、複數個鍍通孔道(13d)、複數個被動元件(30)、一晶片(60)、一封裝膠板(20d)以及一第三表面金屬層(14d)。Referring to FIG. 10, a fifth preferred embodiment of the present invention, the antenna package structure (700) of the integrated surface mount component includes: a dielectric substrate (10d) and a first surface metal layer ( 11d), a second surface metal layer (12d), a plurality of plated through holes (13d), a plurality of passive components (30), a wafer (60), a package rubber plate (20d), and a third surface metal layer (14d).
該介電基板(10d)係採用介電樹脂與玻璃纖維所構成之複合材料或介電樹脂與陶瓷板材或陶瓷粉末所構成的複合材料,該介電基板(10d)的介電常數介於2至50之間。The dielectric substrate (10d) is a composite material composed of a dielectric resin and glass fibers or a composite material of a dielectric resin and a ceramic plate or ceramic powder. The dielectric substrate (10d) has a dielectric constant of 2 Between 50.
該第一表面金屬層(11d)線路係採用曝光、顯影與蝕刻銅箔、電鍍、噴塗、印刷、網印燒結或其組合方式將線路建構在介電基板(10d)的上表面;於圖示一較佳實施例中,該第一表面金屬層(11d)設為一方型迴旋狀的線路圖案,並於中央位置設為一特定的線路圖案。The first surface metal layer (11d) circuit is formed on the upper surface of the dielectric substrate (10d) by exposure, development and etching of copper foil, electroplating, spraying, printing, screen printing sintering or a combination thereof; In a preferred embodiment, the first surface metal layer (11d) is a one-side convoluted line pattern and is set to a specific line pattern at a central position.
該第二表面金屬層(12d)線路同樣係採用曝光、顯影與蝕刻銅箔、電鍍、噴塗、印刷、網印燒結或其組合方式將線路建構在介電基板(10d)的下表面。The second surface metal layer (12d) line is also formed on the lower surface of the dielectric substrate (10d) by exposure, development and etching of copper foil, electroplating, spraying, printing, screen printing, or a combination thereof.
該等鍍通孔道(13d)部分貫通於該介電基板(10d)內部,與該第一表面金屬層(11d)及第二表面金屬層(12d)連接,讓該第一表面金屬層(11d)及第二表面金屬層(12d)可藉由貫穿介電基板(10d)的鍍通孔道(13d)彼此電性連接,而該等鍍通孔道(13d)另一部分貫通於該介電基板(10d)及封裝膠板(20d)內部,與第一、第二及第三表面金屬層(11d)(12d)(14d)連接,讓該第一與第二及第三表面金屬層(11d)(12d)(14d)可藉由貫穿介電基板(10d)及封裝膠板(20d)的鍍通孔道(13d)彼此電性連接。於圖示一較佳實施例,該鍍通孔道(13d)於中央位置貫通於該介電基板(10d)內部,以及該鍍通孔道(13d)於側邊位貫通於該介電基板(10d)及封裝膠板(20d)內部。The plated through holes (13d) partially penetrate the inside of the dielectric substrate (10d), and are connected to the first surface metal layer (11d) and the second surface metal layer (12d) to allow the first surface metal layer (11d) And the second surface metal layer (12d) may be electrically connected to each other through a plated through hole (13d) penetrating through the dielectric substrate (10d), and another portion of the plated through holes (13d) penetrates through the dielectric substrate ( 10d) and inside the encapsulating sheet (20d), connected to the first, second and third surface metal layers (11d) (12d) (14d), the first and second and third surface metal layers (11d) (12d) (14d) can be electrically connected to each other by a plated through hole (13d) penetrating through the dielectric substrate (10d) and the encapsulating plate (20d). In the preferred embodiment, the plated through hole (13d) penetrates the inside of the dielectric substrate (10d) at a central position, and the plated through hole (13d) penetrates the dielectric substrate (10d) at a side position. ) and the inside of the encapsulation board (20d).
該被動元件(30)藉由表面黏著技術將其黏著於第一表面金屬層(11d)之表面,用於串聯或並聯之電性連接,該被動元件(30)係採用電阻、電容或電感或其中任兩者之組合,具有低成本取得、標準化規格的優點。The passive component (30) is adhered to the surface of the first surface metal layer (11d) by a surface adhesion technique for electrical connection in series or in parallel. The passive component (30) is made of a resistor, a capacitor or an inductor or The combination of the two has the advantages of low cost acquisition and standardized specifications.
該晶片(60)係設置於介電基板(10d)上表面與第一表面金屬層(11d)電性連接;於一較佳實施例中,該晶片(60)係採用銀膠或表面黏著技術使其黏貼於該介電基板(10d)的中央位置。The wafer (60) is electrically connected to the first surface metal layer (11d) on the upper surface of the dielectric substrate (10d); in a preferred embodiment, the wafer (60) is made of silver paste or surface adhesion technology. It is adhered to the central position of the dielectric substrate (10d).
該封裝膠板(20d)係覆蓋於該介電基板(10d)之上表面,用以包覆密封該第一表面金屬層(11d)及其表面黏著之複數個被動元件(30)與晶片(60),該封裝膠板(20d)係採用介電樹脂與陶瓷材料所構成之熱固性複合材料,並以真空熱壓合製程加熱、加壓使其軟化並均勻地流動於介電基板(10d)之上表面,當封裝膠板(20d)持續地吸收能量後會產生聚合反應,而能均勻地黏合固化封裝該介電基板(10d)上表面的第一表面金屬層(11d)、被動元件(30)及晶片(60),且藉由真空熱壓合製程能達到受熱均勻、受壓均勻、穩定流動,降低溫差所造成各材質熱膨脹效應而產生整體封裝翹曲變形的現象。藉由封裝膠板(20d)的保護,可避免物理性質的破壞和化學性質的侵蝕,確保訊號與能量的傳遞,使其發揮功能。The encapsulating sheet (20d) covers the upper surface of the dielectric substrate (10d) for covering and sealing the first surface metal layer (11d) and a plurality of passive components (30) and wafers on the surface thereof ( 60) The encapsulant sheet (20d) is a thermosetting composite material composed of a dielectric resin and a ceramic material, and is heated and pressurized by a vacuum thermocompression process to soften and uniformly flow on the dielectric substrate (10d). The upper surface, when the encapsulating rubber sheet (20d) continuously absorbs energy, generates a polymerization reaction, and uniformly bonds and cures the first surface metal layer (11d) and the passive component of the upper surface of the dielectric substrate (10d). 30) and the wafer (60), and by the vacuum thermocompression bonding process, the phenomenon that the heat is uniform, the pressure is uniform, and the flow is stable, and the thermal expansion effect of each material caused by the temperature difference is reduced to cause warpage deformation of the whole package. By the protection of the encapsulating sheet (20d), the destruction of physical properties and the erosion of chemical properties can be avoided, and the transmission of signals and energy can be ensured to function.
該第三表面金屬層(14d)設置於該封裝膠板(20d)上表面,作為與外界裝置電性連接的介面,於圖示一較佳實施例中,該第三表面金屬層(14d)係採用曝光、顯影與蝕刻銅箔、電鍍、噴塗、印刷、網印燒結或其組合方式建構於該封裝膠板(20d)上表面形成一預定的線路圖案,並於該鍍通孔道(13d)位置與外界裝置電性連接;於一較佳實施例中,該鍍通孔道(13d)電性連接一導線(圖未示),藉以增加天線輻射效果。The third surface metal layer (14d) is disposed on the upper surface of the encapsulating board (20d) as an interface electrically connected to the external device. In a preferred embodiment, the third surface metal layer (14d) The surface of the encapsulating rubber sheet (20d) is formed by exposure, development and etching of copper foil, electroplating, spraying, printing, screen printing sintering or a combination thereof to form a predetermined line pattern, and the plated through hole (13d) is formed. The position is electrically connected to the external device. In a preferred embodiment, the plated through hole (13d) is electrically connected to a wire (not shown) to increase the radiation effect of the antenna.
綜上所述,本發明整合表面黏著型元件之封裝結構透過晶片、天線線路與被動元件封裝結構模組化,藉由改變被動元件值的大小,得以調整頻率範圍的自由度以及性能,提高天線特性阻抗與系統端阻抗匹配,同時減少佔用印刷電路板面積,以縮小整體的體積,俾增加印刷電路板之利用空間,並改善結構封膠與介電基板之結合強度,提供承載與結構保護的功能,避免物理性質的破壞和化學性質的侵蝕,此外,將不同的晶片或已封裝完成的疊層晶片或其他電子組件整合於同一封裝模組內成為複合式的封裝體,確保訊號與能量的傳遞。In summary, the package structure of the integrated surface-adhesive component of the present invention is modularized by the wafer, the antenna line and the passive component package structure, and the degree of freedom and performance of the frequency range can be adjusted by changing the value of the passive component to improve the antenna. The characteristic impedance is matched with the impedance of the system end, and the area occupied by the printed circuit board is reduced, so as to reduce the overall volume, increase the utilization space of the printed circuit board, and improve the bonding strength between the structural sealant and the dielectric substrate, and provide bearing and structure protection. Function to avoid physical damage and chemical attack. In addition, different wafers or packaged laminated wafers or other electronic components are integrated into the same package to form a composite package to ensure signal and energy. transfer.
以上所舉實施例僅用於方便說明本發明並非加以限制,在不離本發明精神範疇,熟悉此一行業技藝人士所可作之各種簡易變形與修飾,均仍應含括於以下申請專利範圍中。The above-mentioned embodiments are only intended to facilitate the description of the present invention and are not intended to be limiting, and various modifications and modifications may be made without departing from the spirit of the invention. .
(10)(10a)(10b)(10c)(10d)‧‧‧介電基板(10) (10a) (10b) (10c) (10d) ‧ ‧ dielectric substrate
(11)(11a)(11b)(11c)(11d)‧‧‧第一表面金屬層(11) (11a) (11b) (11c) (11d) ‧ ‧ first surface metal layer
(12)(12a)(12b)(12c)(12d)‧‧‧第二表面金屬層(12) (12a) (12b) (12c) (12d) ‧ ‧ second surface metal layer
(13)(13a)(13b)(13c)(13d)‧‧‧鍍通孔道(13) (13a) (13b) (13c) (13d) ‧ ‧ plated through holes
(14d)‧‧‧第三表面金屬層(14d) ‧‧‧ third surface metal layer
(15)‧‧‧表面金屬層(15) ‧‧‧Surface metal layer
(16)‧‧‧散熱金屬層(16) ‧‧‧thermal metal layer
(30)‧‧‧被動元件(30)‧‧‧ Passive components
(35)‧‧‧電子組件(35)‧‧‧Electronic components
(20)(20a)(20b)(20c)(20d)‧‧‧封裝膠板(20)(20a)(20b)(20c)(20d)‧‧‧Package board
(40)‧‧‧習知天線(40) ‧‧‧General antenna
(41)‧‧‧整合電子元件之封裝天線(41)‧‧‧Encapsulated antennas incorporating electronic components
(50)(51)‧‧‧電路基板(50) (51) ‧‧‧ circuit board
(60)‧‧‧晶片(60) ‧‧‧ wafer
(61)‧‧‧金屬接線(61)‧‧‧Metal wiring
(62)‧‧‧晶片接點(62) ‧‧‧Wit contacts
(63)‧‧‧錫球(63)‧‧‧ solder balls
(100)(400)(500)(600)(700)‧‧‧封裝結構(100) (400) (500) (600) (700) ‧ ‧ package structure
(200)(300)‧‧‧印刷電路板(200) (300)‧‧‧ Printed circuit boards
第1圖係為本發明第一較佳實施例的組合示意圖;Figure 1 is a schematic view showing the combination of the first preferred embodiment of the present invention;
第2圖係為本發明第一較佳實施例的側面剖視圖;Figure 2 is a side cross-sectional view showing a first preferred embodiment of the present invention;
第3圖係為習知印刷電路板的天線電路佈線示意圖;Figure 3 is a schematic diagram showing the wiring of an antenna circuit of a conventional printed circuit board;
第4圖係為本發明的天線電路佈線示意圖;Figure 4 is a schematic diagram of the wiring of the antenna circuit of the present invention;
第5圖係為本發明第二較佳實施例的組合示意圖;第6圖係為本發明第二較佳實施例的側面剖視圖;第7圖係為本發明第三較佳實施例的組合示意圖;第8圖係為本發明第三較佳實施例的側面剖視圖;第9圖係為本發明第四較佳實施例多層疊構的剖視圖;以及第10圖係為本發明第五較佳實施例的組合示意圖。5 is a schematic cross-sectional view showing a second preferred embodiment of the present invention; FIG. 6 is a side cross-sectional view showing a second preferred embodiment of the present invention; and FIG. 7 is a schematic view showing a combination of the third preferred embodiment of the present invention. 8 is a side cross-sectional view showing a third preferred embodiment of the present invention; FIG. 9 is a cross-sectional view showing a multi-layer structure of a fourth preferred embodiment of the present invention; and FIG. 10 is a fifth preferred embodiment of the present invention. A schematic diagram of the combination of the examples.
(10c)...介電基板(10c). . . Dielectric substrate
(11c)...第一表面金屬層(11c). . . First surface metal layer
(12c)...第二表面金屬層(12c). . . Second surface metal layer
(13c)...鍍通孔道(13c). . . Plated through hole
(20c)...封裝膠板(20c). . . Package rubber sheet
(35)...電子組件(35). . . Electronic component
(500)...封裝結構(500). . . Package structure
Claims (23)
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TW098117698A TWI402015B (en) | 2009-05-27 | 2009-05-27 | Integration of surface mount components of the packaging structure |
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KR101776322B1 (en) * | 2011-09-02 | 2017-09-07 | 엘지이노텍 주식회사 | Method of manufacturing chip package member |
TWI557983B (en) | 2014-04-16 | 2016-11-11 | Nat Inst Chung Shan Science & Technology | Non - planar Antenna Embedded Packaging Structure and Its Making Method |
US11502402B2 (en) | 2019-03-15 | 2022-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated patch antenna having insulating substrate with antenna cavity and high-K dielectric |
DE102020100778A1 (en) * | 2019-03-15 | 2020-09-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | INTEGRATED PATCH ANTENNA WITH INSULATING SUBSTRATE WITH ANTENNA CAVITY AND HIGH-K DIELECTRIC |
CN112636011A (en) * | 2019-10-08 | 2021-04-09 | 川升股份有限公司 | Radio frequency assembly combination and antenna device |
CN113725100A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
TWI772170B (en) * | 2021-09-06 | 2022-07-21 | 先豐通訊股份有限公司 | Circuit board with embedded chips and manufacturing method |
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