TWI399723B - Display apparatus, driving method for display apparatus and electronic apparatus - Google Patents

Description

Display device, display device driving method and electronic device

The present invention relates to an active matrix type display device in which a light emitting element is used in a pixel; and a driving method for a display device of the type described. The invention also relates to an electronic device comprising a display device of the type described.

Cross-references for related applications

The content of the present invention is related to Japanese Patent Application No. JP 2007-304616, filed on Nov. 26, 2007, to

In recent years, development of a planar self-luminous type display device using an organic EL (electroluminescence) device as a light-emitting element has been actively pursued. The organic EL device utilizes a phenomenon that if an electric field is applied to an organic film, the organic film emits light. Since the organic EL device is driven by an applied voltage of less than 10 V, its power consumption is low. Furthermore, since the organic EL device is a self-luminous device that emits light by itself, it does not require any illumination member and can be formed as a device for reducing weight and reducing thickness. Furthermore, since the response speed of the organic EL device is substantially several microseconds (μs) and extremely high, residual images do not appear after displaying a moving image.

In a planar self-luminous type display device in which an organic EL device is used in a pixel, an active matrix type display device in which a thin film electrocrystal system is formed as an active element in an integrated relationship in a pixel has been actively developed. For example, Japanese Patent Laid-Open Publication No. 2003-255856 (hereinafter referred to as Patent Document 1), No. 2003-271095 (hereinafter referred to as Patent Document 2), and No. 2004-133240 (hereinafter referred to as Patent Document 3), No. 2004-029791 (hereinafter referred to as Patent Document 4), No. 2004-093682 (hereinafter referred to as Patent Document 5), and No. 2006-215213 (hereinafter referred to as Patent Document 6), discloses an active matrix type plane self Light emitting display device.

Fig. 23 is a view schematically showing an example of a conventional active matrix display device. Referring to Figure 23, the display device shown includes a pixel array section 1 and a plurality of peripheral drive sections. The drive sections include a horizontal selector 3 and a write scanner 4. The pixel array section 1 includes a plurality of signal lines SL extending in the row direction and a plurality of scanning lines WS extending in the column direction. One pixel 2 is arranged where each of the signal lines SL and each of the scanning lines WS cross each other. For the sake of easy understanding, FIG. 23 shows only one pixel 2. The write scanner 4 includes a shift register that operates in response to a clock signal ck supplied from the outside to successively transmit a start pulse sp that is also supplied from the outside to one of the outputs to output a sequential A control signal is applied to the scan line WS. The horizontal selector 3 synchronizes the line sequential scanning on the side of the write scanner 4 to supply an image signal to the signal line SL.

The pixel 2 includes a sampling transistor T1, a driving transistor T2, a storage capacitor C1, and a light emitting element EL (electroluminescence). The driving transistor T2 is driven by a P channel type, and is connected to a power supply line at its source (which is one of the current terminals) and to the light emitting element EL at its drain (which is another current terminal). . The driving transistor T2 is connected to the signal line SL through the sampling transistor T1 at its gate (for its control terminal). The sampling transistor T1 conducts in response to a control signal supplied from the write scanner 4 to one of the control signals, and samples and writes an image signal supplied from the signal line SL to the storage capacitor C1. The driving transistor T2 receives the image signal written to the storage capacitor C1 at its gate as a gate voltage Vgs, and supplies a drain current Ids to the light emitting element EL. As a result, the brightness of the light emitted by the light-emitting element EL corresponds to the image signal. The gate voltage Vgs represents a potential of the gate (reference source).

The driving transistor T2 operates in a saturation region, and the relationship between the gate voltage Vgs and the drain current Ids is represented by the following characteristic expression:

Ids=(1/2)μ(W/L)Cox(Vgs-Vth) ²

Where μ is the mobility of the driving transistor, W is the channel width of the driving transistor, L is the channel length of the driving transistor, Cox is the gate insulating layer capacitance per unit area of the driving transistor, and the Vth system The threshold voltage of the driving transistor. As is clear from this characteristic expression, when the driving transistor T2 operates in a saturation region, it acts as a constant current source that supplies the gate current Ids in response to the gate voltage Vgs.

Fig. 24 illustrates a voltage/current characteristic of the light-emitting element EL. In Fig. 24, the abscissa axis represents the anode voltage V, and the ordinate axis represents the drain current Ids. It is to be noted that the anode voltage of the light-emitting element EL is the gate voltage of the driving transistor T2. The voltage/current characteristics of the light-emitting element EL change with time such that its characteristic curve tends to become less steep as time elapses. Therefore, even if the drain current Ids is fixed, the anode voltage or the drain voltage V changes. In this regard, since the driving transistor T2 in the pixel 2 shown in FIG. 23 is operated in a saturation region, and the gate current Ids corresponding to the gate voltage Vgs can be supplied regardless of the variation of the gate voltage, Therefore, the luminance of the light can be kept constant regardless of the temporal change of the characteristics of the light-emitting element EL.

Figure 25 shows another range of an existing pixel circuit. Referring to FIG. 25, the pixel circuit shown is different from that described above with reference to FIG. 23, in which the driving transistor T2 is not a P-channel type driving transistor but an N-channel type. Starting with the process of a circuit, it often helps to form all of the transistors that make up the pixels from the N-channel transistor.

However, in the circuit configuration of FIG. 25, since the driving transistor T2 is of the N-channel type, it is connected to a power supply line at its drain and to the anode of the light-emitting element EL at its source S. . Therefore, when the characteristic of the light-emitting element EL changes with time, since the potential of the source S of the driving transistor T2 exerts an influence, the gate voltage Vgs changes and the drain current supplied from the driving transistor T2 changes. Ids will change over time. Therefore, the luminance of the light-emitting element EL also changes as time elapses. Further, not only the luminance of the light-emitting element EL but also the threshold voltage Vth and the mobility μ of the driving transistor T2 are scattered in each pixel. Since the threshold voltage Vth and the mobility μ are included in the above-described given transistor characteristic expression, the gate current Ids changes even if the gate voltage Vgs is fixed. As a result, the luminance of the light is spread over each pixel, and the consistency of the screen image cannot be obtained. A display device having a function of correcting the threshold voltage Vth of the driving transistor T2 spread over each pixel (i.e., a threshold voltage correcting function) has been proposed and disclosed, for example, in the above-mentioned Patent Document 3. Likewise, it has been proposed and disclosed, for example, in the above-mentioned Patent Document 6, to disclose a display including the function of correcting the mobility μ of the driving transistor T2 to be dispersed in each pixel (i.e., including a threshold voltage correction function). Device.

The existing display device including the mobility correction function performs mobility correction in accordance with the period in which the sampling transistor T1 is turned on to sample and write an image signal to the storage capacitor C1 (i.e., a sampling period or a writing period). Specifically, during the sampling period, the driving current flowing through the driving transistor T2 is negatively fed back to the storage capacitor C1 in response to the image signal, thereby applying the mobility μ of the driving transistor T1. Corrected to the signal potential of the image signal written in the storage capacitor C1. Accordingly, the sampling period just becomes a mobility correction period.

The signal potential of the image signal changes in response to a hierarchical order from black to white. Meanwhile, in the conventional display device, the sampling period of the image signal, that is, the mobility correction period is fixed irrespective of the hierarchical level of the image signal. However, it is known that the optimal mobility correction period does not need to be fixed, but depends on the hierarchical level of the image signal. As a general trend, the optimum mobility correction period is short when the luminance exhibits a white level, but the optimum mobility correction period is long when the luminance exhibits a black level. However, the conventional display device does not include a countermeasure against this point, and accurate and complete mobility correction cannot be performed, and thus it is necessary to solve the problem that the screen image is not always highly consistent.

According to an embodiment of the present invention, a display device includes a pixel array section and a driving section, the pixel array section including a plurality of scanning lines extending along a column direction and extending along a row direction A plurality of signal lines and a plurality of pixels are arranged in columns and rows where the signal lines and the scan lines intersect each other. Each of the pixels includes a sampling transistor, a driving transistor, a storage capacitor, and a light emitting component. The sampling transistor is connected to one of the scan lines at a control terminal thereof, and A pair of current terminals are connected to one of the signal lines and a control terminal of the driving transistor. The driving transistor is connected to the light emitting element at a first current terminal of a pair of current terminals thereof, and is connected to a power supply at a second current terminal of the current terminal thereof; the storage capacitor is connected to the driving power a control terminal of the crystal, the driving section includes a write scanner and a signal selector, the write scanner supplies a sequential control signal to the scan line during each horizontal period, and the signal selector supplies the image signal to the signal line One of the signal potential and a reference potential is changed during each horizontal period. When one of the signal lines associated with the signal line has the reference potential, the sampling cell system is placed in an on state in response to a control signal supplied to one of the scan lines associated with the scan line to perform the driving A threshold voltage correction operation for the spread of the annihilation voltage of the crystal. The sampling transistor performs a signal writing operation to the storage capacitor during a writing period, the writing period is a first timing from the reference potential to the potential of the signal line from the reference potential And a second timing in which the sampling transistor system is placed in a closed state in response to the control signal; the driving transistor supplies a driving current to the light emitting element according to a signal potential written in the storage capacitor to perform a light emission operating. The signal selector variably adjusts the first timing in response to the signal potential, thereby variably controlling a write period from the first timing to the second timing in response to the signal potential.

In particular, the display device can be configured such that when the signal potential has a white level, the signal selector shifts the first timing toward the second timing to shorten the writing period; When the signal potential has a black level, the signal selector shifts the first timing away from the second timing to lengthen the writing period. In this case, the display device can be configured such that the storage capacitor is coupled between the control terminal and one of the current terminals of the drive transistor; and the drive transistor is negatively biased during the write cycle Retrieving a driving current flowing therebetween to the storage capacitor to perform a correcting operation for mobility dispersion of the driving transistor; and the signal selector variably adjusting the writing period in response to the signal potential to Jiahua should give back the negative feedback.

In the display device, writing from a first timing (the potential of the signal lines is changed from a reference potential to a signal potential) to a second timing (the sampling transistor system is placed in a closed state in response to the control signal) During the input period, the signal potential is written into the storage capacitor. Thus, the signal selector variably controls the first timing in response to the signal potential, thereby variably controlling the write period from the first timing to the second timing. During this write cycle, the drive current flowing through the drive transistor is negatively fed back to the storage capacitor to perform a correction for the mobility spread of the drive transistor. Therefore, the write period from the first timing to the second timing is taken as the mobility correction period. In this embodiment, the write cycle, i.e., the mobility correction period, is adaptively adjusted in response to the signal potential. As a result, optimal control of the mobility correction period based on the level or level of the signal potential can be achieved, and the consistency of the screen image can be enhanced.

Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Figure 1 shows the general configuration of a display device in accordance with this particular embodiment. The display device shown is formed from a panel in which a pixel array section 1 and drive sections (3, 4 and 5) for driving the pixel array section 1 are formed on the same substrate. The pixel array section 1 includes a plurality of scan lines WS extending along a column direction; a plurality of signal lines SL extending along a row direction; and a plurality of pixels 2 arranged in columns and rows on the scan lines WS and Where the signal lines SL cross each other; and a plurality of feed lines DS as power supply lines, which are arranged corresponding to the columns of the pixels 2. The driving sections 3, 4 and 5 comprise a control scanner (write scanner) 4 for sequentially supplying a control signal to the scan lines WS for sequentially scanning pixels 2 in units of columns. a power supply scanner (drive scanner) 5 for responding to the line sequential scanning, supplying a power supply potential converted between the first potential and a second potential to each of the feed lines DS; and a signal The driver (horizontal selector) 3 is configured to supply a signal potential as a video signal and a reference potential to the signal line SL in the rows in response to the line sequential scanning. It should be noted that the control scanner or the write scanner 4 operates in response to one of the clock signals WSck supplied from the outside to successively transmit one of the start pulses WSsp also supplied from the outside to output a control signal to the Wait for the scan line WS. The power supply scanner or drive scanner 5 operates in response to one of the clock signals DSck supplied from the outside to successively transmit one of the start pulses DSsp also supplied from the outside to sequentially change the potential of the feed lines DS in a line. .

Figure 2 shows a specific configuration of one of the pixels 2 included in the display device shown in Figure 1. Referring to FIG. 2, each of the pixels 2 includes a light-emitting element EL of a two-terminal type or a diode type represented by an organic EL device, a sampling transistor T1 of an N-channel type, and a driving transistor T2 of an N-channel type. A storage capacitor C1 of the film type. The sampling transistor T1 is connected to a scan line WS at its gate (as a control terminal), and is connected to the gate G of the driving transistor T2 at one of its source and drain (as a current terminal). And connected to a signal line SL at the other of its source and drain. The driving transistor T2 is connected to the light emitting element EL at one of the source and the drain, and is connected to a feed line DS at the other of its source and drain. In the present embodiment, the driving transistor T2 is of the N-channel type and is connected to the feed line DS at its drain side (one of the current terminals) and to its source S side (another current) The terminal) is connected to the anode side of the light-emitting element EL. The light-emitting element EL is connected at its cathode and fixed to a predetermined cathode potential Vcat. The storage capacitor C1 is connected between the source S (as a current terminal) and the gate G (as a control terminal) of the drive transistor T2. The control scanner or the write scanner 4 converts the potential of the scan line WS between a low potential and a high potential to output a sequential control signal to the pixels 2 having the above configuration, thereby sequentially scanning the lines. The pixels 2 in units of one column. The power supply scanner or drive scanner 5 supplies a power supply potential to the feed lines DS in response to the line sequential scan, the power supply potential being switched between a first potential Vcc and a second potential Vss. The signal driver or level selector 3 synchronizes the line sequential scanning to supply a signal potential Vsig (which is an image signal) and a reference potential Vofs to the signal lines SL extending in the row direction.

Figure 3 illustrates the operation of the pixel shown in Figure 2. It should be noted that the operation described in FIG. 3 is a reference example, and the operation of the pixel circuit shown in FIG. 2 is not limited to the operation described in FIG. The timing chart of FIG. 3 illustrates the potential change of the scanning lines WS, the potential change of the feed line or the power supply line DS, and the potential change of the signal line SL with respect to the common time axis. The potential change of the scanning line WS represents the control signal, and controls the on and off states of the sampling transistor T1. The potential change of the feed line DS represents a transition between the power supply voltages Vcc and Vss. The potential change of the signal line SL represents a transition between the signal potential Vsig of the input signal or the video signal and the reference potential Vofs. This transformation is performed in each horizontal period of 1H. Similarly to the potential change mentioned, the potential change of the gate G and the source S of the driving transistor T2 is also explained. The potential difference Vgs is a potential difference between the gate G and the source S described above.

For convenience of explanation, the period of the timing chart of FIG. 3 is divided into (1) to (7) periods in accordance with the transition of the operation of the pixels. In the period (1) immediately before the subsidiary field, the light-emitting element EL is in a light-emitting state. Thereafter, a new field of the line scan is entered, and the potential of the feed line DS is changed from the first potential Vcc to the second potential Vss in the first period (2). Next, in the next cycle (3), the input signal is converted from the signal potential Vsig to the reference potential Vofs. Further, in the period (4), the sampling transistor T1 is turned on. In the periods (2) to (4), the gate voltage and the source voltage of the driving transistor T2 are initialized. The periods (2) to (4) are preparatory periods for threshold voltage correction, in which the gate G of the driving transistor T2 is initialized to the reference potential Vofs, and the source S of the driving transistor T2 is initialized to the first Two potential Vss. Then, in the period (5), a threshold voltage correcting operation is actually performed, and a voltage corresponding to one of the threshold voltages Vth is stored between the gate G and the source S of the driving transistor T2. Actually, the voltage corresponding to the threshold voltage Vth is written into the storage capacitor C1 connected between the gate G and the source S of the driving transistor T2.

Note that in the reference example of Fig. 3, the threshold correction period (5) is provided three times, and a waiting period (5a) is inserted next to each threshold correction period (5). A voltage corresponding to the threshold voltage Vth can be written into the storage capacitor C1 by dividing the threshold voltage correction period (5) to repeat the threshold voltage correction operation a plurality of times. Note that the present invention is not limited thereto, and the correction operation can be performed within a threshold voltage correction period (5).

Thereafter, the write operation cycle/mobility correction cycle (6) is entered. Here, the signal potential Vsig of the image signal is written into the storage capacitor C1 in an accumulated manner while subtracting the voltage ΔV for mobility correction from the voltage stored in the storage capacitor C1. In the write operation period/mobility correction period (6), it is necessary to place the sampling transistor T1 in an on state in a time zone in which the signal line SL holds the signal potential Vsig. Thereafter, an illumination period (7) is entered, and a luminance of the light-emitting element that emits light corresponds to the signal potential Vsig. Then, since the signal potential Vsig is adjusted by the voltage corresponding to the threshold voltage Vth and the mobility corrected voltage ΔV, the light-emitting luminance of the light-emitting element EL is not affected by the threshold voltage Vth of the driving transistor T2 or The effect of the spread of mobility μ. Note that a bootstrap operation is performed at the beginning of the lighting period (7) while the gate-source voltage Vgs of the driving transistor T2 is kept constant, and the gate of the driving transistor T2 is raised. Extreme potential and source potential.

The operation of the pixel circuit shown in Fig. 2 will be described in detail with reference to Figs. First, as shown in FIG. 4, in the light-emitting period (1), the power supply potential is set at the first potential Vcc and the sampling transistor T1 is tied to a closed state. At this time, since the driving transistor T2 is set such that it operates in a saturation region, in response to the gate-source voltage Vgs applied between the gate G and the source S of the driving transistor T2, The drive current Ids flowing through the light-emitting element EL is assumed to be a value given by the above-mentioned transistor characteristic expression.

Therefore, after entering the preparation periods (2) and (3), the potential of the feed line or the power supply line DS becomes the second potential Vss as shown in FIG. Since the second potential Vss is set such that the driving transistor T2 is operated in a saturation region at this time, the light emitting element EL is turned off, and the side of the power supply line becomes the source of the driving transistor T2. pole. At this time, the anode of the light-emitting element EL is charged to the second potential Vss.

Then, after entering the next preparation period (4), when the potential of the signal line SL becomes the reference potential Vofs, the sampling transistor T1 is turned on to set the gate potential of the driving transistor T2 to the reference potential Vofs, As shown in Figure 7. In this way, the source S and the gate G of the driving transistor T2 in the light-emitting state are initialized, and the gate-source voltage Vgs becomes a value of Vofs-Vss at this time. The gate-source voltage Vgs=Vofs-Vss is set such that it has a value higher than the threshold voltage Vth of the driving transistor T2. By initializing the drive transistor T2 in this manner such that Vgs > Vth is satisfied, preparation for a subsequent threshold voltage correction operation is completed.

Next, after entering the threshold voltage correction period (5), the potential of the feed line DS returns to the first potential Vcc as shown in FIG. When the power supply voltage becomes the first potential Vcc, the potential of the anode of the light-emitting element EL becomes the potential of the source S of the driving transistor T2, and the current flows as indicated by the dotted arrow mark of FIG. At this time, an equivalent connection of the light-emitting element EL is represented by a parallel connection of a diode Tel and a capacitor Cel. Since the anode potential of the light-emitting element EL, that is, the second potential Vss is lower than Vcat+Vthel, the diode Tel is in a closed state, and the leakage current flowing through the diode Tel is considerably smaller than the driving current. The current of the crystal T2. Therefore, almost all of the current flowing through the driving transistor T2 is used to charge the storage capacitor C1 and the equivalent capacitor Cel.

Figure 8 illustrates the time variation of the source of the drive transistor T2 within the threshold voltage correction period (5) illustrated in Figure 7. Referring to FIG. 8, the source voltage of the driving transistor T2, that is, the anode voltage of the light-emitting element EL rises from the second voltage Vss as time elapses. After the threshold voltage correction period (5) elapses, the driving transistor T2 is turned off, and the gate-source voltage Vgs between the source S and the gate G of the driving transistor T2 becomes equal to the threshold voltage. Vth. At this time, the source potential is given as Vofs-Vth. If the value Vofs-Vth remains below Vcat+Vthel, the light-emitting element EL is in an off state.

As seen in Fig. 8, the source potential of the driving transistor T2 rises as time elapses. However, in this example, before the source voltage of the driving transistor T2 reaches Vofs-Vth, the first threshold voltage correction period (5) ends, and thus the sampling transistor T1 is turned off and enters a waiting period (5a). ). Figure 9 illustrates a state of the pixel circuit in this waiting period (5a). In this first waiting period (5a), since the gate-source voltage Vgs of the driving transistor T2 remains higher than the threshold voltage Vth, current flows from the first potential Vcc through the driving transistor T2. To the storage capacitor C1, as shown in FIG. As a result, although the source voltage of the driving transistor T2 rises, the gate of the driving transistor T2 is closed because the sampling transistor T1 is in a closed state and the gate G of the driving transistor T2 is in a high impedance state. The potential of G also rises as the potential of the source S rises. In other words, in the first waiting period (5a), both the source potential and the gate potential of the driving transistor T2 rise. At this time, since the reverse bias is continuously applied to the light-emitting element EL, the light-emitting element EL does not emit light.

Thereafter, when a horizontal period of 1H elapses and the potential of the signal line SL becomes the reference potential Vofs, the sampling transistor T1 is turned on to start the second threshold voltage correcting operation. Thereafter, when the second threshold voltage correction period (5) elapses, the second waiting period (5a) is entered. By repeating the threshold voltage correction period (5) and the wait period (5a) in this manner, the gate-source voltage Vgs of the driving transistor T2 eventually reaches a voltage corresponding to the threshold voltage Vth. At this time, the source potential of the driving transistor T2 is Vofs-Vth, and is lower than Vcat+Vthel.

Thereafter, when entering the write operation period/mobility correction period (6), the potential of the signal line SL is changed from the reference potential Vofs to the signal potential Vsig, and then the sampling transistor T1 is turned on, as shown in FIG. Show. At this time, the signal potential Vsig has a voltage value according to a level. Since the sampling transistor T1 is turned on, the gate potential of the driving transistor T2 becomes the signal potential Vsig. At the same time, the source potential of the driving transistor T2 rises with time because the current flowing therethrough comes from the first potential Vcc. Also at this time, if the source potential of the driving transistor T2 does not exceed the sum of the threshold voltage Vthel of the light-emitting element EL and the cathode potential Vcat, the current flowing from the driving transistor T2 is only used for charging equivalent. Capacitor Cel and storage capacitor C1. At this time, since the threshold voltage correcting operation of the driving transistor T2 has been completed, the current supplied from the driving transistor T2 reflects the mobility μ. In particular, in the case where the driving transistor T2 has a high mobility μ, the amount of current at this time is large, and the amount of potential increase ΔV of the source is also large. On the other hand, in the case where the driving transistor T2 has a low mobility μ, the amount of current of the driving transistor T2 is small, and the potential increase amount ΔV of the source is also small. By this operation, the gate-source voltage Vgs of the driving transistor T2 is compressed by the potential increase amount ΔV reflecting the mobility μ, and at the time point when the mobility correction period (6) is to be ended, the erasing is completely eliminated. The gate-source voltage Vgs is obtained in the mobility μ.

Fig. 11 illustrates a change in time with respect to the source potential of the driving transistor T2 in the mobility correction period (6) described above. As can be seen from Fig. 11, in the case where the mobility of the driving transistor T2 is high, the source voltage of the driving transistor T2 rises rapidly, and the gate-source voltage Vgs is also compressed to the same extent. In other words, in the case where the mobility μ is high, the gate-source voltage Vgs is compressed so as to cancel the influence of the mobility μ, and the driving current can be suppressed. On the other hand, in the case where the mobility μ is low, the source voltage of the driving transistor T2 does not rise rapidly, and the gate-source voltage Vgs is not as strong as that of the compression. Therefore, in the case where the mobility μ is low, the gate-source voltage Vgs is not compressed so much as to supplement the low driving capacitance.

Figure 12 illustrates an operational state in the illumination period (7). In the light-emitting period (7), the sampling transistor T1 is turned off to cause the light-emitting element EL to emit light. The gate voltage Vgs of the driving transistor T2 is kept constant, and the driving transistor T2 supplies the fixed driving current Ids to the light emitting element EL according to the above-described characteristic expression. Since the driving current Ids' flows through the light emitting element EL, the anode voltage of the light emitting element EL, that is, the source voltage of the driving transistor T2 rises to Vx, and wherein the light is emitted at a time point when the voltage exceeds Vcat+Vthel The element EL emits light. As the lighting time becomes longer, the current/voltage of the light-emitting element EL changes. Therefore, the potential of the source S changes as shown in FIG. However, since the gate-source voltage Vgs of the driving transistor T2 is maintained at a fixed value by the bootstrap operation, the driving current Ids' flowing through the light-emitting element EL does not change. Therefore, even if the current/voltage characteristic of the light-emitting element EL is deteriorated, it is required to cause the fixed drive current Ids' to flow, and the luminance of the light-emitting element EL does not change at all.

Incidentally, the optimal mobility correction period does not need to be fixed, but depends on the brightness level or level of the image signal. In order to eliminate the screen image unevenness caused by the mobility, it is necessary to adaptively control the mobility correction period in response to the hierarchical level. As is the general trend, the optimum mobility correction period is short when white is displayed, but the optimum mobility correction period is long when black is displayed.

Fig. 13 illustrates an adaptive control method for correcting the time or signal writing time according to the mobility of the hierarchical class. Note that FIG. 13 illustrates a reference example. Referring to FIG. 13, the input signal to be supplied to a signal line SL, that is, the image signal is converted between the reference potential Vofs and the signal potential Vsig in a period of 1H. In response to the conversion, a control signal pulse is applied to the scan line WS, and the sampling transistor T1 is placed in an on state twice. First, when the input signal has the reference potential Vofs, the sampling transistor T1 is placed in an on state to perform the threshold correction operation as described above. Next, when the potential of the input signal changes to the signal potential Vsig, the sampling transistor T1 is again placed in an on state to perform a signal writing operation. The period in this signal write operation is exactly performed to become a mobility correction period. In the reference example of FIG. 13, a falling edge of the second control signal pulse is provided to perform the signal writing period, that is, the adaptive control of the mobility correction period. The falling edge waveform of the control signal pulse is an analog waveform and has a large voltage width and therefore cannot be generated inside the panel but can be generated using an externally provided module. A desired falling edge waveform is generated by the module and input to a power supply line of the write scanner in the panel to obtain a control signal pulse having a desired falling edge waveform. However, since this module produces a waveform with high accuracy using high potential, it is complicated and expensive, and requires high power consumption. Therefore, the use of an external module poses a hindrance to the consideration, wherein the display device is applied to the display of a portable device.

Figure 14 illustrates the adaptive control of the mobility correction period in the reference example of Figure 13. As described above, the control signal pulse supplied to the scan line WS has a characteristic falling edge waveform which first exhibits a steep slope and then exhibits a gradual change, and finally exhibits a steeply falling slope. This falling edge waveform is applied to the control terminal of the sampling transistor T1, that is, to the gate of the sampling transistor T1. At the same time, the signal potential Vsig is applied to the source of the sampling transistor T1. Therefore, the gate voltage Vgs that controls the on/off of the sampling transistor T1 depends on the signal potential Vsig applied to the source of the sampling transistor T1.

Where the signal potential in the white display is represented by Vsig white and the threshold voltage of the sampling transistor T1 is represented by VthT1, when the falling edge of the control signal pulse just crosses the Vsig white+ indicated by a chain line When the class of VthT1 is set, the sampling transistor T1 is placed in a closed state. Since the time at which the sampling transistor T1 is placed in a closed state is exactly the time point at which the control signal pulse begins to drop steeply, the sampling transistor T1 is placed in an on state until it is placed in a closed state. The white display signal write cycle becomes shorter. Therefore, the mobility correction period at the time of white display also becomes short.

On the other hand, in the case where the signal potential of the black display is represented by Vsig black, the sampling transistor is when the control signal pulse is lower than Vsig black+VthT1 indicated by a broken line at the portion of its final falling edge. T1 is placed in a closed state. Therefore, the signal writing period at the time of black display becomes long. The adaptive control of the mobility correction period according to the signal potential is performed in this way. Note that in the case of a gray display between the white display and the black display, when the sampling transistor T1 is placed in a closed state, the falling edge waveform just shows a part of the mitigation change, and can be performed here. The fine adjustment of the waveform is corrected according to the mobility of the gray scale. Note that, as mentioned above, this reference example requires an external module to generate a characteristic falling edge waveform and has a problem in mobile applications and the like.

In order to deal with the problem of the reference example as described above, according to a specific embodiment, in response to the hierarchical level of the image signal, the falling edge phase of the image signal is adjusted, that is, the image signal or the input signal is input to the image. The timing of switching from the reference potential to the pixel of the signal potential to perform adaptive control of the optimum mobility correction time. Figure 15A illustrates a drive sequence in accordance with a particular embodiment. Referring to FIG. 15A, the timing chart of FIG. 15A is substantially the same as the timing chart of the reference example of FIG. 3, and the same reference numerals are used for ease of understanding. A control signal is supplied from the write scanner to the scan line WS, and the sampling transistor T1 is placed in an on and off state in response to the control signal. The write scanner supplies sequential control signals to the scan lines WS during each horizontal period (1H). At the same time, an input signal is supplied from the signal selector to each signal line SL. The signal selector supplies an image signal or an input signal to each of the signal lines SL, which exhibits a transition between the signal potential Vsig and the reference potential Vofs in each horizontal period. A power supply potential exhibiting a transition between the low potential Vss and the high potential Vcc is supplied from the power supply scanner to each of the power supply lines DS.

As seen in Fig. 15A, when the power supply line or the feed line DS is at the low potential Vss, each pixel performs a threshold correction preparation operation in a preparation period (4). Then, when the potential of the power supply line DS is changed from the low potential Vss to the high potential Vcc, a threshold correction operation is performed in a correction period (5). In the present embodiment, this threshold correction operation is performed three times in a time division manner.

In the last period of 1H in a non-lighting period, a third threshold voltage correction period (5) and a signal writing period, that is, a mobility correction period (6) are included. After that, it enters a lighting period (7). Here, if attention is paid to the last 1H period in the non-light-emitting period, the sampling transistor is supplied in response to the control signal supplied to the scanning line WS at the timing t0 at which the signal line SL has the reference potential Vofs. The T1 is placed in an on state to perform the third threshold voltage correcting operation for canceling the spread of the threshold voltage Vth of the driving transistor T2. Thereafter, writing from the first timing t1 (the potential of the signal line SL is changed from the reference potential Vofs to the signal potential Vsig) to the second timing (the sampling transistor T1 is placed in a closed state in response to the control signal) In the input period (6), a signal writing operation in which the signal potential Vsig is written to the storage capacitor C1 is performed. Thereafter, in an illumination period (7), the driving transistor T2 supplies a driving signal to the light emitting element EL in accordance with the signal potential written in the storage capacitor C1, so that the light emitting element EL emits light.

Due to the characteristic nature of an embodiment of the present invention, the signal selector or horizontal selector variably adjusts the first timing t1, that is, the transformed phase of the driving signal, in response to the level or level of the signal potential Vsig. The signal writing period (6) from the first timing t1 to the second timing t2 is variably controlled in response to the signal potential Vsig. Specifically, when the signal potential Vsig has a white level, the signal selector shifts the first timing t1 toward the second timing t2 to shorten the writing period (6); but when the signal potential Vsig has In the black level, the signal selector shifts the first timing t1 away from the second timing t2 to lengthen the writing period (6). In the writing period (6), the driving transistor T2 negatively returns the driving current flowing through the writing period (6) to the storage capacitor C1 to perform a correcting operation for the driving. The mobility μ of the transistor T2. The signal selector variably adjusts the write period (6) in response to the level of the signal potential Vsig to optimize the negative feedback amount as described above. Phase adjustment based on the transition time of the signal level or luminance level can be implemented by a relatively simple configuration of the class/phase conversion circuit without the need for a complicated external module.

Fig. 15B illustrates an operational state in which white display is performed. The input signal supplied to the signal line SL is converted from the reference potential Vofs to the signal potential Vsig in one cycle of 1H. The timing of this transformation is represented by t1. The sampling transistor T1 is placed in an on state in response to a control signal pulse applied to the scan line WS. This timing of the sampling transistor T1 placed in an on state is represented by t0. When the input signal is the reference potential Vofs, the sampling transistor T1 exhibits an on state and performs a threshold correction operation. Thereafter, at timing t1, the input signal is switched to the signal potential Vsig, and a write operation of a write signal is entered. At the same time, the mobility correction corresponding to the white signal is started. After the input signal is converted to the signal potential Vsig at the timing t1, the sampling transistor T1 is disposed in a closed state at the timing t2, thereby completing the white signal writing operation. In the sequence of operations as described above, the timing t1 at which the input signal transitions from the reference potential Vofs to the signal potential VSig is relatively shifted toward the drive transistor T2. As a result, the white signal writing time is shortened, and the mobility correction time is optimized according to the white level. In other words, when a white signal is input, the phase of the signal of the input signal is delayed to shorten the signal writing time period.

Fig. 15C illustrates an operational state at the time of writing a black signal. At timing t1, the input signal is converted from the reference potential Vofs to the signal potential Vsig. Since black is displayed, the level of the signal potential Vsig is lower than the level when white is displayed as shown in Fig. 15B. Accordingly, the timing t1 at which the input signal is converted from the reference potential Vofs to the signal potential Vsig is shifted away from the timing t2. In other words, the black signal write period can be extended by moving the phase of the signal of the input signal forward. In this manner, in a specific embodiment of the present invention, the signal writing period is defined by timing t1 (signal rising) and timing t2 (sampling transistor T1 is placed in a closed state), and in response to inputting to the The level of the image signal of the pixel changes the falling edge phase t1 of the signal. As a result, it makes it possible to correct for unevenness due to mobility at all levels, and it is possible to obtain uniform image quality without streaks or unevenness. In addition, according to a specific embodiment of the present invention, since it is excluded that an analog waveform must be input from an external module to a write scanner, power consumption reduction and cost reduction can be achieved.

Fig. 15D shows an output section of the horizontal selector 3, which corresponds to a signal line SL of one line. Although not shown in the figure, the horizontal selector 3 includes, in addition to the output section, a signal processing section for supplying a signal voltage Vsig and a reference potential Vofs to the output section; A shift register for supplying a control signal to the output section in synchronization with a line sequential scan on the write scanner side.

The output section of the horizontal selector 3 is composed of transistors H1 and H2, a resistor R and a capacitor C. The transistor H1 is for outputting a reference potential Vofs, and is connected at its pair of current terminals to a supply line of a reference potential Vofs and a signal line SL. The transistor H2 is for outputting a signal potential Vsig, and is connected to the supply line of the signal potential Vsig and the signal line SL at a pair of current electrodes thereof, and is connected to the shift at a control terminal or point B thereof. A corresponding point or point A of the scratchpad. An RC circuit formed by the resistor R and the capacitor C is interposed between the point A and the point B.

Figure 15E illustrates the operation of the horizontal selector 3 shown in Figure 15D. Referring to FIG. 15E, a rectangular control pulse is applied from the shift register to the control terminal of the transistor H1 in the first half of a horizontal scanning period of 1H. As a result, the transistor H1 is placed in an on state to output the reference potential Vofs to the corresponding signal line SL.

Next, after entering the second half of the horizontal scanning period of 1H, a rectangular control pulse is applied from the shift register to the point A. This control pulse finally passes through the RC circuit to the point B, which is the control terminal of the transistor H2. The rectangular pulse is deformed according to the time constant of the RC circuit, and exhibits a rising edge waveform and a falling edge waveform, as seen in FIG. 15E. Since the pulse waveform is deformed, the rising edge form successively passes through a class (Vsig black+VthH2) obtained by adding the signal potential Vsig black at the time of black display and the threshold voltage VthH2 of the transistor H2, and Another class (Vsig white+VthH2) obtained by adding the signal potential Vsig white at the time of white display and the threshold voltage VthH2 of the transistor H2. Note that at this point in time, the control signal WS has been applied to the scan line WS at the timing t0, and the sampling cell system on the pixel 2 side is in an on state.

In the case of white display, the transistor H2 is placed in an on state when the point B exceeds the timing t1 (white) of the potential of Vsig white + VthH2. Specifically, since the current terminal of the transistor H2 connected to the signal supply line side serves as the source and the point B serves as the gate, when the gate-source voltage exceeds (Vsig white+VthH2)-Vsig white=VthH2 The transistor H2 is placed in an on state. As a result, the signal potential Vsig white for white display is applied from the signal supply line to the signal line SL. Specifically, at the timing t1 (white), the potential of the signal line SL is changed from the reference potential Vofs to the signal potential Vsig white.

In the case of black display, the transistor H2 is placed in an on state when the point B exceeds the timing t1 (black) of the potential of Vsig black + VthH2. Specifically, since the current terminal of the transistor H2 connected to the signal supply line side serves as the source and the point B serves as the gate, when the gate-source voltage exceeds (Vsig black+VthH2)-Vsig black=VthH2 The transistor H2 is placed in an on state. As a result, the signal potential Vsig black for black display is applied from the signal supply line to the signal line SL. Specifically, at the timing t1 (black), the potential of the signal line SL is changed from the reference potential Vofs to the signal potential Vsig black. As is clear from the timing chart, the timing t1 (black) is immediately shifted forward from the timing t1 (white). In other words, the horizontal selector 3 variably controls the first timing t1 in response to the level of the signal potential Vsig.

Thereafter, when entering the second timing t2, the control signal WS is canceled, and the sampling cell system on the pixel 2 side is placed in a closed state. As a result, the sampling of the signal potential Vsig is ended. Therefore, the signal writing time period at the time of white display is from time t1 (White) to time t2, and the signal writing time period at the time of black display is from the timing t1 (black) to the timing t2. In this way, when the signal potential has a white level, the horizontal selector 3 shifts the first timing t1 (white) toward the second timing t2 to shorten the writing time; but when the signal potential has a black level, The horizontal selector 3 shifts the first timing t1 (black) away from the second timing t2 to elongate the write time.

The display device according to the present invention has such a thin film device configuration as shown in FIG. Figure 16 shows a schematic sectional structure in which one pixel is formed on an insulating substrate. As seen in Figure 16, the pixel shown includes a transistor section (illustrated in Figure 16, a TFT) comprising a plurality of thin film transistors; a capacitor section, such as a storage capacitor or the like; and a light emitting section , such as an organic EL element. The transistor section and the capacitor section are formed on a substrate by a TFT process, and the light-emitting section such as an organic EL element is laminated on the transistor section and the capacitor section. A transparent opposing substrate is adhered to the light-emitting section by a bonding agent to form a planar panel.

The display device of the present invention includes such a display device of a planar shape module type as seen in FIG. Referring to a display array section of Fig. 17, a plurality of pixels each including an organic EL element, a thin film transistor, a film capacitor, etc. are formed and integrated in a matrix, such as an insulating substrate. A bonding agent is disposed in a second manner such that it surrounds the pixel array segment or the pixel matrix segment, and a glass or the like opposing substrate is adhered to form a display module. A color filter layer, a protective film, a light intercepting film, or the like may be provided on the transparent opposite substrate as necessary. Since a connector is used to input and output signals and the like from the outside to the pixel array area, and vice versa, for example, a flexible printed circuit (FPC) can be provided on the display module.

The display device according to the present invention has a form of a flat panel and can be applied as a display device of various electronic devices in various fields, wherein an image signal input to or generated in the electronic device is displayed as an image. Such as digital cameras, notebook PCs, portable phones and camcorders. Hereinafter, an example of an electronic device to which the display device is applied will be described.

Figure 18 shows a television set to which the present invention is applied. Referring to Fig. 18, the television set includes a front panel 12 and an image display screen 11 which are formed from a filter glass plate 3 or the like and which is produced by using the display device of the present invention as the image display screen 11.

Figure 19 shows a digital camera to which the present embodiment is applied. Referring to Figure 19, the upper side shows the front elevational view of the digital camera and the lower side shows the rear elevational view of the digital camera. The illustrated digital camera includes an image reading lens, a flash illumination section 15, a display section 16, a control switch, a menu switch, a shutter 19, and the like. The digital camera is produced by using the display device according to the present invention as the display section 16.

Figure 20 shows a notebook type personal computer to which the present invention is applied. Referring to Fig. 20, the notebook type personal computer shown includes a main body 20, a keyboard 21 for inputting characters and the like, a display section 22 for displaying an image on a main body cover, and the like. . The notebook type personal computer is produced using the display device of the present invention as the display section 22.

Figure 21 shows a portable terminal device to which the present invention is applied. Referring to Fig. 21, the left side shows that the portable terminal device is in an open state, and the right side displays a folded state. The portable terminal device includes an upper casing 23, a lower casing 24, a connecting section 25 in the form of a rotating shaft section, a display section 26, a primary display section 27, an image light 28, a camera 29, and and many more. The portable terminal device is produced using the display device of the present invention as the secondary display section 27.

Figure 22 shows a video camera to which the present invention is applied. Referring to FIG. 22, the video camera shown includes a main body section 30; a lens 34 for reading an image of an image reading object; and a start/stop switch 35 for image reading, A screen monitor 36 and the like, the start/stop switch is provided on the side of the body section 30 that faces forward. This video camera is produced using the display device of the present invention as the screen monitor 36.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and changes can be made in accordance with the design requirements and other factors, as long as they are within the scope of the accompanying claims or their equivalents.

1. . . Pixel array section

2. . . Pixel

3. . . Horizontal selector

4. . . Write scanner

5. . . Drive scanner

11. . . Image display screen

12. . . Front panel

13. . . Filter glass plate

15. . . Flashing section

16. . . Display section

19. . . shutter

20. . . main body

twenty one. . . keyboard

twenty two. . . Display section

twenty three. . . Upper side casing

twenty four. . . Lower side housing

25. . . Connection section

26. . . Display section

27. . . Secondary display section

28. . . Image light

29. . . camera

30. . . Body section

34. . . lens

35. . . Start/stop switch

36. . . Screen monitor

C. . . Capacitor

Cel. . . Capacitor

Cl. . . Storage capacitor

DS. . . Feed line

EL. . . Light-emitting element

G. . . Gate

H1. . . Transistor

H2. . . Transistor

R. . . Resistor

S. . . Source

SL. . . Signal line

T1. . . Sampling transistor

T2. . . Drive transistor

Tel. . . Dipole

WS. . . Scanning line

1 is a block diagram showing a general configuration of a display device according to the present invention;

2 is a circuit diagram showing an example of a pixel formed in the display device shown in FIG. 1;

3 is a timing chart illustrating a reference example of the operation of the pixel shown in FIG. 2;

4, 5, 6, and 7 are circuit diagrams illustrating the operation of the pixel shown in FIG. 2;

Figure 8 is a diagram for explaining the operation illustrated in Figure 7;

9 and 10 are circuit diagrams illustrating the operation of the pixel shown in Fig. 2;

Figure 11 is a diagram for explaining the operation illustrated in Figure 10;

Figure 12 is a circuit diagram showing an operation of the pixel shown in Figure 2;

Figure 13 is a timing chart illustrating the operation of the pixel shown in Figure 2;

Figure 14 is a waveform diagram illustrating the operation of the pixel shown in Figure 2;

Figure 15A is a waveform diagram illustrating the operation of the display device shown in Figure 1;

15B and 15C are timing diagrams illustrating a driving method of the display device of FIG. 1;

Figure 15D is a circuit diagram showing the form of an output section of a horizontal selector of the display device of Figure 1;

Figure 15E is a timing diagram illustrating the operation of the horizontal selector shown in Figure 15D;

Figure 16 is a cross-sectional view showing a configuration of one of the display devices of Figure 1;

Figure 17 is a plan view showing a module configuration of one of the display devices of Figure 1;

Figure 18 is a perspective view showing a television set including the display device of Figure 1;

Figure 19 is a perspective view showing a digital still camera including the display device of Figure 1;

Figure 20 is a perspective view showing a notebook type personal computer including the display device of Figure 1;

21 is a schematic diagram showing a portable terminal device including the display device of FIG. 1;

Figure 22 is a perspective view showing a video camera including the display device of Figure 1;

Figure 23 is a circuit diagram showing an example of an existing display device;

Figure 24 is a diagram for explaining the problem of the conventional display device of Figure 23;

Figure 25 is a circuit diagram showing another example of a conventional display device.

1. . . Pixel array section

2. . . Pixel

3. . . Horizontal selector

4. . . Write scanner

5. . . Drive scanner

DS. . . Feed line

SL. . . Signal line

WS. . . Scanning line

Claims (5)

A display device comprising: a pixel array section; and a driving section; the pixel array section comprising a plurality of scanning lines extending along a column direction, a plurality of signal lines extending in a row direction, and a plurality of pixels arranged in columns and rows at intersections of the scan lines and the signal lines; each of the pixels comprising a sampling transistor, a driving transistor, and a storage capacitor And a light-emitting element; the sampling transistor is connected to one of the scan lines at a control terminal thereof, and is connected to one of the signal lines at a pair of current terminals thereof and One of the driving transistors controls a terminal; the driving transistor is connected to the light emitting element at a first current terminal of one of the pair of current terminals, and is connected to the second current terminal of one of the current terminals a power supply; the storage capacitor is coupled to the control terminal of the drive transistor; the drive section includes a write scanner and a signal selector; the write is performed during each horizontal period The scanner supplies a sequential control signal to the scan lines; the signal selector supplies image signals to the signal lines, wherein a signal potential and a reference potential are converted during each horizontal period; when one of the signal lines is associated with the signal When the line has the reference potential, the sampling cell system is placed in an on state in response to a control signal supplied to the associated scan line of one of the scan lines to perform the spread of the erase voltage of the drive transistor. a threshold voltage correcting operation; the sampling transistor performs a signal writing operation for writing the signal potential to the storage capacitor in a writing period, the writing period is from the potential of the associated signal line from the reference Converting a potential to a first timing of the signal potential to a second timing in which the sampling transistor system is placed in a closed state in response to the control signal; the driving transistor is based on the signal written in the storage capacitor a potential supply driving current to the light emitting element to perform a light emitting operation; the signal selector variably adjusting the first timing in response to the signal potential In response to the signal potential variably controlled from the first timing to the second timing of the writing period. The display device of claim 1, wherein when the signal potential has a white level, the signal selector shifts the first timing toward the second timing to shorten the writing period; but when the signal potential has a In the black level, the signal selector shifts the first timing away from the second timing to lengthen the write period. The display device of claim 2, wherein the storage capacitor is connected between the control terminal and one of the current terminals of the driving transistor; and the driving transistor is negatively fed back during the writing period a drive current flowing therebetween to the storage capacitor to perform a correcting operation for a spread of the mobility of the drive transistor; and the signal selector variably adjusts the write period in response to the signal potential to Jiahua should give back the negative feedback. A driving method for a display device, the display device comprising a pixel array section and a driving section, the pixel array section comprising a plurality of scanning lines extending along a column direction and extending along a row a plurality of signal lines, and a plurality of pixels, wherein the plurality of pixels are arranged in columns and rows at intersections of the scan lines and the signal lines; each of the pixels includes a sampling transistor and a driving a transistor, a storage capacitor and a light-emitting element; the sampling transistor is connected at one of its control terminals to an associated scan line of the scan lines, and is connected to the signal lines at a pair of current terminals thereof a first signal line and one of the driving transistor control terminals; the driving transistor is connected to the light emitting element at one of the first current terminals of the pair of current terminals, and the second of the current terminals thereof The current terminal is connected to a power supply; the storage capacitor is connected to the control terminal of the drive transistor; the drive section includes a write scanner and a signal selector, each The write scanner supplies a sequential control signal to the scan lines during a horizontal period, the signal selector supplies image signals to the signal lines, wherein a signal potential and a reference potential are converted during each horizontal period; the driving method The method includes the following steps: when one of the signal lines associated with the signal line has the reference potential, the sampling transistor is placed in an on state in response to a control signal supplied to one of the scan lines associated with the scan line to perform a threshold voltage correcting operation for dispersing the threshold voltage of the driving transistor; performing a signal writing operation for writing the signal potential to the storage capacitor in a writing period, the writing period is from the And converting a potential of the associated signal line from the reference potential to a first timing of the signal potential to a second timing in which the sampling transistor system is placed in a closed state in response to the control signal; according to writing to the storage capacitor The signal potential in the driving transistor supplies a driving current from the driving transistor to the light emitting element to perform a light emitting operation; and in response to the signal potential Variably adjusting the first timing, in response to the signal potential so as to variably control from the first timing to the second timing of the writing period. An electronic device comprising: a display device comprising a pixel array section and a driving section; the pixel array section comprising a plurality of scanning lines extending along a column direction, a plurality of extending along a row direction a signal line, and a plurality of pixels, wherein the plurality of pixels are arranged in columns and rows at intersections of the scan lines and the signal lines; each of the pixels includes a sampling transistor and a driving circuit a crystal, a storage capacitor and a light-emitting element; the sampling transistor is connected to one of the scan lines at one of its control terminals, and is connected to one of the signal lines at a pair of current terminals thereof a first signal line and one of the driving transistor control terminals; the driving transistor is connected to the light emitting element at a first current terminal of one of the pair of current terminals, and a second current at one of the current terminals The terminal is connected to a power supply; the storage capacitor is connected to the control terminal of the driving transistor; the driving section comprises a write scanner and a signal selector; The write scanner supplies a sequential control signal to the scan lines during a period; the signal selector supplies image signals to the signal lines, wherein a signal potential and a reference potential are converted during each horizontal period; when the signals When one of the associated signal lines of the line has the reference potential, the sampling cell system is placed in an on state in response to a control signal supplied to one of the scan lines associated with the scan lines to perform the cancellation of the drive transistor. a threshold voltage correction operation for spreading the threshold voltage; the sampling transistor performs a signal writing operation for writing the signal potential to the storage capacitor in a write cycle, the write cycle is from the associated signal line Transmitting a potential from the reference potential to a first timing of the signal potential to a second timing in which the sampling transistor system is placed in a closed state in response to the control signal; the driving transistor is written according to the storage The signal potential in the capacitor supplies a drive current to the light emitting element to perform a lighting operation; the signal selector is variably adjusted in response to the signal potential The first timing, in response to the signal potential so as to variably control from the first timing to the second timing of the writing period.