TWI397100B - Plasma reactor and method for using the same - Google Patents
Plasma reactor and method for using the same Download PDFInfo
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- TWI397100B TWI397100B TW095121069A TW95121069A TWI397100B TW I397100 B TWI397100 B TW I397100B TW 095121069 A TW095121069 A TW 095121069A TW 95121069 A TW95121069 A TW 95121069A TW I397100 B TWI397100 B TW I397100B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
- H01J37/32155—Frequency modulation
- H01J37/32165—Plural frequencies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32568—Relative arrangement or disposition of electrodes; moving means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32623—Mechanical discharge control means
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Description
本發明係關於半導體製造。更特定言之,本發明係關於一種電漿蝕刻裝置。The present invention relates to semiconductor fabrication. More specifically, the present invention relates to a plasma etching apparatus.
典型的電漿蝕刻裝置包含一反應器,該反應器中存在一腔室,反應性氣體流經該腔室。在腔室內,通常藉由射頻能量將氣體離子化為電漿。電漿之高反應性離子能夠在將一半導體晶圓製成積體電路(IC)期間與材料(諸如,互連件之間的介電質或該半導體晶圓之一表面上的一聚合物遮罩)反應。在蝕刻前,將晶圓置放於腔室內且藉由一使晶圓之一頂部表面曝露於電漿中之夾盤或固持器將晶圓固持於適當位置。A typical plasma etching apparatus includes a reactor in which a chamber is present through which a reactive gas flows. Within the chamber, the gas is typically ionized into a plasma by radio frequency energy. The highly reactive ions of the plasma can be used to form a semiconductor circuit into a bulk circuit (IC) and a material (such as a dielectric between the interconnects or a polymer on one surface of the semiconductor wafer) Mask) reaction. Prior to etching, the wafer is placed in a chamber and held in place by a chuck or holder that exposes the top surface of one of the wafers to the plasma.
在半導體加工中,每一製程中的晶圓上之蝕刻率或沈積率一致性直接影響產品良率。此已成為一處理反應器的主要品質要求之一且因此被視為反應器之設計及開發期間的一非常重要的參數。隨著晶圓直徑之大小的每一增加,確保積體電路之每一批之一致性的問題變得更加困難。舉例而言,隨著晶圓大小及每一晶圓之較小電路大小自200 mm增加至300 mm,邊緣排除區域縮小至(例如)2 mm。因此,至距離晶圓邊緣2 mm為止始終保持一致的蝕刻率、輪廓及臨界尺寸已變得非常重要。In semiconductor processing, the etch rate or deposition rate uniformity on the wafer in each process directly affects product yield. This has become one of the main quality requirements for a process reactor and is therefore considered a very important parameter during the design and development of the reactor. As each of the diameters of the wafers increases, the problem of ensuring the consistency of each batch of integrated circuits becomes more difficult. For example, as the wafer size and the smaller circuit size per wafer increase from 200 mm to 300 mm, the edge exclusion area shrinks to, for example, 2 mm. Therefore, it has become very important to have consistent etch rates, profiles and critical dimensions up to 2 mm from the edge of the wafer.
在一電漿蝕刻反應器中,蝕刻參數(蝕刻率、輪廓、CD等)的一致性受到若干參數影響。保持一致的電漿放電及因此晶圓上方的電漿化學對於改良一致性已變得至關重要。已設想出許多嘗試以藉由經由控制注入一噴頭之氣流、修改該噴頭之設計及在晶圓周圍置放邊緣環來改良晶圓的一致性。In a plasma etch reactor, the consistency of the etch parameters (etch rate, profile, CD, etc.) is affected by several parameters. Consistent plasma discharge and therefore plasma chemistry over the wafer has become critical to improving consistency. Many attempts have been made to improve wafer uniformity by injecting a jet of gas through a nozzle, modifying the design of the nozzle, and placing edge rings around the wafer.
電容耦合之蝕刻反應器中之一問題為缺乏一致的RF耦合,尤其在晶圓之邊緣周圍。圖1說明一習知的電容耦合式電漿處理腔室100,其代表通常用以蝕刻一基板之類型的例示性電漿處理腔室。電漿反應器100包含一腔室102、一底部電極104、一頂部電極106。底部電極104包括一中心底部電極108及一邊緣底部電極110。頂部電極106包括一中心頂部電極112及一邊緣頂部電極114。邊緣頂部電極114及邊緣底部電極110分別具有一環繞中心頂部電極112及中心底部電極108之環形形狀以形成單一平面。One problem in capacitively coupled etch reactors is the lack of consistent RF coupling, especially around the edges of the wafer. 1 illustrates a conventional capacitively coupled plasma processing chamber 100 that represents an exemplary plasma processing chamber of the type typically used to etch a substrate. The plasma reactor 100 includes a chamber 102, a bottom electrode 104, and a top electrode 106. The bottom electrode 104 includes a center bottom electrode 108 and an edge bottom electrode 110. The top electrode 106 includes a center top electrode 112 and an edge top electrode 114. The edge top electrode 114 and the edge bottom electrode 110 each have an annular shape surrounding the center top electrode 112 and the center bottom electrode 108 to form a single plane.
中心底部電極108連接至RF電源供應器118,而頂部電極106及邊緣底部電極110被接地,以便排出產生於頂部電極106與底部電極104之間的電漿116中電荷。如圖1所說明的,由於接地的邊緣底部電極110,輝光放電區(電漿116)的形狀在中心底部電極108之邊緣附近扭曲。彼扭曲導致一置放於中心底部電極108上之基板(未圖示)上的不一致蝕刻率。The center bottom electrode 108 is connected to the RF power supply 118, while the top electrode 106 and the edge bottom electrode 110 are grounded to discharge charge generated in the plasma 116 between the top electrode 106 and the bottom electrode 104. As illustrated in FIG. 1, the shape of the glow discharge region (plasma 116) is distorted near the edge of the center bottom electrode 108 due to the grounded edge bottom electrode 110. This distortion causes an inconsistent etch rate on a substrate (not shown) placed on the central bottom electrode 108.
在電漿處理期間,正離子加速穿過等勢場線以撞擊基板之表面,藉此提供所需的蝕刻效果,諸如改良蝕刻方向性。歸因於上部電極106及底部電極104的幾何形狀,穿過晶圓表面的場線可能不一致且可在晶圓104之邊緣處顯著變化。因此,通常提供接地環110以改良整個晶圓表面上的處理均勻性。During plasma processing, positive ions accelerate through the equipotential field lines to strike the surface of the substrate, thereby providing the desired etching effect, such as improved etch directivity. Due to the geometry of the upper electrode 106 and the bottom electrode 104, the field lines across the wafer surface may be inconsistent and may vary significantly at the edges of the wafer 104. Therefore, the ground ring 110 is typically provided to improve processing uniformity across the wafer surface.
因為頂部電極106中的部分為靜態的,所以不能個別控制晶圓之中心及邊緣處的蝕刻率。蝕刻製程期間的不一致性可在中心與邊緣之間產生不同尺寸,從而降低每一晶圓之可靠產品之良率。Because the portion of the top electrode 106 is static, the etch rate at the center and edges of the wafer cannot be individually controlled. Inconsistencies during the etching process can result in different sizes between the center and the edges, thereby reducing the yield of reliable products per wafer.
因此,需要一種獨立控制一晶圓之中心及邊緣處之蝕刻率的方法及裝置。本發明之一主要目的係解決此等要求且提供進一步相關優勢。Therefore, there is a need for a method and apparatus for independently controlling the etch rate at the center and edges of a wafer. One primary object of the present invention is to address such requirements and to provide further related advantages.
一種電漿反應器,其包含一腔室、一底部電極、一頂部電極、一鄰近於該底部電極且大體上環繞該底部電極的底部接地延伸。頂部接地延伸鄰近於該頂部電極且大體上平行於該頂部電極。該頂部電極亦被接地。該頂部接地延伸能夠獨立地升高或降低以延伸至該底部接地延伸上方的一區域中。A plasma reactor comprising a chamber, a bottom electrode, a top electrode, a ground extension adjacent the bottom electrode and substantially surrounding the bottom electrode. A top ground extension extends adjacent to the top electrode and is substantially parallel to the top electrode. The top electrode is also grounded. The top ground extension can be independently raised or lowered to extend into an area above the bottom ground extension.
本發明之實施例在本文中描述電漿反應器。普通熟習此項技術者將認識到,本發明之以下詳細說明僅為說明性的且不意欲以任何方式限制。擁有本揭示案之益處的此等熟習此項技術者將容易地想到本發明之其他實施例。現將詳細參考附圖中說明之本發明的實施例。在該等圖及以下詳細說明中將使用相同的參考指示符指示相同或類似部件。Embodiments of the invention describe a plasma reactor herein. It will be appreciated by those skilled in the art that the following detailed description of the invention is intended to be illustrative and not restrictive. Other embodiments of the present invention will be readily apparent to those skilled in the art having the benefit of this disclosure. Reference will now be made in detail to the embodiments of the invention illustrated The same reference indicators will be used in the drawings and the detailed description below to refer to the same.
為清楚起見,未展示及描述本文中描述之實施例的所有常規特徵。然而,應瞭解:在任何此種實際實施例之開發中,為達成開發者之具體目標(諸如符合與應用及商業化相關的約束),必須進行許多的實施例具體決策,且此等具體目標將自一實施例變至另一實施例且自一開發者變至另一開發者。此外,應瞭解,此開發工作可能係複雜且耗時的,但對於擁有本揭示案之益處的普通熟習此項技術者而言,此仍為一常規的工程任務。For the sake of clarity, not all of the conventional features of the embodiments described herein are shown and described. However, it should be understood that in the development of any such actual embodiment, in order to achieve a developer's specific objectives (such as compliance with application and commercialization constraints), many embodiment specific decisions must be made, and such specific objectives It will vary from one embodiment to another and from one developer to another. Moreover, it should be appreciated that this development work can be complex and time consuming, but it is still a routine engineering task for those of ordinary skill in the art having the benefit of this disclosure.
圖2說明一電漿反應器200之一實施例,該電漿反應器包含一腔室202、一底部電極208、一底部電極延伸210、一頂部電極212及一頂部電極延伸214。根據一實施例,底部電極延伸210包括一平行且鄰近於該底部電極208且環繞該底部電極208的接地環210。頂部電極延伸214包括一平行且鄰近於該頂部電極212且環繞該頂部電極212的可調整接地環214。2 illustrates an embodiment of a plasma reactor 200 that includes a chamber 202, a bottom electrode 208, a bottom electrode extension 210, a top electrode 212, and a top electrode extension 214. According to an embodiment, the bottom electrode extension 210 includes a ground ring 210 that is parallel and adjacent to the bottom electrode 208 and that surrounds the bottom electrode 208. The top electrode extension 214 includes an adjustable ground ring 214 that is parallel and adjacent to the top electrode 212 and that surrounds the top electrode 212.
底部電極208連接至RF電源供應器218,而頂部電極212、頂部電極延伸214及底部電極延伸210被接地,以用於自產生於頂部電極212與底部電極208之間的電漿216排出電荷。舉例而言,底部電極延伸210及頂部電極延伸212可由一導電材料(諸如鋁)製成。如圖2中所說明的,電漿216包括兩個區域220及222,其基於頂部電極區域214之位置(高度)而具有不同的電漿密度。The bottom electrode 208 is coupled to the RF power supply 218, while the top electrode 212, the top electrode extension 214, and the bottom electrode extension 210 are grounded for discharging charge from the plasma 216 generated between the top electrode 212 and the bottom electrode 208. For example, bottom electrode extension 210 and top electrode extension 212 can be made of a conductive material such as aluminum. As illustrated in FIG. 2, the plasma 216 includes two regions 220 and 222 that have different plasma densities based on the location (height) of the top electrode region 214.
底部電極208經組態以容納一工件且包括一相關聯的底部電極區域,該區域經調適以容納該工件。底部電極208耦接至至少一個電源供應器218。電源供應器218經組態以產生傳送至底部電極208的RF功率。僅出於說明性目的,一雙頻率電源供應器218可用於產生被施加至一氣體以產生電漿216之高電位。更特定言之,所說明的電源供應器218為一工作於2 MHz及27 MHz下的雙電源頻率電源供應器,該電源包括於由Lam Research製造的蝕刻系統中。熟習此項技術者應瞭解,亦可使用能夠在處理腔室202中產生電漿的其他電源供應器。熟習此項技術者應瞭解,本發明不限於2 MHz及27 MHz之RF頻率,而可應用於一廣泛的頻率範圍。本發明亦不限於雙頻電源供應器,而是亦可以一廣泛的頻率範圍應用於具有三或三個以上RF電源之系統。The bottom electrode 208 is configured to receive a workpiece and includes an associated bottom electrode region that is adapted to accommodate the workpiece. The bottom electrode 208 is coupled to at least one power supply 218. Power supply 218 is configured to generate RF power that is delivered to bottom electrode 208. For illustrative purposes only, a dual frequency power supply 218 can be used to generate a high potential that is applied to a gas to produce plasma 216. More specifically, the illustrated power supply 218 is a dual supply frequency power supply operating at 2 MHz and 27 MHz, which is included in an etching system manufactured by Lam Research. Those skilled in the art will appreciate that other power supplies capable of producing plasma in the processing chamber 202 can also be used. Those skilled in the art will appreciate that the present invention is not limited to RF frequencies of 2 MHz and 27 MHz, but can be applied to a wide range of frequencies. The invention is also not limited to dual frequency power supplies, but can also be applied to systems having three or more RF power sources over a wide range of frequencies.
頂部電極212係安置在底部電極208上方相距一預定距離處。頂部電極212、頂部電極延伸214以及接地延伸210經組態以提供一用於自底部電極208傳送的RF功率之完整電路。頂部電極延伸214可獨立於頂部電極212上下移動,以控制底部電極208之邊緣(電漿區222)處的電漿密度。隨著底部電極208之邊緣處的電漿密度變化,可獨立於電漿區220中的蝕刻率控制該區域上的蝕刻率(不管是較快速率還是較慢速率)。普通熟習此項技術者將瞭解,存在許多降低及升高頂部電極延伸214的方法。舉例而言,一機械或電動旋鈕可用以升高或降低頂部電極延伸214而無需打開且進入腔室202的內部。The top electrode 212 is disposed a predetermined distance above the bottom electrode 208. Top electrode 212, top electrode extension 214, and ground extension 210 are configured to provide a complete circuit for RF power delivered from bottom electrode 208. The top electrode extension 214 can move up and down independently of the top electrode 212 to control the plasma density at the edge of the bottom electrode 208 (plasma zone 222). As the plasma density at the edge of the bottom electrode 208 changes, the etch rate (whether faster or slower) on that region can be controlled independently of the etch rate in the plasma region 220. Those of ordinary skill in the art will appreciate that there are many ways to reduce and raise the top electrode extension 214. For example, a mechanical or electric knob can be used to raise or lower the top electrode extension 214 without opening and entering the interior of the chamber 202.
在電漿處理期間,正離子加速穿過等勢場線以撞擊基板之表面,藉此提供所需的蝕刻效果,諸如改良的蝕刻方向性。歸因於頂部電極212及底部電極208的幾何形狀,穿過晶圓表面的場線可能不一致且可在晶圓邊緣處顯著變化。因此,提供頂部電極延伸214及底部電極延伸210以改良整個晶圓表面上的處理均勻性。During plasma processing, positive ions accelerate through the equipotential field lines to strike the surface of the substrate, thereby providing the desired etching effect, such as improved etch directivity. Due to the geometry of the top electrode 212 and the bottom electrode 208, the field lines across the wafer surface may be inconsistent and may vary significantly at the edge of the wafer. Thus, a top electrode extension 214 and a bottom electrode extension 210 are provided to improve processing uniformity across the wafer surface.
電漿反應器200經組態以容納一藉由電漿反應器200轉換成電漿216的氣體(未圖示)。舉例而言且無限制地,泵入腔室內之相對高的氣體流動速率為1500 sccm。亦可應用小於1500 sccm以及大於1500 sccm的氣體流動速率。The plasma reactor 200 is configured to house a gas (not shown) that is converted to a slurry 216 by the plasma reactor 200. By way of example and without limitation, a relatively high gas flow rate into the chamber is 1500 sccm. Gas flow rates of less than 1500 sccm and greater than 1500 sccm can also be applied.
為在腔室202內產生電漿216,使用電源供應器218且在底部電極208與頂部接地電極212之間傳送RF功率。接著氣體被轉換成用於處理工件或一半導體基板的電漿216。舉例而言且無限制地,可應用每立方公分電漿體積2W的RF功率位準。亦可應用小於每立方公分電漿體積2W的RF功率位準。To generate plasma 216 within chamber 202, power supply 218 is used and RF power is transferred between bottom electrode 208 and top ground electrode 212. The gas is then converted into a plasma 216 for processing the workpiece or a semiconductor substrate. For example and without limitation, an RF power level of 2 W per cubic centimeter of plasma volume can be applied. An RF power level of less than 2 W per cubic centimeter of plasma volume can also be applied.
出於說明性目的,圖2中描述之電漿反應器200使用電容耦合以在處理腔室202中產生電漿216。熟習此項技術者應瞭解,本發明之裝置及方法可經調適以與感應耦合電漿一起使用。For illustrative purposes, the plasma reactor 200 depicted in FIG. 2 uses capacitive coupling to create a plasma 216 in the processing chamber 202. Those skilled in the art will appreciate that the apparatus and method of the present invention can be adapted for use with inductively coupled plasma.
普通熟習此項技術者將瞭解,圖2所示之以上配置不意欲限制,且在不偏離本文中揭示之發明概念的情況下,可使用其他配置。舉例而言,兩或兩個以上的鄰近頂部電極延伸214可經定位以進一步控制底部電極208邊緣上的蝕刻率。It will be understood by those skilled in the art that the above configuration shown in FIG. 2 is not intended to be limiting, and other configurations may be used without departing from the inventive concepts disclosed herein. For example, two or more adjacent top electrode extensions 214 can be positioned to further control the etch rate on the edge of the bottom electrode 208.
圖3說明一種使用圖2中說明之電漿反應器的方法。在302中,選擇頂部電極延伸214的位置(升高或降低)。頂部電極延伸214能夠被升高及降低以延伸至該底部電極延伸上方的一區域中。在304中,電漿反應器200處理一由底部電極208支撐的晶圓。在306中,檢查該晶圓以判定整個晶圓表面上的蝕刻一致性。在308中,基於306中之分析調整頂部電極延伸214的位置以進一步改良整個晶圓表面上的蝕刻率一致性。Figure 3 illustrates a method of using the plasma reactor illustrated in Figure 2. At 302, the position (raised or lowered) of the top electrode extension 214 is selected. The top electrode extension 214 can be raised and lowered to extend into a region above the bottom electrode extension. At 304, the plasma reactor 200 processes a wafer supported by the bottom electrode 208. At 306, the wafer is inspected to determine etch uniformity across the wafer surface. At 308, the position of the top electrode extension 214 is adjusted based on the analysis in 306 to further improve the etch rate uniformity across the wafer surface.
儘管已展示及描述了本發明之實施例及應用,但擁有本揭示案之益處的熟習此項技術者將顯而易見:在不偏離本文中之發明概念之情況下,可能有比上文提及之修改多的許多修改。因此,除非在附加申請專利範圍之精神中,否則本發明不受限制。Although the embodiments and applications of the present invention have been shown and described, it will be apparent to those skilled in the art <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Many modifications have been made to the changes. Therefore, the invention is not limited unless it is in the spirit of the appended claims.
100...電容耦合式電漿處理腔室/電漿反應器100. . . Capacitively coupled plasma processing chamber/plasma reactor
102...腔室102. . . Chamber
104...底部電極104. . . Bottom electrode
106...頂部電極106. . . Top electrode
108...中心底部電極108. . . Center bottom electrode
110...邊緣底部電極110. . . Bottom bottom electrode
112...中心頂部電極112. . . Center top electrode
114...邊緣頂部電極114. . . Edge top electrode
116...電漿116. . . Plasma
118...RF電源供應器118. . . RF power supply
200...電漿反應器200. . . Plasma reactor
202...腔室202. . . Chamber
208...底部電極208. . . Bottom electrode
210...底部電極延伸210. . . Bottom electrode extension
212...頂部電極212. . . Top electrode
214...頂部電極延伸214. . . Top electrode extension
216...電漿216. . . Plasma
218...RF電源供應器218. . . RF power supply
220...電漿區220. . . Plasma zone
222...電漿區222. . . Plasma zone
圖1為示意性說明一根據一先前技術之電漿反應器的圖。BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view schematically showing a plasma reactor according to a prior art.
圖2為示意性說明一根據一實施例之電漿反應器的圖。2 is a diagram schematically illustrating a plasma reactor in accordance with an embodiment.
圖3為示意性說明操作圖2中說明之電漿反應器之方法的流程圖。Figure 3 is a flow chart that schematically illustrates a method of operating the plasma reactor illustrated in Figure 2.
200...電漿反應器200. . . Plasma reactor
202...腔室202. . . Chamber
208...底部電極208. . . Bottom electrode
210...底部電極延伸210. . . Bottom electrode extension
212...頂部電極212. . . Top electrode
214...頂部電極延伸214. . . Top electrode extension
216...電漿216. . . Plasma
218...RF電源供應器218. . . RF power supply
220...電漿區220. . . Plasma zone
222...電漿區222. . . Plasma zone
Claims (14)
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US11/152,016 US20060278339A1 (en) | 2005-06-13 | 2005-06-13 | Etch rate uniformity using the independent movement of electrode pieces |
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JP (1) | JP4970434B2 (en) |
KR (2) | KR20130023390A (en) |
CN (1) | CN101194340B (en) |
SG (1) | SG162771A1 (en) |
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Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8012306B2 (en) * | 2006-02-15 | 2011-09-06 | Lam Research Corporation | Plasma processing reactor with multiple capacitive and inductive power sources |
US20070221332A1 (en) * | 2006-03-22 | 2007-09-27 | Tokyo Electron Limited | Plasma processing apparatus |
KR100978754B1 (en) * | 2008-04-03 | 2010-08-30 | 주식회사 테스 | Plasma processing apparatus |
US20080277064A1 (en) * | 2006-12-08 | 2008-11-13 | Tes Co., Ltd. | Plasma processing apparatus |
KR100823302B1 (en) * | 2006-12-08 | 2008-04-17 | 주식회사 테스 | Plasma processing apparatus |
US20080156772A1 (en) * | 2006-12-29 | 2008-07-03 | Yunsang Kim | Method and apparatus for wafer edge processing |
US20170213734A9 (en) * | 2007-03-30 | 2017-07-27 | Alexei Marakhtanov | Multifrequency capacitively coupled plasma etch chamber |
US20090236214A1 (en) * | 2008-03-20 | 2009-09-24 | Karthik Janakiraman | Tunable ground planes in plasma chambers |
US8382941B2 (en) * | 2008-09-15 | 2013-02-26 | Micron Technology, Inc. | Plasma reactor with adjustable plasma electrodes and associated methods |
US20130098390A1 (en) * | 2011-10-25 | 2013-04-25 | Infineon Technologies Ag | Device for processing a carrier and a method for processing a carrier |
US20140060739A1 (en) * | 2012-08-31 | 2014-03-06 | Rajinder Dhindsa | Rf ground return in plasma processing systems and methods therefor |
SG11201608771WA (en) * | 2014-05-09 | 2016-11-29 | Ev Group E Thallner Gmbh | Method and device for plasma treatment of substrates |
CN105789010B (en) * | 2014-12-24 | 2017-11-10 | 中微半导体设备(上海)有限公司 | Plasma processing apparatus and the adjusting method of plasma distribution |
WO2018187679A1 (en) | 2017-04-07 | 2018-10-11 | Applied Materials, Inc. | Plasma density control on substrate edge |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5723227A (en) * | 1980-07-17 | 1982-02-06 | Nippon Telegr & Teleph Corp <Ntt> | Plasma etching device |
JPH08321488A (en) * | 1995-05-26 | 1996-12-03 | Sony Corp | Dry etching method and magnetron rie equipment |
JPH10289881A (en) * | 1997-04-15 | 1998-10-27 | Kokusai Electric Co Ltd | Plasma cvd device |
WO2002093616A1 (en) * | 2001-05-16 | 2002-11-21 | Lam Research Corporation | Hollow anode plasma reactor and method |
US20020170676A1 (en) * | 2000-01-10 | 2002-11-21 | Mitrovic Andrej S. | Segmented electrode apparatus and method for plasma processing |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61164271U (en) * | 1985-04-01 | 1986-10-11 | ||
JPH03138382A (en) * | 1989-10-20 | 1991-06-12 | Nissin Electric Co Ltd | Reactive ion etching device |
US5508881A (en) * | 1994-02-01 | 1996-04-16 | Quality Microcircuits Corporation | Capacitors and interconnect lines for use with integrated circuits |
TW299559B (en) * | 1994-04-20 | 1997-03-01 | Tokyo Electron Co Ltd | |
US5585012A (en) * | 1994-12-15 | 1996-12-17 | Applied Materials Inc. | Self-cleaning polymer-free top electrode for parallel electrode etch operation |
JP2953974B2 (en) * | 1995-02-03 | 1999-09-27 | 松下電子工業株式会社 | Method for manufacturing semiconductor device |
US5567640A (en) * | 1996-01-11 | 1996-10-22 | Vanguard International Semiconductor Corporation | Method for fabricating T-shaped capacitors in DRAM cells |
US6017825A (en) * | 1996-03-29 | 2000-01-25 | Lam Research Corporation | Etch rate loading improvement |
US5705438A (en) * | 1996-10-18 | 1998-01-06 | Vanguard International Semiconductor Corporation | Method for manufacturing stacked dynamic random access memories using reduced photoresist masking steps |
US5731130A (en) * | 1996-11-12 | 1998-03-24 | Vanguard International Semiconductor Corporation | Method for fabricating stacked capacitors on dynamic random access memory cells |
US5792693A (en) * | 1997-03-07 | 1998-08-11 | Vanguard International Semiconductor Corporation | Method for producing capacitors having increased surface area for dynamic random access memory |
US5780338A (en) * | 1997-04-11 | 1998-07-14 | Vanguard International Semiconductor Corporation | Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits |
US5895250A (en) * | 1998-06-11 | 1999-04-20 | Vanguard International Semiconductor Corporation | Method of forming semicrown-shaped stacked capacitors for dynamic random access memory |
US6165276A (en) * | 1999-09-17 | 2000-12-26 | United Microelectronics Corp. | Apparatus for preventing plasma etching of a wafer clamp in semiconductor fabrication processes |
US6432833B1 (en) * | 1999-12-20 | 2002-08-13 | Micron Technology, Inc. | Method of forming a self aligned contact opening |
US6485988B2 (en) * | 1999-12-22 | 2002-11-26 | Texas Instruments Incorporated | Hydrogen-free contact etch for ferroelectric capacitor formation |
WO2001050518A1 (en) * | 2000-01-03 | 2001-07-12 | Micron Technology, Inc. | Method of forming a self-aligned contact opening |
US6872281B1 (en) * | 2000-09-28 | 2005-03-29 | Lam Research Corporation | Chamber configuration for confining a plasma |
US6492774B1 (en) * | 2000-10-04 | 2002-12-10 | Lam Research Corporation | Wafer area pressure control for plasma confinement |
KR100500938B1 (en) * | 2000-12-30 | 2005-07-14 | 주식회사 하이닉스반도체 | Method for forming capacitor |
US6319767B1 (en) * | 2001-03-05 | 2001-11-20 | Chartered Semiconductor Manufacturing Ltd. | Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique |
US6531324B2 (en) * | 2001-03-28 | 2003-03-11 | Sharp Laboratories Of America, Inc. | MFOS memory transistor & method of fabricating same |
US6741446B2 (en) * | 2001-03-30 | 2004-05-25 | Lam Research Corporation | Vacuum plasma processor and method of operating same |
JP2002359232A (en) * | 2001-05-31 | 2002-12-13 | Tokyo Electron Ltd | Plasma treatment apparatus |
US6770166B1 (en) * | 2001-06-29 | 2004-08-03 | Lam Research Corp. | Apparatus and method for radio frequency de-coupling and bias voltage control in a plasma reactor |
US6527911B1 (en) * | 2001-06-29 | 2003-03-04 | Lam Research Corporation | Configurable plasma volume etch chamber |
US6984288B2 (en) * | 2001-08-08 | 2006-01-10 | Lam Research Corporation | Plasma processor in plasma confinement region within a vacuum chamber |
US6717193B2 (en) * | 2001-10-09 | 2004-04-06 | Koninklijke Philips Electronics N.V. | Metal-insulator-metal (MIM) capacitor structure and methods of fabricating same |
US6841943B2 (en) * | 2002-06-27 | 2005-01-11 | Lam Research Corp. | Plasma processor with electrode simultaneously responsive to plural frequencies |
US7405521B2 (en) * | 2003-08-22 | 2008-07-29 | Lam Research Corporation | Multiple frequency plasma processor method and apparatus |
-
2005
- 2005-06-13 US US11/152,016 patent/US20060278339A1/en not_active Abandoned
-
2006
- 2006-06-12 CN CN2006800208380A patent/CN101194340B/en active Active
- 2006-06-12 KR KR1020137002561A patent/KR20130023390A/en not_active Application Discontinuation
- 2006-06-12 KR KR1020077029150A patent/KR101283830B1/en active IP Right Grant
- 2006-06-12 JP JP2008516039A patent/JP4970434B2/en active Active
- 2006-06-12 SG SG201004056-6A patent/SG162771A1/en unknown
- 2006-06-12 WO PCT/US2006/023114 patent/WO2006135924A1/en active Application Filing
- 2006-06-13 TW TW095121069A patent/TWI397100B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5723227A (en) * | 1980-07-17 | 1982-02-06 | Nippon Telegr & Teleph Corp <Ntt> | Plasma etching device |
JPH08321488A (en) * | 1995-05-26 | 1996-12-03 | Sony Corp | Dry etching method and magnetron rie equipment |
JPH10289881A (en) * | 1997-04-15 | 1998-10-27 | Kokusai Electric Co Ltd | Plasma cvd device |
US20020170676A1 (en) * | 2000-01-10 | 2002-11-21 | Mitrovic Andrej S. | Segmented electrode apparatus and method for plasma processing |
WO2002093616A1 (en) * | 2001-05-16 | 2002-11-21 | Lam Research Corporation | Hollow anode plasma reactor and method |
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JP2008544500A (en) | 2008-12-04 |
CN101194340A (en) | 2008-06-04 |
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CN101194340B (en) | 2011-12-28 |
US20060278339A1 (en) | 2006-12-14 |
KR20130023390A (en) | 2013-03-07 |
WO2006135924A9 (en) | 2007-02-22 |
WO2006135924A1 (en) | 2006-12-21 |
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KR20080019225A (en) | 2008-03-03 |
JP4970434B2 (en) | 2012-07-04 |
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