TWI389257B - 藉由複數層磊晶層用於電壓分佈的系統與方法 - Google Patents
藉由複數層磊晶層用於電壓分佈的系統與方法 Download PDFInfo
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
Description
依據本說明書之實施例是關於藉由複數層磊晶層用於在一積體電路元件裏進行電壓分佈的系統和方法。
本申請案為核發給瑪斯雷德(Masleid)的2004年11月16日提出申請之同時待決、共同擁有的美國專利申請案序列號第10/990,885號之一部分延續案,代理人案號為TRAN-P346,名稱為「藉由磊晶層用於電壓分佈的系統和方法」,其全部內容已併入本文以供參考。
核發給潘漢姆(Pelham)和布林(Burr)之2002年12月31日提出申請之同時待決、共同擁有的美國專利申請案序列號第10/334,272號,名稱為「用於表面阱區裏之MOSFET的路徑主體偏壓電壓之對角深阱區間(Diagonal Deep Well Region for Routing Body-Bias Voltage for MOSFETs in Surface Well Regions)」,其全部內容已併入本文以供參考。
希望在一積體電路裏分佈電壓,例如主體偏壓(body biasing)電壓。
因此,藉由複數層磊晶層用於在一積體電路元件裏進行電壓分佈的系統和方法將會高度需求。
故此,揭示藉由複數層磊晶層用於電壓分佈的系統和方法。依據本發明一第一實施例,一積體電路包含一連通類型(connectivity type)的一晶圓基底。一連通類型的一磊晶層被置於一反連通類型的一第二磊晶層上,其被置於該晶圓基底上。
依據本發明另一實施例,一積體電路包含一傳導類型的一磊晶層,其用於實質平行於該第一磊晶層的一平面而傳導一第一電壓。該積體電路進一步包含位於該第一磊晶層下之反傳導類型之一第二磊晶層,其用於實質平行於該第二磊晶層的一平面而傳導一第二電壓。
第1圖揭示依據本發明實施例之積體電路的一部分之一側剖圖。
第2圖揭示依據本發明實施例,藉由一磊晶層之一電壓分佈方法的步驟。
在下列本發明的揭示內容裏,為提供對本發明的一透徹理解,闡明藉由複數層磊晶層用於電壓分佈的系統和方法、及多個具體實施例。不過,將會為熟於此技術領域者所認可地是,本發明可在無該等具體實施例或在其等等效實施例幫助下加以實施。在其餘示例裏,為免不必要混淆本發明而不詳述習知方法、程式、元件和電路。
依據本發明之實施例見述於設計和操作積體半導體的內容中。更特別地,本發明之實施例關於藉由複數層磊晶層用於電壓分佈的系統和方法。但是,可理解地是,本發明之元件可應用於半導體操作的其餘領域裏。
本發明之實施例的下列陳述闡明,當採用一N-阱製程時,將一主體偏壓電壓耦合形成於表面N-阱裏之pFET(或p-型場效電晶體),及/或形成於P-磊晶層裏的nFET(或n-型場效電晶體)。但是,可以理解地是,依據本發明之實施例可等效應用於,當採用一P-阱製程時,將一主體偏壓電壓耦合形成於表面P-阱裏之nFET(或n-型場效電晶體),及/或形成於表面N-磊晶層裏的pFET(或p-型場效電晶體)。因此,依據本發明之實施例很適合形成於p-型和n-型材料裏的半導體,且類似實施例視為處於本發明範圍內。
第1圖揭示依據本發明實施例之一積體電路100的一部分之一側剖圖。積體電路100包含一晶圓基底160,例如P+型材料。置於其上的為n-型材料層150。n-型材料層150典型地為一磊晶層。置於n-型材料層150上的為至少一P-型材料的磊晶層102。可以理解地是,一般而言,一第一導電類型之一磊晶層,比如p-型材料102,傳統上並不置於一第二導電類型之一基底上,比如n-型材料層150。
本發明之實施例很適合多種製程形成複數層磊晶層。舉例而言,複數層磊晶層可被形成於一實質連續製程裏,其中摻質(dopant)類型及/或濃度被改變以產生不同特性的,例如層。作為選擇,一磊晶層可在一第一時間時形成,而一第二磊晶層在一實質不同時間及/或採用一不同製程,例如在一分離和獨特製程裝置裏,而加以形成。
N-型阱擴散103形成一連續「護環(guard ring)」或壁,其形成隔離槽(isolation tub)125的一外邊界。可以理解地是,依據本發明之實施例很適合用於n-型阱擴散103之多種形狀的一阱結構(將示於平面圖裏)。舉例而言,n-型阱擴散103之一平面圖可為矩形,具有曲面特徵,例如凸面或非凸面,及/或包含多種其餘閉合形狀。
眾所周知,傳統隔離槽是藉由形成一隔離結構或槽的一底部之一深n-阱層或板,耦合此類一護環且位於其底層,而加以完成。相對照,n-型材料層150形成隔離槽125的底部。深n-阱104段被置於n-型阱擴散103下麵,其使n-型阱擴散103耦合n-型材料層150。深n-阱104形成一連續「護環」或壁,其一般沿n-型阱擴散103周線而延伸。該深n-阱104在阱擴散103的N-材料和n-型材料層150的N材料之間形成一歐姆連接。
積體電路100包含多個主動元件(active devices),例如PFET(P型場效電晶體)110和140與NFET(N型場效電晶體)120和130。可以理解地是,積體電路100將典型包含多於所示之四個元件。NFET 120形成於包含P-磊晶材料之一隔離槽125裏,其藉由n-型阱擴散103和深n-阱104之結合體而與P-磊晶層102的其餘部分電絕緣。隔離槽125進一步藉由n-型材料層150與基底160絕緣。在隔離槽125裏,NFET 120可被給予,獨立於施加給位於隔離槽125外面的其餘元件之其餘主體偏壓電壓,之一主體偏壓電壓。舉例而言,一主體偏壓電壓可藉由P-接頭121而提供給隔離槽125。
可以理解地是,P-接頭121不需要緊密連接NFET 120。如磊晶層102之一磊晶層是高度導電的。此類導電性足夠使一主體偏壓電壓,例如來自一單獨接頭或有限數量的接頭,耦合如隔離槽125之一隔離槽內的多個NFET。
可以理解地是,有時希望在一表面p-型磊晶層內的一表面p-阱裏形成n-型場效電晶體,比如NFET 120及/或130,以獲得此類元件之一所需特性。舉例而言,此類一可選擇性的表面p-阱(未示)可被形成,以包括NFET 120和P-接頭121。依據本發明之實施例很適合此類可選擇性表面結構。
可以理解地是,p-型場效電晶體一般形成於n-型材料裏。PFET 110形成於n-阱112內。N-阱112形成於p-型材料的隔離槽125內。可以理解地是,n-阱112與積體電路100的其餘n-型材料電絕緣,例如n-阱112與n-型阱擴散103、深n-阱104和n-型材料層150電絕緣。舉例而言,n-阱112沒有延伸到超出磊晶層102之一深度。在n-阱112裏,PFET 110可被給予,獨立於施加給位於n-阱112外面的其餘元件之其餘主體偏壓電壓,之一主體偏壓電壓。舉例而言,一主體偏壓電壓可藉由N-接頭111而提供給n-阱112。以相似於p-接頭121的一方式,可以理解地是,n-接頭111不需要緊密連接pTFE 110。
隔離槽125可形成一主體偏壓區間。一主體偏壓區間典型包含一積體電路之電路的一部分,例如積體電路100,其典型地既包含n-型場效電晶體,例如NFET 120,又包含P型場效電晶體,例如PFET 110。一主體偏壓區間使位於此類一主體偏壓區間內之電路,例如NFET 120及/或PFET 110,在主體偏壓電壓時操作,該主體偏壓電壓與用於位於此類一主體偏壓區間外面之一積體電路的其餘部分之主體偏壓電壓不同。舉例而言,NFET 120及/或PFET 110可和不同的主體偏壓電壓而不是單和積體電路100的NFET 130及/或PFET 140一起操作。
仍舊參看第1圖,NFET 130形成於積體電路100的磊晶層102裏。在磊晶層102裏,NFET 130可被提供一主體偏壓電壓。舉例而言,一主體偏壓電壓可從基底160經P-型通道(P-type via)155而提供給磊晶層102。P-型通道155使P基底160耦合磊晶層102。
P-型通道155不需要一大的垂直剖面區域,例如平面視圖裏,以包含合適的傳導特性,例如低電阻。舉例而言,P-型通道155很適合如平面圖所示之一較小電路剖面。可以理解地是,P-型通道155無疑是相當短的,僅僅橫跨磊晶層102底部到基底160之間的一段距離。可被進一步理解地是,P-型通道155並沒有形成一隔離結構,例如一護環。舉例而言,n-型材料層150A電鄰接n-型材料層150B。可被進一步理解地是,磊晶層102耦合基底160之區域,例如磊晶層102沒有被隔離之區域,比如第1圖裏除了隔離槽125之外的區域,並不需要表面接頭,例如第1圖的p-接頭121。
依據本發明實施例,P-型通道155很適合多種結構類型及/或結構方法。舉例而言,P-型通道155可包含具有足夠摻質之一深p-阱,以克服n-型材料層150的傳導性。
可以理解地是,藉由一基底之一主體偏壓電壓的該種新奇分佈可降低,傳統技術下用於分佈主體偏壓電壓之位於一晶圓表面上的連接結構,例如接頭,和接觸結構及金屬化之需要。
PFET 140形成於磊晶層102裏的n-阱145之內。N-阱145藉由深n-阱通道結構146電耦合n-型材料層150。一主體偏壓電壓可從n-型材料層150A經深n-阱通道146耦合至n-阱145。可以理解地是,深n-阱通道146以相似於習知介於積體電路及/或印刷線路板的佈線層(wiring levels)之間的通孔之方式,作用為一通道結構。可被進一步理解地是,藉由一晶圓基底之一主體偏壓電壓的該種新奇分佈可降低或消除,傳統技術下用於分佈主體偏壓電壓之位於一晶圓表面上的連接結構,例如接頭,和接觸結構及金屬化之需要。
深n-阱通道146不需要一大的垂直剖面區域,例如平面視圖裏,以包含合適的傳導特性,例如低電阻。舉例而言,深n-阱通道146很適合如平面圖所示之一較小電路剖面。可以理解地是,深n-阱通道146無疑是相當短的,僅僅橫跨n-阱145底部到n-型材料層150之間的一段距離。因此,深n-阱通道146在長度及/或寬度方面可實質小於n-阱145,同時卻保持合乎要求的傳導特性。一小尺寸深n-阱通道146在將一主體偏壓電壓分佈給NFET 130功能方面,有助於磊晶層102之側向傳導。可被進一步理解地是,深n-阱通道146並沒有形成一隔離結構,例如一護環。
依據本發明另一實施例,一護環可包含主動元件。舉例而言,第1圖的N-型阱擴散(n-阱)103可由相似於包含PFET 140的n-阱/通道145之一結構所替換。可以理解地是,在此類一示例裏,深n-阱通道146將會需要由例如深n-阱104之一連續結構所替換,以維持隔離槽125之隔離。
可被進一步理解地是,本說明書所述之藉由n-型材料層150之一主體偏壓電壓分佈在n-型材料層150內為實質側向。
依據本發明之再一實施例,進入耦合一n-型材料層150之一n-阱之一n-型接頭,例如n-接頭115或進入n-阱145之一接頭(未示),可被選擇性地組構以提供穿過磊晶層102至n-型材料層150之一方便接頭。相似地,進入位於隔離槽125外面之磊晶層102內之一p-型接頭(未示),可被選擇性地組構以提供自積體電路100的頂面至基底160之一方便接頭。對照P-型通道155,P-型壁結構105將n-型材料層150的部分相互隔離。類似隔離可使n-型材料層150能夠將不同電壓,例如n-阱主體偏壓電壓,分佈於積體電路100的不同區域。可以理解地是,P-型壁結構105應該形成於一n-型隔離結構,例如n-阱擴散103和深n-阱104所形成的護環,之一n-型隔離結構的外面(平面圖裏)。一般而言,P-型壁結構105可具有實質相似於n-阱擴散103和深n-阱104的一平面圖形狀。
舉例而言,P-型壁結構105將n-型材料層150C與n-型材料層150A和150B電絕緣。n-型材料層150C可使一第一主體偏壓電壓,自n-接頭115經n-阱擴散(n-阱)103、深n-阱104,經深n-阱通道147至罩著PFET 110主體之n-阱112,而耦合PFET 110。其間,n-型材料層150A可使一第二主體偏壓電壓藉由至罩著PFET 140之n-阱145的深n-阱通道146,而耦合PFET 140。
可以理解地是,P-型壁結構105一般將使磊晶層102耦合基底160。依據本發明實施例,P-型壁結構105或相似隔離結構可發揮P-型通道155所提供之一些或全部耦合功能作用。因此,在一些實施例中,P-型通道155可被有利地去除。
第2圖揭示依據本發明實施例,藉由一磊晶層進行電壓分佈之一方法200。在210中,一電壓,例如一主體偏壓電壓,被施加到置於鄰近反連通類型的層間之該磊晶層。舉例而言,一電壓可被施加於第1圖的n-接頭115。該電壓經由n-型阱擴散103和深n-阱104(第1圖)而耦合n-型材料層150。
在220中,該電壓在該磊晶層裏被實質側向傳導。在230裏,該電壓從該磊晶層,例如n-型材料層150(第1圖),被分佈到包含該磊晶層的一積體電路裏之另一點處。
舉例而言,再次參看第1圖,一主體偏壓電壓可自n-接頭115經由n-阱112、深n-阱通道147、n-型材料層150C、n-阱擴散103和深n-阱104而耦合PFET 110。
因此,對依據本發明之實施例,藉由複數層磊晶層用於電壓分佈的系統和方法進行了陳述。儘管本發明表述於特別實施例中,但是應該理解,本發明不應該解釋為此類實施例之局限,而應該解釋為依據隨後申請專利範圍之表述。
100...積體電路
102...磊晶層
103...N-型阱擴散
104...深N-阱
105...P-型壁結構
110...P型場效電晶體(PFET)
111...N-接頭
112...N-阱
115...n-接頭
120...N型場效電晶體(NFET)
121...P-接頭
125...隔離槽
130...N型場效電晶體(NFET)
140...P型場效電晶體(PFET)
145...N-阱/通道
146...深N-阱通道
147...深n-阱通道
150...n-型材料層
150A...n-型材料層
150B...n-型材料層
150C...n-型材料層
155...P-型通道
160...晶圓基底
第1圖揭示依據本發明實施例之積體電路的一部分之一側剖圖。
第2圖揭示依據本發明實施例,藉由一磊晶層之一電壓分佈方法的步驟。
100...積體電路
102...磊晶層
103...N-型阱擴散
104...深N-阱
105...P-型壁結構
110...P型場效電晶體(PFET)
111...N-接頭
112...N-阱
115...n-接頭
120...N型場效電晶體(NFET)
121...P-接頭
125...隔離槽
130...N型場效電晶體(NFET)
140...P型場效電晶體(PFET)
145...N-阱/通道
146...深N-阱通道
147...深n-阱通道
150...n-型材料層
150A...n-型材料層
150B...n-型材料層
150C...n-型材料層
155...P-型通道
160...晶圓基底
Claims (26)
- 一種積體電路,其包含:一傳導類型之一晶圓基底;一傳導類型之一第一磊晶層設置於該晶圓上的一反傳導類型(opposite conductivity type)之一第二磊晶層,該第一磊晶層設置於該第二磊晶層上;以及一傳導類型之一深阱,該深阱用於將一主體偏壓電壓從該晶圓基底耦合至形成於該第一磊晶層裏的場效電晶體之主體接點。
- 如申請專利範圍第1項之積體電路,其進一步包含形成於該第二磊晶層一孔裏之一通道結構,其中該主體偏壓電壓自該晶圓基底經由該通道結構而耦合至該第一磊晶層。
- 如申請專利範圍第2項之積體電路,其中該主體偏壓電壓在該晶圓基底裏被實質側向傳導。
- 如申請專利範圍第1項之積體電路,其中一反傳導性之該層使一主體偏壓電壓耦合至形成於該傳導類型的一阱內之一場效電晶體的主體接點。
- 如申請專利範圍第4項之積體電路,其中該主體偏壓電壓在一反傳導性的該層裏被實質側向傳導。
- 如申請專利範圍第4項之積體電路,其進一步包含該反傳導類型之一深阱,其中該主體偏壓電壓自該第二磊晶層經該深阱而耦合至該阱。
- 如申請專利範圍第1項之積體電路,其進一步包含形成於該反傳導類型之一阱裏之該反傳導類型的一接頭,係用於將一電壓耦合至該第二磊晶層。
- 如申請專利範圍第1項之積體電路,其進一步包含形成於該磊晶層裏之該傳導類型的一接頭,係用於將一電壓耦合至該晶圓基底。
- 一種積體電路,其包含:一傳導類型的一第一磊晶層,係用於實質平行於該第一磊晶層一平面而傳導一第一電壓;反傳導類型之一第二磊晶層,係位於該第一磊晶層下且用於實質平行於該第二磊晶層一平面而傳導一第二電壓;以及互補金屬氧化半導體裝置,係設置於該第一磊晶層中。
- 如申請專利範圍第9項之積體電路,其中該第一電壓為供形成於該第一磊晶層裏的一場效電晶體用之一主體偏壓電壓。
- 如申請專利範圍第10項之積體電路,其進一步包含一接點,該接點係位於該第一磊晶層中且用於將該主體偏壓電壓耦合至該第一磊晶層。
- 如申請專利範圍第9項之積體電路,其包含該反傳導類型的一阱,係位於該第一磊晶層裏且用於形成一場效電晶體。
- 如申請專利範圍第12項之積體電路,其包含該反傳導類 型的一深結構,該深結構係用於將該阱耦接該第二磊晶層。
- 如申請專利範圍第13項之積體電路,其中經由該深結構之傳導係實質垂直於該第一磊晶層之該平面。
- 如申請專利範圍第13項之積體電路,其中該深結構係用於將一主體偏壓電壓自該第二磊晶層耦合至該阱。
- 一種積體電路,其包含:一傳導類型之一基底;一反傳導類型之一第一磊晶層,係設置於該基底上且包含第一和第二電氣隔絕區域;以及該傳導類型區域之一第二磊晶層,係設置於該第一磊晶層上且包含第一和第二電氣隔絕區域。
- 如申請專利範圍第16項之積體電路,其中該第二磊晶層的該第一區域被多個該反傳導類型之結構隔離開該第二磊晶層的該第二區域。
- 如申請專利範圍第17項之積體電路,其中該等多個結構實質垂直且延伸進該第一磊晶層裏。
- 如申請專利範圍第18項之積體電路,其中該等多個結構包含該反傳導類型之一表面阱和一深阱。
- 如申請專利範圍第19項之積體電路,其進一步包含該反傳導類型的一阱,該阱係形成於該第二磊晶層中的該第一區域裏,且該阱被設置用於形成場效電晶體。
- 如申請專利範圍第20項之積體電路,其進一步包含該反傳導類型的一深阱,該深阱係用於將該阱耦接該第一磊 晶層。
- 如申請專利範圍第17項之積體電路,其中該第二磊晶層之該第一區域被該第一磊晶層隔離開該基底。
- 如申請專利範圍第16項之積體電路,其中該第一磊晶層之該第一區域被該傳導類型之一結構電氣隔絕於該第一磊晶層之該第二區域。
- 如申請專利範圍第23項之積體電路,其中該結構包含該傳導類型之深阱。
- 如申請專利範圍第16項之積體電路,其中該第一磊晶層之該第二區域包含該傳導類型的一深通道結構,該深通道結構係用於將該第二磊晶層的該第二區域電耦合該基底。
- 一種藉由一磊晶層之分佈電壓的方法,該方法包含:將該電壓施加到設置於鄰近反傳導類型的層間之該磊晶層;在該磊晶層裏實質側向傳導該電壓;以及經由次表面分佈(substrate distribution)將該電壓自該磊晶層分佈至包含該磊晶層之一積體電路內的一主動裝置處。
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