TWI387021B - 半導體組件及製造該組件之方法 - Google Patents

半導體組件及製造該組件之方法 Download PDF

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Publication number
TWI387021B
TWI387021B TW097132934A TW97132934A TWI387021B TW I387021 B TWI387021 B TW I387021B TW 097132934 A TW097132934 A TW 097132934A TW 97132934 A TW97132934 A TW 97132934A TW I387021 B TWI387021 B TW I387021B
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Taiwan
Prior art keywords
trench
die
opening
molded
wafer
Prior art date
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TW097132934A
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English (en)
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TW200917396A (en
Inventor
Swee Kwang Chua
Suan Jeung Boon
Yong Poo Chia
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Micron Technology Inc
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Publication of TW200917396A publication Critical patent/TW200917396A/zh
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Publication of TWI387021B publication Critical patent/TWI387021B/zh

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Description

半導體組件及製造該組件之方法
本發明係關於半導體裝置及組件，以及用於製造該等裝置及組件之方法。
半導體處理及封裝技術正持續演進以滿足對改良之效能以及減小之大小及成本的產業需求。電子產品需要在相對較小空間中具有高裝置密度之封裝半導體組件。舉例而言，可用於記憶體裝置、處理器、顯示器及其他微特徵裝置之空間在個人電子裝置(諸如，手機、膝上型電腦及許多其他產品)中持續減小。因此，存在在仍維持或改良效能且降低成本的同時減小微特徵裝置之總體大小的需要。
一用以改良此等微特徵裝置之效能且減小其大小及成本的技術涉及晶圓級封裝("WLP")。WLP通常指代微特徵裝置在晶圓級的封裝，而非在自晶圓分割裝置之後處理及封裝個別裝置。WLP之一益處在於其產生具有最小形狀因數之晶片大小封裝。WLP藉由將封裝之構件(諸如互連元件)限制在裝置之佔據面積或扇入區域內來達成此等較小大小。此等構件被限制在裝置佔據面積內，因為該等構件係在將該等裝置單一化之前以晶圓級形成。WLP亦提供製造歸因於封裝之總體減小之大小及互連之相對較短長度而具有極佳電及熱效能之封裝之益處。由WLP提供之額外優點包括歸因於在晶圓級之同時或並行處理及測試的製造容易性及減小的組件成本。即使WLP可提供以上列出之益處， 其仍可能不適於具有高插腳計數或高輸入/輸出要求之裝置。舉例而言，裝置佔據面積之空間限制約束封裝中的互連元件之數目及間距。
為了克服此問題，可分割晶粒並將其電鍍在包括環繞晶粒且延伸穿過模製聚合物之互連的組裝封裝中。雖然將此等互連定位在晶粒之佔據面積之外可增加互連之數目及/或間距，但此可顯著增加處理之成本及複雜性。舉例而言，在某些情況下，填充過程可將空氣捕集在通路中，其可導致互連或封裝在填充材料及封裝硬化時破裂。通路中之該等非均勻性提供不一致的電連接且損害互連之完整性及封裝之效能。另外，藉由切除或鑽孔過程來形成通路通常需要以順序方式形成個別通路，從而增加處理時間。藉由蝕刻過程同時形成通路可快得多，但蝕刻可導致不一致的通路大小。亦可能難以使用蝕刻過程達成通路之密集分布。此外，通路形成之後的電鍍及填充處理步驟需要額外處理時間。
本揭示案之若干實施例係針對封裝的半導體裝置、組件及形成該等裝置及組件之方法。本揭示案之許多細節將參考特定結構及形成該等裝置及組件之方法於下文得到描述。術語"半導體裝置"及"半導體組件"始終用以包括多種製品，包括(例如)具有主動構件之半導體晶圓、個別積體電路晶粒、封裝的晶粒及呈堆疊組態之半導體裝置或組件。某些實施例之許多特定細節在圖1A至圖6及隨後之正 文中陳述以提供對此等實施例之透徹理解。在圖1A至圖6中，相似參考字符指代相似構件，且因此，將不關於圖式重複對此等構件中之許多者的描述。若干其他實施例可具有不同於此部分中所描述的組態、構件或過程之組態、構件或過程。因此，熟習此項技術者將瞭解，可存在額外實施例，或所述實施例可在無下文所描述之若干細節的情況下實踐。
圖1A為具有第一側面102、第二側面104及複數個半導體裝置或晶粒106之習知半導體晶圓100的等角視圖。晶粒106可包括(例如)動態或靜態隨機存取記憶體、快閃記憶體、微處理器、成像器或另一類型之特殊應用積體電路。個別晶粒106可包括位於第一側面102之複數個結合位點108，其用以電連接晶粒106與其他構件。如下文所闡釋，結合位點108可包括晶粒106之第一側面102處之交錯組態。藉由邊界線107描繪晶粒106，且在沿邊界線107進行分割以單一化晶粒106之前處理晶粒106並將其組裝在晶圓100上。
在自晶圓100單一化晶粒106之後，可將晶粒106嵌入以晶圓形式組態之模料中，如圖1B中所說明。更具體言之，圖1B為包括第一側面112及第二側面114之模製晶圓110的等角視圖。模製晶圓110由模料116構成，模料116可包括(例如)熱固性物、熱塑性物、熱固性物及熱塑性物之雜化版本，或其他適合模料。模製晶圓110亦包括單一化之晶粒106(個別地識別為第一晶粒106a、第二晶粒106b等)。在 所說明之實施例中，結合位點108位於模製晶圓100之第一側面112，且晶粒106係以柵格狀圖案定位且彼此由模料116中之小路(lane)隔開。舉例而言，如圖1B中所說明，晶粒之間的小路可包括於第一方向上在晶粒106之間延伸之列118a及大致橫穿列118a的於第二方向上在晶粒106之間延伸之行118b。熟習此項技術者將瞭解，將晶粒之間的小路或間隔描述為"列"及"行"係出於說明之目的且未必要求列及行之水平或垂直組態。模料116中之列118a及行118b提供環繞晶粒106的額外空間以形成互連結構或其他構件。歸因於晶圓100材料之成本約束，在晶圓100級(展示於圖1A中)，此等互連結構通常不形成於晶粒106之間。因此，下文描述的組件及方法利用圖1B中所說明之模製晶圓110組態來形成與晶粒106相關聯之互連結構。
圖2A說明經處理且自模製晶圓110單一化的半導體組件200之一實施例。更具體言之，圖2A為包括嵌入模料116中之晶粒106中之一者的半導體組件200之側視橫截面圖。組件200包括自組件200之第一側面202延伸至第二側面204的互連結構或電連接器248(個別地識別為第一電連接器248a及第二電連接器248b)。在此實施例中，電連接器248可具有延伸穿過模料116中之凹陷或開口224的導線結合250。
個別導線結合250可由一導電材料構成，諸如鎳、銅、金、銀、鉑、此等金屬之合金，及/或適於導線結合或類似技術之任何其他導電材料。可基於裝置特定處理器或效能需要來選擇導線結合250之特性。舉例而言，導線結合 250可具有經選擇以滿足效能及整合要求的直徑、幾何形狀(例如，圓形橫截面或平坦橫截面)及/或彈性模數。導線結合250將位於第一側面202的個別相應結合位點108(個別地識別為結合位點108a及以虛線展示的第二結合位點108b)連接至位於第二側面204的相應接觸點230。圖2A中所說明之第二結合位點108b在圖2A之平面外，但其出於說明之目的而以虛線展示。如圖2D及圖2J中所說明，在某些實施例中，結合位點108可彼此交錯或對準。
接觸點230可包括安置在緊接第二側面204之開口224中的導電材料232(例如，焊料)。在某些實施例中，接觸點230可大致與第二側面204共平面，如圖2A所示。然而，在其他實施例中，接觸點230可自第二側面204凹入，或自第二側面204突出且形成凸塊以促進組件之堆疊。接觸點230可安置於形成於第一側面202中之溝槽210與形成於第二側面204中之通道220(其中僅一者展示於圖2A中)之間的相交處。在圖2A中所說明之實施例中，溝槽210大致垂直於圖2A之平面延伸且通道220大致平行於圖2A之平面延伸。導線結合250之第一部分252附著至接觸點230或嵌入接觸點230中，且導線結合250之第二部分254附著至相應結合位點108。組件200進一步包括一安置在組件200之第一側面202之上的介電囊封劑258，其至少部分地覆蓋導線結合250及結合位點108。介電材料258可使連接器248電隔離且支撐導線結合250。
如下文所詳細闡釋，組件200併有來自WLP及重新組態 的模製晶圓110之處理益處，同時仍提供可以相對簡化之處理步驟形成之高品質互連。舉例而言，並非切除、蝕刻或鑽出個別通路，而是於第一側面溝槽210與相應第二側面通道220之相交處形成穿過模料116之開口224。另外，在圖2A所示之實施例中，電連接器248包括連續的導線結合250，其提供穿過組件200之均勻電連接，而不需要形成、電鍍及填充與習知互連相關聯之通路之複雜過程。
在圖2A中所說明之實施例中，組件200及電連接器248已完全形成。以下描述之圖2B至圖2J說明形成圖2A之組件200之方法中的各種技術及階段。圖2B為沿圖1B之線A－A的組件200之橫截面圖，其說明處理環繞第一晶粒106a及第二晶粒106b之模料116之階段。在此階段，移除模料116之一部分以在第一晶粒106a與第二晶粒106b之間的列118a中形成一或多個溝槽210(個別地識別為第一溝槽210a及第二溝槽210b)。溝槽210形成於第一側面202處且延伸至模料中之一中間深度。更具體言之，模料116具有一第一厚度T1 ，且第一晶粒106a及第二晶粒106b各具有一小於第一厚度T1 之第二厚度T2 。第一溝槽210a及第二溝槽210b各具有一小於模料116之第一厚度T1 且等於或大於晶粒106之第二厚度T2 的模料116中之第一深度D1 。因此，個別溝槽210可比個別晶粒106深地延伸至模料116中，而不一路延伸穿至組件200之第二側面204。
在某些實施例中，形成溝槽210可包括以一切割裝置(未圖示)(諸如，晶圓鋸、刀片、雷射、流體噴射、蝕刻劑， 或適於移除模料116之受控制部分的其他工具)部分地分割模料116。舉例而言，為了形成第一溝槽210a及第二溝槽210b，兩個隔開的切割裝置可在單次通過中移除列118a中之相應模料116。在其他實施例中，單一切割裝置可藉由進行多次通過且在諸次通過之間重新定位切割裝置及/或晶圓來移除模料116。在某些實施例中，可在列118a中形成單一溝槽210(而非第一溝槽210a及第二溝槽210b)，其具有與第一溝槽210a與第二溝槽210b之外壁之間的寬度大致相同的寬度(如圖2B中之虛線所示)。另外，雖然圖2B中所說明之溝槽210具有一大致直線的橫截面，但熟習此項技術者將瞭解，溝槽210可包括其他組態，包括(但不限於)彎曲側壁或溝槽210之側壁之間的平滑過渡。
圖2C說明在於第一側面202中形成溝槽210之後的一階段，在該階段中自第二側面204選擇性地移除模料116以在與溝槽210之相交處形成開口224。更具體言之，圖2C為沿圖1B之線B－B的組件200之橫截面圖。出於說明之目的，將圖2C所示之組件200倒置，使得第二側面204面朝上。另外，晶粒106及結合位點108在圖2C之平面外且以虛線展示以便於參考。在此組態中，在一大致橫穿上述溝槽210(僅第一溝槽210a展示於圖2C中)之方向形成多個第二側面通道220。可以大致類似於上文關於溝槽210所描述之方式的方式形成通道220。在某些實施例中，通道220可大致類似於溝槽210，且出於在兩者之間進行區分之清楚性目的稱其為通道而非溝槽。
在圖2C中所說明之實施例中，通道220不形成於第一晶粒106a與第二晶粒106b之間的行118b中，而是以預選定間距形成於個別晶粒106之佔據面積內。在其他實施例中，通道220可形成於第二側面204上之任何預選定位置處。通道220具有一自第二側面204起的至模料116中之第二深度D2 ，該深度不貫穿晶粒106。然而，溝槽210之第一深度D1 與通道220之第二深度D2 之組合等於或大於模料116之第一厚度T1 。因此，第一側面溝槽210與第二側面通道220之間的相交形成開口224且提供穿過模料116之路徑(access)。
圖2D為模製晶圓110之俯視圖，其關於個別晶粒106說明溝槽210及相交通道220之組態。在處理中之此階段，開口224已形成於晶粒106之間的列118a中。在圖2D中所說明之實施例中，第一側面溝槽210在晶粒106之間的列118a中相互平行地延伸且彼此隔開。第二側面通道220(以虛線展示)大致垂直於溝槽210且在個別晶粒106之佔據面積內延伸。溝槽210與通道220之間的相交因此在列118a中形成開口224。然而，在其他實施例中，通道220及溝槽210可經組態以在個別晶粒106之周邊周圍而不僅在其之間的列118a中形成開口224。
上述形成開口之組態及方法提供一形成穿過模料116之開口224之相對較快且節省成本的方法。舉例而言，在形成第一側面溝槽210之後切割單一第二側面通道220藉由穿過模料116之僅單次通過於相交處產生多個開口224。另外，移除溝槽210及通道220之模料116使用現存方法且避 免與習知通路技術相關聯之挑戰中的一些。舉例而言，以雷射鑽孔可產生具有一大於出口直徑之入口直徑的非均勻通路。與鑽出通路相關聯之另一挑戰包括不合需要的熔融且重新固化之模料，其可保持在通路之入口側。此外，充分電鍍並填充一藉由鑽孔技術形成的具有小縱橫比之通路亦可提供重大挑戰。
在形成溝槽210及通道220之後，圖2E及圖2F說明於組件200之第二側面204處形成接觸點230之階段。更具體言之，圖2E為沿圖1B之線B－B的組件200之側視橫截面圖，且圖2F為沿圖1B之線A－A的組件200之側視橫截面圖。一起參看圖2E及圖2F，接觸點230係藉由將導電材料232安置在與相應開口224對準之通道220中而形成。
出於說明之目的，圖2E說明將導電材料232安置在同一組件200中的不同方法。舉例而言，在某些實施例中，導電材料232可藉由印刷、以導電噴墨安置、濺鍍或其他方法而沈積在或嵌入開口224中。如關於圖2E之左側所示，印刷組件236將導電材料232沈積在通道220中。印刷組件236可包括一刮刀238及一具有與通道220及相應開口224對準之孔242的模板240。隨著刮刀238通過模板240，穿過模板240中之相應孔242來安置離散量之導電材料232以形成接觸點230。在其他實施例中且如關於圖2E之右側所示，導電噴墨234可將離散量之導電材料232嵌入開口224中以形成接觸點230。
如圖2F中所說明，導電材料232不填充整個通道220(通 道中之一者展示於圖2F中)，且接觸點230大致與相應開口224對準。因此，為了自第一側面202穿過溝槽210的進一步處理，接觸點230係可達到的。形成接觸點230之導電材料232可包括焊錫膏或可經組態以在開口224處大致保持在離散位置的其他導電材料。舉例而言，為了防止導電材料232延伸或塗佈(smear)至溝槽210或通道220中，可修改導電材料232之冶金術。此外，凸塊下金屬化(未圖示)可應用於通道220中的模料116之側壁，以確保導電材料232與模料116及與組件200相關聯之其他金屬化黏附。
在圖2E及圖2F中所說明之實施例中，接觸點230大致與第二側面204共平面，且因此可提供對組件200之外部電存取。舉例而言，在某些實施例中，諸如焊球之導電部件(未圖示)可附著至接觸點230。然而，在其他實施例中，接觸點230可凹入第二側面204中或自第二側面204突出。舉例而言，接觸點232可為凸塊或凸起接觸點，其自第二側面204突出以促進組件200與其他裝置或組件之堆疊。
如圖2G及圖2H中所說明，在形成緊接第二側面204之接觸點230之後，繼續電連接器248之處理。更具體言之，圖2G及圖2H為沿圖1B之線A－A的組件200之側視橫截面圖，其說明連接第一側面202與第二側面204之間的導線結合250之過程。參考關於圖2G之右側所示之第二晶粒106b，導線結合250經附著至接觸點230且延伸穿過開口224及第二溝槽210b以連接至結合位點108。如關於圖2G之左側所示，導線結合工具256處於進行此連接之過程中。舉例而 言，工具256之頸狀部分258可插入第一溝槽210a中且穿過開口224以將導線結合250直接附著至接觸點230。在某些實施例中，工具256可將導線結合250之第一部分252嵌入接觸點230中。舉例而言，工具256可藉由導線結合250之第一部分252刺穿導電材料232。然而，在其他實施例中，結合工具256本身可刺穿導電材料232且接著將導線結合250之第一部分252注入至接觸點230中。工具256接著纏繞導線結合250且將導線結合250之第二部分254附著至晶粒106a之結合位點108。
在某些實施例中，在將導線結合250附著在相應接觸點230與結合位點108之間之後，接觸點230可經回焊，如圖2H中所說明。回焊接觸點230可幫助確保接觸點230與導線結合250之插入或嵌入的第一部分252之充分附著。在形成電連接器248之後，可將介電囊封劑258安置於第一側面202處，如圖2H中所說明。囊封劑258可保護晶粒106不受污染(例如，歸因於濕氣、粒子等)。囊封劑258亦可使導線結合250及第一側面202處之其他導電特徵穩定化且電隔離。在某些實施例中，該囊封劑可由一介電材料構成且在一模製過程中安置在組件200上。
接下來轉向圖2I及圖2J，自模製晶圓110單一化具有相應晶粒106及構件之個別組件200。更具體言之，圖2I為沿圖1B之線A－A的單一化之組件200之側視橫截面圖，且圖2J為單一化之組件200之俯視圖。然而，出於說明之目的，圖2J不展示第一側面202上之囊封劑258以更好地說明 個別電連接器248。一起參看圖2I及圖2J，可單一化組件200，以使電連接器248在組件200之周邊處被封閉或暴露。舉例而言，可藉由沿個別晶粒106之間的列118a及行118b切割圖1B之模製晶圓110而將組件200單一化。在某些實施例中，列118a在相應溝槽210之間被大致平分。然而，在其他實施例中，可沿列118a(或行118b)單一化個別晶粒106，以在個別晶粒106及電連接器248之周邊周圍留下預訂量之模製材料116。舉例而言，如關於圖2I及圖2J之左側所示，單一化之組件200包括一側壁部分258，其將導線結合250封閉在第一側面202與第二側面204之間的模料116內。然而，在其他實施例中，可單一化組件200，以使該等連接器未被模料116封閉且在組件200之周邊處暴露。舉例而言，如出於說明之目的關於圖2I及圖2J之右側在同一組件200上所示，在於單一化過程期間將模製材料116移除之後，電連接器248暴露。暴露組件200之側面上的電連接器248提供用以在處理之稍後階段中電連接至的另一位置之益處。
圖3A為根據另一實施例組態之組件300的橫截面側視圖。組件300大致類似於以上關於圖1A至圖2J描述之組件200；然而，在此實施例中，組件300具有電連接器348(個別地識別為第一電連接器348a及第二電連接器348b)，其包括具有形成第二側面204上之接觸點330的相應變形之第一部分352之導線結合350。勝於藉由將導電材料232沈積在開口224中來形成上述接觸點230，圖3A中所說明之接觸 點330係由導線結合350之第一部分352形成。因此，電連接器348包括一將第一側面202連接至第二側面204之連續且不中斷的導線結合350。
出於說明之目的，關於圖3A之右側展示第一電連接器348a，且關於圖3A之左側在同一組件300上展示第二電連接器348b。第一電連接器348a包括延伸穿過組件300且具有大致變形成勾狀部件358之第一部分352(具有一大致彎曲或永久偏轉之組態)之導線結合350。導線結合350延伸穿過溝槽210與通道220之相交處的開口224，且導線結合350之第二部分354經附著至相應結合位點108a。導線結合350之第一部分352無需形成實際勾狀物，然而，第一部分352可變形且經組態以使得其至少部分地使導線結合350保持緊接第二側面204。因此，導線結合350之變形之第一部分352在第二側面204處形成接觸點330且提供對組件300之外部電存取。
除了導線結合350之第一部分352變形以大致包括一球狀部件356之外，關於圖3A之左側說明的第二電連接器348b大致類似於第一電連接器348a。球狀部件356係由導線結合350之第一部分352形成且具有一至少與開口224之橫截面尺寸一樣大的橫截面尺寸。因此，球狀部件256可經組態以至少部分地使導線結合350之第一部分352保持緊接第二側面204以形成接觸點330。
在以上所述且在圖3A中說明之實施例中，接觸點330可實質上與第二側面204共平面或自第二側面204突出。舉例 而言，勾狀部件358可經形成以大致與第二側面204共平面，且球狀部件356可經形成以自第二側面204突出。然而，在其他實施例中，導線結合350之第一部分352(包括勾狀部件358或球狀部件356)可經組態以形成一至少部分地凹入組件300之第二側面204中之接觸點330。
如下文所闡釋且關於圖3B及圖3C更詳細描述，電連接器348可提供穿過組件300且在組件300內的高品質互連，其可以節省成本的方式製造。舉例而言，電連接器348可藉由現存半導體處理及導線結合技術形成。另外，電連接器348包括連續且固態之導線結合350(包括第一部分352上之接觸點330)，以形成自第一側面202延伸至第二側面204之電連接器348。
圖3B說明一處理階段，在該階段，導線結合350之第一部分352偏轉或以其他方式變形成導線結合350之第一部分352處的勾狀部件358。如上文關於圖1A至圖2J所描述，開口224形成於第一側面溝槽210與第二側面通道220之間的相交處。因此，導線結合工具256可定位在溝槽210中緊接開口224處且使導線結合350之第一部分352延伸以自第二側面204突出。偏轉部件370可使第一部分352永久偏轉以在第二側面204上形成接觸點330。舉例而言，偏轉部件370可在由箭頭372指示之方向在第二側面204上移動以使導線結合350之第一部分352彎曲。在其他實施例中，偏轉部件370可在其他方向移動以形成第一部分352之勾狀部件358。在使第一部分352變形之後，將導線結合350之第二 部分354附著至第一側面202上之一相應結合位點108。
圖3C說明電連接器348之一處理階段，其中在導線結合350之第一部分352上形成球狀部件356。在此實施例中，緊接自第二側面204突出的導線結合350之第一部分352定位一電子點火("EFO")工具360。EFO工具360緊接第一部分352發出火花362或其他熱源且形成一無空氣球或第一部分352處之球狀部件356。隨後，導線結合工具256將導線結合350之第二部分354附著至第一側面202上之一相應結合位點108。因此，球狀部件356在第二側面204上形成接觸點330。
組件300之處理可以類似於上文關於圖1A至圖2J描述之技術及實施例的方式繼續。舉例而言，可將囊封劑258安置在組件300之第一側面202上，且可使用上述技術自模製晶圓110(展示於圖1B中)單一化個別組件。
圖4A為根據另一實施例組態之組件400的橫截面圖。圖4A所示之組件400的某些態樣大致類似於上述組件；然而，在此實施例中，組件400具有電連接器448，其包括將第一側面202電連接至第二側面204的重新分配結構450，而非導線結合250。更具體言之，每一重新分配結構450可包括一導電層452，其經由第一側面溝槽410而電連接至第二側面接觸點430。在某些實施例中，第一側面溝槽410之側壁部分可包括一導電鍍層454以促進導電層452與接觸點430之間的電連接。然而，在其他實施例中，導電層452可至少部分地填充與接觸點430對準的每一溝槽410之一部 分，以直接連接至接觸點430。類似於上述實施例，組件400亦可包括安置在重新分配結構450之上緊接第一側面202處的囊封劑258。
與圖4A中所說明之組件400相關聯之處理步驟可大致類似於上述處理步驟；然而，在此實施例中，形成穿過模料116之開口424可為不同的。舉例而言，如下文關於說明代表性處理階段之圖4B至圖4D所描述，單一溝槽410(而非第一平行溝槽210a及第二平行溝槽210b)可在個別晶粒106之間形成於第一側面202中。另外，個別孔420(而非第二側面通道220)形成於第二側面204中以橫斷溝槽410且形成開口424。
更具體言之，圖4B為模製晶圓110之仰視圖，其關於個別晶粒106(以虛線展示)說明溝槽410(以虛線展示)及相交孔420之組態。在處理之此階段中，於第一側面202處在列118a中形成單一溝槽410。在形成溝槽410之後，以預選定間距在第二側面204中形成孔420以橫斷溝槽410。在某些實施例中，藉由鑽孔、雷射、蝕刻劑、流體噴射或其他適合技術形成孔420。孔420可具有一大致橫穿溝槽410定向的橢圓形形狀。類似於上述實施例，溝槽410及孔420之組合深度(未圖示)可大於或等於模料116之厚度以產生開口424。
在形成開口424之後，圖4C說明一緊接第一側面202形成重新分配結構450之階段。在某些實施例中，將導電層452直接耦接至相應結合位點108及位於溝槽410處之側壁部分 的導電鍍層454(以虛線展示)。然而，在其他實施例中，導電層452可至少部分地填充與開口424對準的溝槽410之一部分(以虛線展示)以與第二側面204上的接觸點430(圖4C中未展示)直接連接。在沈積導電層452以保護晶粒106且使組件之構件(諸如，重新分配結構450之導電層452)電隔離之後，可將介電囊封劑258(圖4C中未展示)安置在第一側面202上。
在緊接第一側面202安置重新分配結構450之後，可將個別接觸點430嵌入於第二側面204處以完成穿過組件400之電連接器448。為了形成接觸點430，可將導電材料432(展示於圖4A中)之離散部分安置在自第二側面204起且與開口424對準之個別孔420中。導電材料432可包括類似材料且可以大致類似於上文關於圖2E描述之方式的方式安置。
圖4D為呈堆疊組態的單一化組件400(個別地識別為第一組件400a及第二組件400b)之等角視圖。在所說明之實施例中，第二組件400b之第一表面202b可堆疊在第一組件400a之第二表面204a上。可使用上述方法單一化第一組件400a及第二組件400b。在某些實施例中，自模製晶圓110(例如，參見圖4B)單一化晶粒106可包括沿列118a大致平分溝槽410及孔420。因此，在單一化組件400之後，電連接器448可在組件400之側面部分處暴露以電連接至其他構件、裝置及組件。
在某些實施例中，可以不同次序執行上文關於圖4B至圖4D描述之處理步驟。舉例而言，可在於第一側面202中形 成溝槽410之前在第二側面204中形成孔420。因此，孔420可自第二側面204鑽至一中間深度且隨後以導電材料432填充而形成接觸點430。在填充孔420之後，可在第一側面202中形成溝槽410以橫斷嵌入之接觸點430。重新分配結構450可接著被安置在第一側面202上且使第一側面202與第二側面204之間的電連接器448完整。
圖4A至圖4D中所說明之電連接器448亦併有WLP益處且利用晶粒106周圍的間隔以藉由相對簡化之處理步驟提供可靠且高品質的互連。舉例而言，勝於鑽孔或蝕刻穿過整個組件，在溝槽410與孔420之相交處形成開口424。另外，使溝槽410橫斷孔420(或反之亦然)減小此等個別特徵之深度及縱橫比，此可減小稍後處理步驟的複雜性。因此，所說明之實施例可藉由使用一簡化過程來改良電連接器448之可製造性及可靠性。
圖5為用於形成半導體組件之方法或過程500之一實施例的流程圖。在此實施例中，過程500包括在一具有成列及行排列之複數個晶粒的模製晶圓之一模製部分中形成至一中間深度的複數個第一側面溝槽(步驟505)。在某些實施例中，此步驟可包括在晶粒之間的每一列或行中形成單一溝槽。然而，在其他實施例中，此步驟可包括在晶粒之間的每一列或行中形成兩個或兩個以上平行且隔開之溝槽。
該過程進一步包括自位於與第一側面溝槽對準之區域處的模製部分之第二側面移除材料(步驟510)。自第二側面移除材料形成穿過模製晶圓之模製部分之開口。在某些實施 例中，此步驟可包括形成至一中間深度之第二側面溝槽或通道。該等第二側面通道可大致橫穿該等第一側面溝槽。然而，在其他實施例中，此步驟可包括在模料中與該等第一側面溝槽對準之個別位置處形成自第二側面至一中間深度的孔。第一側面溝槽與第二側面通道(或第二側面孔)之深度之組合大於模製晶圓之模料之厚度以形成穿過模料之開口。
該過程進一步包括在模製部分之第二側面於開口處形成複數個電接觸點(步驟515)。在某些實施例中，此步驟可包括將離散量之導電材料(例如，焊料)自第二側面安置在該等開口中。然而，在其他實施例中，此步驟可包括穿過開口插入導線結合之一部分及使導線結合之該部分在第二側面處變形。該過程進一步包括將第二側面接觸點電連接至晶粒上之相應結合位點(步驟520)。在某些實施例中，此步驟可包括將導線結合附著至第二側面上之接觸點且附著至第一側面上之相應結合位點。在包括第二側面上的導線結合之變形部分之實施例中，此步驟可包括將遠離變形部分的導電結合之一部分附著至第一側面上之一相應結合位點。在其他實施例中，此步驟可包括將一重新分配結構安置於第一側面上。
圖5中所說明之過程可在一相對較短的時段中完成，因為不必形成、電鍍及填充個別通路以產生組件之第一側面與第二側面之間的電連接。實情為，相交之溝槽與通道可快速地產生穿過模料的多個開口。舉例而言，在形成第一 側面溝槽之後，形成單一第二側面通道在單次通過中於相交處產生多個開口。
可將具有上文關於圖1A至圖5描述之電連接器之組件中的任一者併入至無數較大及/或較為複雜的系統中之任一者中，該等系統之代表性實例為圖6中示意展示之系統600。系統600可包括處理器602、記憶體604(例如，SRAM、DRAM、快閃及/或其他記憶體裝置)、輸入/輸出裝置606及/或其他子系統或構件608。具有上文關於圖1A至圖5描述的電連接器之組件可包括於圖6所示之構件中的任一者中。所得系統600可執行多種計算、處理、儲存、感測、成像及/或其他功能中的任一者。因此，代表性系統600包括(但不限於)電腦及/或其他資料處理器，例如，桌上型電腦、膝上型電腦、網際網路設備、掌上型裝置(例如，掌上型電腦、穿戴式電腦、蜂巢式或行動電話、個人數位助理、音樂播放器等)、多處理器系統、基於處理器或可程式化的消費電子產品、網路電腦及小型電腦。其他代表性系統600可容納於單一單元中或分散在多個互連單元中(例如，經由通信網路)。系統600之構件因此可包括局部及/或遠端記憶體儲存裝置，及多種電腦可讀媒體中的任一者。
自前述內容將瞭解，雖然為說明起見本文中已描述特定實施例，但在不偏離本發明之情況下可進行各種修改。舉例而言，可將一或多個額外組件堆疊在上述實施例中之任一者中的組件上以形成堆疊組件。在上下文允許的情況 下，單數或複數術語亦可分別包括複數或單數術語。此外，除非詞語"或"明確限制為僅意謂單一項而排除關於清單或者兩個或兩個以上項中之其它項，否則"或"在該清單中之使用應解釋為包括(a)該清單中之任一單一項，(b)該清單中之所有項，或(c)該清單中之項的任何組合。另外，術語"包含"始終用以意謂包括至少所述特徵，以使得並不排除任何更大數目之相同特徵或額外類型之特徵。
在不偏離本文中所揭示的實施例之情況下可進行各種修改。舉例而言，可在其他實施例中組合或消除在特定實施例之背景下描述之特徵。此外，儘管已在某些實施例之背景下描述與彼等實施例相關聯之優點，但其它實施例亦可展現該等優點，且並非所有實施例需要必要地展現該等優點以處於本發明之範疇內。舉例而言，可在模料中形成具有變化寬度及深度之溝槽或通道。因此，除如由隨附申請專利範圍所限制之外，本發明不受限制。
100‧‧‧習知半導體晶圓
102‧‧‧第一側面
104‧‧‧第二側面
106‧‧‧半導體裝置或晶粒
106a‧‧‧第一晶粒
106b‧‧‧第二晶粒
107‧‧‧邊界線
108‧‧‧結合位點
108a‧‧‧結合位點
108b‧‧‧第二結合位點
110‧‧‧模製晶圓
112‧‧‧第一側面
114‧‧‧第二側面
116‧‧‧模料
118a‧‧‧列
118b‧‧‧行
200‧‧‧半導體組件
202‧‧‧第一側面
202b‧‧‧第一表面
204‧‧‧第二側面
204a‧‧‧第二表面
210‧‧‧溝槽
210a‧‧‧第一溝槽
210b‧‧‧第二溝槽
220‧‧‧通道
224‧‧‧開口
230‧‧‧接觸點
232‧‧‧導電材料
234‧‧‧導電噴墨
236‧‧‧印刷組件
238‧‧‧刮刀
240‧‧‧模板
242‧‧‧孔
248‧‧‧連接器
248a‧‧‧第一電連接器
248b‧‧‧第二電連接器
250‧‧‧導線結合
252‧‧‧第一部分
254‧‧‧第二部分
256‧‧‧導線結合工具
258‧‧‧介電囊封劑/介電材料/頸狀部分/側壁部分
300‧‧‧組件
330‧‧‧接觸點
348‧‧‧電連接器
348a‧‧‧第一電連接器
348b‧‧‧第二電連接器
350‧‧‧導線結合
352‧‧‧第一部分
354‧‧‧第二部分
356‧‧‧球狀部件
358‧‧‧勾狀部件
360‧‧‧電子點火("EFO")工具
362‧‧‧火花
370‧‧‧偏轉部件
372‧‧‧箭頭
400‧‧‧組件
400a‧‧‧第一組件
400b‧‧‧第二組件
410‧‧‧第一側面溝槽
420‧‧‧孔
424‧‧‧開口
430‧‧‧第二側面接觸點
432‧‧‧導電材料
448‧‧‧電連接器
450‧‧‧重新分配結構
452‧‧‧導電層
454‧‧‧導電鍍層
600‧‧‧系統
602‧‧‧處理器
604‧‧‧記憶體
606‧‧‧輸入/輸出裝置
608‧‧‧子系統或構件
D1 ‧‧‧第一深度
D2 ‧‧‧第二深度
T1 ‧‧‧第一厚度
T2 ‧‧‧第二厚度
圖1A為習知半導體晶圓之等角視圖。
圖1B為根據本發明之一實施例組態的模製晶圓之等角視圖。
圖2A為根據本發明之一實施例組態的半導體組件之側視橫截面圖。
圖2B及圖2C為說明製造一根據本發明之一實施例組態的半導體組件之方法中之各種階段的側視橫截面圖。
圖2D為說明製造一根據本發明之一實施例組態的半導體 組件之方法中之一階段的俯視圖。
圖2E至圖2I為說明製造一根據本發明之一實施例組態的半導體組件之方法中之各種階段的側視橫截面圖。
圖2J為說明製造一根據本發明之一實施例組態的半導體組件之方法中之一階段的俯視圖。
圖3A為根據本發明之一實施例組態的半導體組件之側視橫截面圖。
圖3B及圖3C為說明製造一根據本發明之一實施例組態的半導體組件之方法中之各種階段的側視橫截面圖。
圖4A為根據本發明之另一實施例組態的半導體組件之側視橫截面圖。
圖4B為說明製造一根據本發明之一實施例組態的半導體組件之方法中之一階段的俯視圖。
圖4C為說明製造一根據本發明之一實施例組態的半導體組件之方法中之一階段的側視橫截面圖。
圖4D為根據本發明之一實施例組態的堆疊半導體組件之等角視圖。
圖5為製造一根據本發明之又一實施例組態的半導體組件之過程的流程圖。
圖6為併有根據本發明之其他實施例組態的半導體組件之系統的示意圖。
106‧‧‧晶粒
108a‧‧‧結合位點
108b‧‧‧第二結合位點
116‧‧‧模料
200‧‧‧半導體組件
202‧‧‧第一側面
204‧‧‧第二側面
210a‧‧‧第一溝槽
210b‧‧‧第二溝槽
220‧‧‧通道
224‧‧‧開口
230‧‧‧接觸點
248a‧‧‧第一電連接器
248b‧‧‧第二電連接器
250‧‧‧導線結合
252‧‧‧第一部分
254‧‧‧第二部分
258‧‧‧介電囊封劑/介電材料/頸狀部分/側壁部分

Claims (35)

  1. 一種製造一半導體裝置之方法，其包含：在一模製晶圓之一第一側面處之一模製材料中在嵌入該模製材料中的一第一半導體晶粒與一第二半導體晶粒之間的一小路中形成至少一溝槽，其中該第一晶粒及該第二晶粒具有位於該第一側面之結合位點；在一與該溝槽重疊之部分處自與該第一側面相對的該模製晶圓之一第二側面移除材料，其中移除該材料形成穿過該模製晶圓的複數個第一開口；形成經由穿過該模製晶圓的相應第一開口而自該第一晶粒及該第二晶粒之個別結合位點延伸至該模製晶圓之該第二側面的電連接器；及單一化該第一晶粒及該第二晶粒。
  2. 如請求項1之方法，其中：該溝槽為一第一溝槽且該方法進一步包含在該模製晶圓之該第一側面中在該小路中形成一第二溝槽，其中該第二溝槽與該第一溝槽隔開且大致平行於該第一溝槽；且自該第二側面移除材料包括在一大致橫穿該第一溝槽及該第二溝槽之方向在該模製晶圓之該第二側面中形成一通道，其中形成該通道分別在該通道與該第一溝槽及該通道與該第二溝槽之間的相交處形成穿過該模製晶圓之該等第一開口及複數個第二開口。
  3. 如請求項2之方法，其中該第一溝槽、該第二溝槽及該 通道各具有小於該模製晶圓之一厚度的在該模製晶圓中之一深度。
  4. 如請求項2之方法，其中形成電連接器包含藉由一穿過該第一開口之第一導線結合將該第一晶粒之一相應結合位點耦接至該第二側面及藉由一穿過該第二開口之第二導線結合將該第二晶粒之一相應結合位點耦接至該第二側面。
  5. 如請求項4之方法，其進一步包含將一介電材料安置在該模製晶圓之該第一側面上及在該第一導線結合及該第二導線結合之至少一部分及該第一晶粒及該第二晶粒之上。
  6. 如請求項4之方法，其中：該等第一開口包括一側壁部分且該等第二開口包括一側壁部分；且單一化該等晶粒包含切開該第一溝槽與該第二溝槽之間的該模製晶圓及至少部分地移除該第一開口之該側壁部分及該第二開口之該側壁部分，以使該第一導線結合及該第二導線結合分別在該單一化之第一晶粒及該單一化之第二晶粒之一周邊處暴露。
  7. 如請求項2之方法，其進一步包含以一導電材料至少部分地填充該等第一開口及該等第二開口，且其中將該第一晶粒及該第二晶粒之該等結合位點電連接至該模製晶圓之該第二側面包括：將一第一導線結合之一第一部分嵌入一相應第一開口 中之該導電材料中且穿過該第一開口將與該第一部分相對的該第一導線結合之一第二部分連接至該第一晶粒之一相應結合位點；及將一第二導線結合之一第一部分嵌入一相應第二開口中之該導電材料中且穿過該第二開口將與該第一部分相對的該第二導線結合之一第二部分連接至該第二晶粒之一相應結合位點。
  8. 如請求項7之方法，其中將該第一導線結合之該第一部分嵌入該導電材料中包括以該第一導線結合之該第一部分刺穿該導電材料。
  9. 如請求項7之方法，其中將該第一導線結合之該第一部分嵌入該導電材料中包括以一導線結合工具刺穿該導電材料及將該第一部分注入至該導電材料中。
  10. 如請求項7之方法，其中至少部分地填充該等第一開口及該等第二開口包括將一離散量之該導電材料安置在該等第一開口及該等第二開口中之每一者中。
  11. 如請求項7之方法，其中該等第一開口及該等第二開口中之該導電材料實質上與該第二側面共平面。
  12. 如請求項2之方法，其中形成電連接器包括：將一第一導線結合插入至該等第一開口中之一者中，以使該第一導線結合之一第一部分穿過該模製晶圓自該第二側面突出；使該第一導線結合之該第一部分變形，其中該變形的第一部分至少部分地防止該導線結合穿過該第一開口收 縮；及將與該第一部分相對的該第一導線結合之一第二部分連接至該第一晶粒之一相應結合位點。
  13. 如請求項12之方法，其中使該第一導線結合之該第一部分變形包括以一電子點火在該第一部分處形成一球狀部件。
  14. 如請求項13之方法，其中該球狀部件自該模製晶圓之該第二側面突出。
  15. 如請求項12之方法，其中使該第一導線結合之該第一部分變形包括永久偏轉該第一部分。
  16. 如請求項1之方法，其中自該第二側面移除材料包括移除與該溝槽對準之個別位置處的該模製晶圓之一離散部分。
  17. 如請求項16之方法，其中移除該模製晶圓之一離散部分包括以一雷射鑽穿該模製晶圓。
  18. 如請求項16之方法，其中形成電連接器包括：將一導電材料安置在該等第一開口中緊接該模製晶圓之該第二側面處；及在該第一晶粒之該等結合位點與該相應第一開口之間形成一重新分配結構。
  19. 如請求項18之方法，其中該重新分配結構至少部分地填充該等第一開口。
  20. 如請求項18之方法，其中在該等第一開口形成之後且在將該導電材料安置在該等第一開口中之後形成該溝槽。
  21. 如請求項18之方法，其中該溝槽橫斷安置在該等第一開口中之該導電材料。
  22. 一種製造一半導體裝置之方法，其包含：在一具有成列及行排列之複數個晶粒的模製晶圓之一模製部分中形成至一中間深度的複數個第一側面溝槽，其中個別晶粒包括複數個結合位點且該等第一側面溝槽沿該等晶粒之間的該等列或行中之一者彼此平行；自位於與該等第一側面溝槽對準之區域處的該模製部分之一背面移除材料，其中移除該材料形成穿過該模製部分之開口；在該模製部分之該背面於該等開口處形成複數個電接觸點；及將該等背面接觸點電連接至該等晶粒上之相應結合位點。
  23. 一種在嵌入一模製晶圓中的兩個或兩個以上半導體晶粒之間形成完全延伸穿過該模製晶圓之一厚度的一或多個孔之方法，該方法包含：在該兩個或兩個以上晶粒之間在一第一方向部分地分割該模製晶圓之一第一側面，其中部分地分割該第一側面形成一具有一小於該模製晶圓之該厚度之深度的溝槽；及自與該第一側面相對的該模製晶圓之一第二側面移除該模製晶圓之一部分且自該第二側面橫斷該溝槽。
  24. 如請求項23之方法，其中： 該溝槽為一第一溝槽，且其中該方法進一步包含：在該兩個或兩個以上晶粒之間平行於該第一溝槽且與該第一溝槽隔開地部分分割該模製晶圓之該第一側面以形成一第二溝槽；且其中移除該模製晶圓之該部分包括在一大致橫穿該第一方向之第二方向部分地分割該第二側面及形成一橫斷該第一溝槽及該第二溝槽之通道。
  25. 如請求項24之方法，其中：該第一溝槽具有一第一深度；該第二溝槽具有該第一深度；且該通道具有一第二深度，其中該第一深度與該第二深度之組合至少等於該模製晶圓之該厚度。
  26. 如請求項23之方法，其中自該第二側面移除該模製晶圓之一部分包含引導一雷射、引導一流體噴射及將一蝕刻劑安置在該第二側面之該部分上中之至少一者。
  27. 一種半導體組件之中間製品，其包含：一模製晶圓，其具有一成形為一具有一第一側面及一第二側面之晶圓的模製材料、一在該模製材料中之第一半導體晶粒及一在該模製材料中與該第一晶粒隔開的第二半導體晶粒；一在該模製晶圓之該第一側面中該第一晶粒與該第二晶粒之間的第一溝槽，其中該第一溝槽具有一小於該模製晶圓之一厚度之深度；及一與該第一溝槽對準的該模製晶圓之該第二側面中之 凹陷，其中該凹陷具有一小於該模製晶圓之該厚度之深度且在一與該第一晶粒與該第二晶粒之間的該第一溝槽之相交處形成一穿過該模製晶圓之第一開口。
  28. 如請求項27之該半導體組件之中間製品，其進一步包含：一在該模製晶圓之該第一側面中該第一晶粒與該第二晶粒之間的第二溝槽，其中該第二溝槽大致平行於該第一溝槽並與該第一溝槽隔開且具有一近似等於該第一溝槽之該深度的深度；且其中該凹陷包括一在該模製晶圓之該第二側面中的大致橫穿該第一溝槽及該第二溝槽之通道；其中該通道在與該第一溝槽之該相交處形成該第一開口且該通道在與該第二溝槽之一相交處形成一第二開口。
  29. 如請求項28之該半導體組件之中間製品，其進一步包含：一第一接觸點，其在該模製晶圓之該第二側面處定位於該第一開口中；一第二接觸點，其在該模製晶圓之該第二側面處定位於該第二開口中；一第一導線結合，其延伸穿過該第一開口且連接至該第一晶粒及該第一接觸點；及一第二導線結合，其延伸穿過該第二開口且連接至該第二晶粒及該第二接觸點。
  30. 如請求項29之該半導體組件之中間製品，其中： 該第一接觸點包括一安置在該第一開口中緊接該第二側面處的導電材料，且其中該第一導線結合被嵌入該第一導電材料中；且該第二接觸點包括安置在該第二開口中緊接該第二側面處的該導電材料，且其中該第二導線結合被嵌入該第二導電材料中。
  31. 如請求項28之該半導體組件之中間製品，其進一步包含：一連接至該第一晶粒之第一導線結合，其中該第一導線結合延伸穿過該第一開口且在緊接該模製晶圓之該第二側面的該第一導線結合之一末端部分處變形；及一連接至該第二晶粒之第二導線結合，其中該第二導線結合延伸穿過該第二開口且在緊接該模製晶圓之該第二側面的該第二導線結合之一末端部分處變形。
  32. 如請求項31之該半導體組件之中間製品，其中該第一導線結合之該變形之末端部分包括一具有一大於該第一開口之一橫截面尺寸之橫截面尺寸的球狀部件，且該第二導線結合之該變形之末端部分包括一具有一大於該第二開口之一橫截面尺寸之橫截面尺寸的球狀部件。
  33. 如請求項31之該半導體組件之中間製品，其中該第一導線結合之該變形之末端部分包括一至少部分地保持該第一導線之該末端部分緊接該模製晶圓之該第二側面的勾狀部件，且該第二導線結合之該變形之末端部分包括一至少部分地保持該第二導線結合之該末端部分緊接該模 製晶圓之該第二側面的勾狀部件。
  34. 如請求項27之該半導體組件之中間製品，其中該第一半導體、該第一溝槽及該第一開口形成併入至一半導體系統中的一半導體組件之部分，該半導體系統包括一處理器、一記憶體裝置及一輸入或輸出裝置中之至少一者。
  35. 一種半導體組件，其包含：一具有一第一側面、一第二側面及一厚度之模料；一嵌入該模料中之晶粒，該晶粒具有一位於該模料之該第一側面之結合位點；一在該模料中與該晶粒隔開的溝槽，該溝槽具有一自該模料之該第一側面起的第一深度；一在該模料中之通道，其具有一自該模料之該第二側面起的第二深度，其中該第一深度與該第二深度之組合至少等於該模料之該厚度，且其中該通道大致橫穿該溝槽且橫斷該溝槽以形成一穿過該模料之開口；一位於該模料之該第二側面之接觸點，該接觸點定位於該通道中且與該開口對準；及一延伸穿過該開口之電連接器，該電連接器具有一連接至該晶粒之該結合位點之第一末端部分及一連接至該接觸點之第二末端部分。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG150404A1 (en) * 2007-08-28 2009-03-30 Micron Technology Inc Semiconductor assemblies and methods of manufacturing such assemblies
US7863722B2 (en) * 2008-10-20 2011-01-04 Micron Technology, Inc. Stackable semiconductor assemblies and methods of manufacturing such assemblies
US11830845B2 (en) * 2011-05-03 2023-11-28 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
KR20120126364A (ko) * 2011-05-11 2012-11-21 에스케이하이닉스 주식회사 반도체 칩 모듈 및 이를 갖는 플래나 스택 패키지
DE102011114635A1 (de) * 2011-10-04 2013-04-04 Smartrac Ip B.V. Chipkarte und Verfahren zur Herstellung einer Chipkarte
US9305854B2 (en) * 2012-08-21 2016-04-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL using UV-cured conductive ink over wafer level package
EP2921833B1 (de) * 2014-03-18 2016-12-28 Mettler-Toledo GmbH Thermoanalytischer Sensor und Verfahren zu dessen Herstellung
US9911629B2 (en) 2016-02-10 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated passive device package and methods of forming same
US10211141B1 (en) 2017-11-17 2019-02-19 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10396053B2 (en) 2017-11-17 2019-08-27 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10276523B1 (en) 2017-11-17 2019-04-30 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10566301B2 (en) 2017-11-17 2020-02-18 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US11972980B2 (en) * 2020-11-25 2024-04-30 Semiconductor Components Industries, Llc Singulation systems and related methods

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391685B1 (en) * 1999-02-23 2002-05-21 Rohm Co., Ltd Method of forming through-holes in a wafer and then dicing to form stacked semiconductor devices
US6412971B1 (en) * 1998-01-02 2002-07-02 General Electric Company Light source including an array of light emitting semiconductor devices and control method
US6521995B1 (en) * 1999-06-28 2003-02-18 Micron Technology, Inc. Wafer-level package
US20030232488A1 (en) * 2002-06-14 2003-12-18 Chua Swee Kwang Wafer level packaging
US20060228825A1 (en) * 2005-04-08 2006-10-12 Micron Technology, Inc. Method and system for fabricating semiconductor components with through wire interconnects
US20070029666A1 (en) * 2004-01-13 2007-02-08 Koh Hoo Goh Chip-Sized Flip-Chip Semiconductor Package and Method for Making the Same

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4567812A (en) 1980-12-31 1986-02-04 Itt Industries, Inc. Brake boosters for automotive vehicles
US4930216A (en) * 1989-03-10 1990-06-05 Microelectronics And Computer Technology Corporation Process for preparing integrated circuit dies for mounting
JPH0513666A (ja) 1991-06-29 1993-01-22 Sony Corp 複合半導体装置
US5266833A (en) * 1992-03-30 1993-11-30 Capps David F Integrated circuit bus structure
US5834162A (en) * 1996-10-28 1998-11-10 Regents Of The University Of California Process for 3D chip stacking
US6372623B1 (en) * 1997-08-18 2002-04-16 Texas Instruments Incorporated Semiconductor device and method of fabrication
US5888884A (en) * 1998-01-02 1999-03-30 General Electric Company Electronic device pad relocation, precision placement, and packaging in arrays
JP3728918B2 (ja) 1998-03-25 2005-12-21 セイコーエプソン株式会社 基板、基板の製造方法及び突起製造装置
JP3447602B2 (ja) 1999-02-05 2003-09-16 シャープ株式会社 半導体装置の製造方法
US6351028B1 (en) 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
JP2001223323A (ja) * 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6528393B2 (en) 2000-06-13 2003-03-04 Advanced Semiconductor Engineering, Inc. Method of making a semiconductor package by dicing a wafer from the backside surface thereof
KR100855015B1 (ko) * 2000-12-21 2008-08-28 테쎄라 테크놀로지스 헝가리 케이에프티. 패키징된 집적회로 및 그 제조 방법
KR100369907B1 (ko) 2001-02-12 2003-01-30 삼성전자 주식회사 반도체 패키지와 그 반도체 패키지의 기판 실장 구조 및적층 구조
US6910268B2 (en) * 2001-03-27 2005-06-28 Formfactor, Inc. Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via
KR100407472B1 (ko) 2001-06-29 2003-11-28 삼성전자주식회사 트렌치가 형성된 상부 칩을 구비하는 칩 적층형 패키지소자 및 그 제조 방법
US6759745B2 (en) 2001-09-13 2004-07-06 Texas Instruments Incorporated Semiconductor device and manufacturing method thereof
KR100455693B1 (ko) 2001-10-17 2004-11-15 주식회사 케이이씨 칩싸이즈패키지 및 그 제조 방법
US6908784B1 (en) 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
SG111069A1 (en) 2002-06-18 2005-05-30 Micron Technology Inc Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods
SG107595A1 (en) 2002-06-18 2004-12-29 Micron Technology Inc Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assembles and packages including such semiconductor devices or packages and associated methods
US6855572B2 (en) 2002-08-28 2005-02-15 Micron Technology, Inc. Castellation wafer level packaging of integrated circuit chips
TWI282158B (en) 2002-10-11 2007-06-01 Siliconware Precision Industries Co Ltd Semiconductor package with ground-enhancing chip and fabrication method thereof
SG119185A1 (en) 2003-05-06 2006-02-28 Micron Technology Inc Method for packaging circuits and packaged circuits
US7141874B2 (en) * 2003-05-14 2006-11-28 Matsushita Electric Industrial Co., Ltd. Electronic component packaging structure and method for producing the same
JP3574450B1 (ja) * 2003-05-16 2004-10-06 沖電気工業株式会社 半導体装置、及び半導体装置の製造方法
JP2004342861A (ja) * 2003-05-16 2004-12-02 Sony Corp チップ状電子部品及び擬似ウェーハ、これらの製造方法、並びに電子部品の実装構造
SG120123A1 (en) 2003-09-30 2006-03-28 Micron Technology Inc Castellated chip-scale packages and methods for fabricating the same
JP2005175019A (ja) * 2003-12-08 2005-06-30 Sharp Corp 半導体装置及び積層型半導体装置
JP4566568B2 (ja) * 2004-01-23 2010-10-20 日東電工株式会社 半導体装置の製造方法及びこれに用いる耐熱性粘着テープ
JP2005310954A (ja) * 2004-04-20 2005-11-04 Nec Corp 半導体パッケージとその製造方法
US20050269692A1 (en) 2004-05-24 2005-12-08 Chippac, Inc Stacked semiconductor package having adhesive/spacer structure and insulation
US7199449B2 (en) 2004-08-24 2007-04-03 Micron Technology, Inc. Wafer backside removal to complete through-holes and provide wafer singulation during the formation of a semiconductor device
DE102004041889B4 (de) 2004-08-30 2006-06-29 Infineon Technologies Ag Halbleitervorrichtung mit gestapelten Halbleiterbauelementen und Verfahren zu deren Herstellung
DE102005003125A1 (de) 2005-01-21 2006-07-27 Robert Bosch Gmbh Elektrische Schaltung und Verfahren zur Herstellung einer elektrischen Schaltung
US7205656B2 (en) 2005-02-22 2007-04-17 Micron Technology, Inc. Stacked device package for peripheral and center device pad layout device
US7781299B2 (en) 2005-03-31 2010-08-24 Kingston Technology Corporation Leadframe semiconductor package stand and method for making the same
KR100716826B1 (ko) * 2005-05-10 2007-05-09 삼성전기주식회사 전자부품이 내장된 기판의 제조방법
KR101107474B1 (ko) * 2005-06-07 2012-01-19 엘지디스플레이 주식회사 소프트몰드와 이를 이용한 패턴방법
US7307348B2 (en) 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US7667333B2 (en) 2006-01-27 2010-02-23 Infineon Technologies Ag Stack of semiconductor chips
US7298037B2 (en) 2006-02-17 2007-11-20 Stats Chippac Ltd. Stacked integrated circuit package-in-package system with recessed spacer
US7511379B1 (en) * 2006-03-23 2009-03-31 National Semiconductor Corporation Surface mountable direct chip attach device and method including integral integrated circuit
US7701045B2 (en) 2006-04-11 2010-04-20 Rambus Inc. Point-to-point connection topology for stacked devices
DE102006037538B4 (de) 2006-08-10 2016-03-10 Infineon Technologies Ag Elektronisches Bauteil, elektronischer Bauteilstapel und Verfahren zu deren Herstellung sowie Verwendung einer Kügelchenplatziermaschine zur Durchführung eines Verfahrens zum Herstellen eines elektronischen Bauteils bzw. Bauteilstapels
US7592691B2 (en) 2006-09-01 2009-09-22 Micron Technology, Inc. High density stacked die assemblies, structures incorporated therein and methods of fabricating the assemblies
KR100809718B1 (ko) 2007-01-15 2008-03-06 삼성전자주식회사 이종 칩들을 갖는 적층형 반도체 칩 패키지 및 그 제조방법
US7585750B2 (en) * 2007-05-04 2009-09-08 Stats Chippac, Ltd. Semiconductor package having through-hole via on saw streets formed with partial saw
SG150404A1 (en) * 2007-08-28 2009-03-30 Micron Technology Inc Semiconductor assemblies and methods of manufacturing such assemblies
JP5098085B2 (ja) 2007-12-18 2012-12-12 スパンション エルエルシー 半導体装置及びその製造方法
DE102008014653A1 (de) * 2008-03-17 2009-09-24 Robert Bosch Gmbh Vorrichtung mit Halbleiterbauelement sowie Herstellungsverfahren
US7659145B2 (en) * 2008-07-14 2010-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device
US7863722B2 (en) 2008-10-20 2011-01-04 Micron Technology, Inc. Stackable semiconductor assemblies and methods of manufacturing such assemblies

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6412971B1 (en) * 1998-01-02 2002-07-02 General Electric Company Light source including an array of light emitting semiconductor devices and control method
US6391685B1 (en) * 1999-02-23 2002-05-21 Rohm Co., Ltd Method of forming through-holes in a wafer and then dicing to form stacked semiconductor devices
US6521995B1 (en) * 1999-06-28 2003-02-18 Micron Technology, Inc. Wafer-level package
US20030232488A1 (en) * 2002-06-14 2003-12-18 Chua Swee Kwang Wafer level packaging
US20070029666A1 (en) * 2004-01-13 2007-02-08 Koh Hoo Goh Chip-Sized Flip-Chip Semiconductor Package and Method for Making the Same
US20060228825A1 (en) * 2005-04-08 2006-10-12 Micron Technology, Inc. Method and system for fabricating semiconductor components with through wire interconnects

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