TWI385456B - Active device array substrate and display panel - Google Patents

Description

Active device array substrate and display panel

The present invention relates to an active array substrate and a display panel, and more particularly to an active device array substrate and a display panel that are less susceptible to damage by electrostatic discharge.

Generally, the liquid crystal display panel includes an active device array substrate, a color filter substrate, and a liquid crystal layer, wherein the active device array substrate is assembled opposite to the color filter substrate, and the liquid crystal layer is located on the active device array substrate and the color filter substrate. between. In the process of fabricating the liquid crystal display panel, both the manufacturing equipment, the operator, and the active device array substrate itself may accumulate a lot of static charges. When the active device array substrate is exposed to a manufacturing device, an operator, or other objects during the manufacturing process, it is likely to cause an electrostatic discharge (ESD) phenomenon.

Since the lines and components on the active device array substrate are very fine, as long as a slight electrostatic discharge occurs, it is easy to cause the entire liquid crystal display panel to be scrapped. In order to solve the problem that the electrostatic discharge phenomenon causes damage to the liquid crystal display panel, an electrostatic discharge protection circuit is generally designed on the active device array substrate. However, the ESD protection circuit is often designed for components in the display area of the active device array substrate. Therefore, if an electrostatic discharge phenomenon occurs in the peripheral circuit region outside the display region, the liquid crystal display panel may be damaged.

The present invention provides an active device array substrate in which components of a peripheral line region are less susceptible to electrostatic discharge damage and have good quality.

The invention further provides a display panel with good quality.

The invention provides an active device array substrate, comprising a substrate, an active device array, a plurality of driving die pads, a plurality of flexible circuit board pads, a detecting circuit, a common potential circuit and an electrostatic protection circuit. The substrate has a display area and a peripheral line area located around the display area. The active component array is located in the display area. The drive wafer pads are located in the peripheral line region and are electrically connected to the active device array. The flexible circuit board pads are located in the peripheral wiring area and are electrically connected to the driving wafer pads. The test line is located between the driver die pad and the flexible circuit board pad. The common potential line is electrically connected to the active device array, wherein the common potential line comprises an annular closed circuit. The annular closed circuit surrounds the active element array and has a connection line between the detection line and the flexible circuit board pads. The ESD protection circuit electrically connects the active device array and the common potential line.

The invention further provides a display panel comprising an active device array substrate, a pair of substrates and a display medium layer as described above. The opposite substrate faces the active device array substrate, and the display dielectric layer is disposed between the active device array substrate and the opposite substrate.

Based on the above, in the active device array substrate of the present invention, the common potential line connected to the ESD line constitutes an annular closed conduction path, and a part of the common potential line is located between the detection line and the flexible circuit board pad. Therefore, the detection circuit and the flexible circuit board pads can be protected by the common potential line to avoid the destruction of the electrostatic discharge. In other words, the active device array substrate of the present invention and the display panel using the active device array substrate have good quality.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a display panel according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of an active device array substrate according to an embodiment of the present invention. Referring to FIG. 1 , the display panel 10 includes an active device array substrate 100 , a pair of substrates 200 , and a display medium layer 300 . The opposite substrate 200 faces the active device array substrate 100, and the display dielectric layer 300 is disposed between the opposite substrate 200 and the active device array substrate 100. In an embodiment, the display medium layer 300 may be a liquid crystal layer. The liquid crystal molecules in the liquid crystal layer can be subjected to an electric field action between the active device array substrate 100 and the opposite substrate 200 to cause a state change and display. In other embodiments, the display medium layer 300 can also be an excitation light layer or other material layer that can serve as a display medium.

Next, referring to FIG. 2 , the active device array substrate 10 includes a substrate 110 , an active device array 120 , a plurality of driving die pads 130 , a plurality of flexible circuit board pads 140 , a detecting circuit 150 , and a common potential line 160 . And an electrostatic protection circuit 170. The substrate 110 has a display area 112 and a peripheral line area 114 located around the display area 112. In the present embodiment, the display area 112 is the inner area surrounded by the broken line in FIG. 2, and the area of the dotted line to the edge of the substrate 110 is the peripheral line area 114.

The active device array 120 is located in the display area 112. The driver die pad 130 is located in the peripheral line region 114 and is electrically connected to the active device array 120. The flexible circuit board pads 140 are located in the peripheral wiring region 114 and are electrically connected to the driving wafer pads 130. The detection line 150 is located between the drive wafer pad 130 and the flexible circuit board pads 140. The common potential line 160 is electrically connected to the active device array 120, wherein the common potential line 160 includes an annular closed line 162. The annular closed line 162 surrounds the active device array 120 and has a connection line 162A between the sense line 150 and the flexible circuit board pads 140. The ESD protection line 170 is electrically connected to the active device array 120 and the common potential line 160.

It is worth mentioning that FIG. 2 is only a schematic diagram of the active device array substrate 100, and some of the components are only shown in a simple manner and are not specifically illustrated because they belong to the prior art. For example, the driving die pad 130 is actually a plurality of conductive pads for connecting the driving wafers, and in the drawings of the embodiment, only the regions configuring the driving wafers are represented without actually depicting each. Conductive pads. The detection line 150 is also represented only by the area in which it is located. In addition, there are actually a plurality of wires (not shown) between the driving die pad 130 and the flexible circuit board pad 140 to be electrically connected to each other.

In detail, the active device array 120 includes a plurality of scan lines 122, a plurality of data lines 124, a plurality of common lines 126, and a plurality of pixel units 128. The scan line 122 is electrically connected to the ESD protection line 170 and a portion of the drive wafer pad 130. The data line 124 intersects the scan line 122 and is electrically connected to the ESD line 170 and another portion of the drive wafer pad 130. The common line 126 is electrically connected to the common potential line 170 and a further portion of the driving wafer pad 130. The pixel units 128 are arranged in an array in the display area 112, and the pixel units 128 are electrically connected to the corresponding scan lines 122, data lines 124, and common lines 126.

In addition, the active device array substrate 100 further includes a plurality of transmission lines 180 disposed at least on one side of the active device array 120 and electrically connecting the active device array 120 and the driving wafer pads 130. In the present embodiment, the transmission lines 180 are located on both sides of the active device array 120. In addition, a portion of the transmission line 180 connected to the common line 126 is more electrically connected to the annular closed line 162.

A plurality of lines for transmitting signals such as the scanning line 122, the data line 124, and the common line 126 are disposed within the range of the display area 112. Once any of the lines is damaged by electrostatic discharge, the active device array 120 will likely be completely scrapped. For example, each scan line 122 is connected to a plurality of pixel units 128 for display. If one of the scanning lines 122 is broken due to the destruction of the electrostatic discharge, the pixel unit 128 connected to the scanning line 122 cannot be turned on for display. As a result, when the active device array substrate 100 is applied to the display panel 10 of FIG. 1, a bright line or a dark line that cannot be normally displayed is generated, and the display panel 10 is defective.

Furthermore, in order to have good signal transmission characteristics, these lines are made of an opaque metal material. However, the configuration of these lines may limit the area in which the display area 112 can be displayed, that is, the display aperture ratio is limited. Therefore, when fabricating these lines, designers often desire to narrow the line width of these lines to enhance the display effect of the display panel 10. However, the narrower the line width, the worse the line's resistance to electrostatic discharge, that is, the easier it is to break due to the destruction of electrostatic discharge. Therefore, the electrostatic protection of the active device array 120 is quite important.

In the present embodiment, the ESD protection line 170 includes a plurality of first ESD protection elements 172 and a plurality of second ESD protection elements 174. The first ESD protection element 172 is connected between the active device array 120 and the second ESD protection element 174, and the second ESD protection element 174 is connected between the first ESD protection element 172 and the common potential line 160. The static electricity protection circuit 170 can conduct static charges accumulated in the active device array 120 to the outside of the active device array substrate 100 by the common potential line 160 to avoid damage caused to each component by electrostatic discharge.

However, FIG. 3 is a partially enlarged schematic view showing a region A of the active device array substrate of FIG. Referring to FIG. 2 and FIG. 3 simultaneously, in the peripheral line region 114, there is often an accumulation of static charge between the flexible circuit board pads 140 and the detection lines 150. Therefore, the common potential line 160 of the present embodiment includes at least the annular closed line 162, wherein the connecting line 162A of the annular closed line 162 is disposed between the flexible circuit board pad 140 and the detecting line 150. Once there is unnecessary static charge accumulation between the flexible circuit board pads 140 and the sense lines 150, the connection lines 162A can conduct these static charges. As a result, the flexible circuit board pads 140 and the detection lines 150 can obtain appropriate protection to help improve the quality of the active device array substrate 100.

According to the actual test results, if the active device array substrate 100 is not provided with the connection line 162A, the detection line 150 is destroyed under the electrostatic test of 8000 volts. However, the active device array substrate 100 of the present embodiment is provided with the connection line 162A, so that only a slight defect occurs at the edge of the connection line 162A during the electrostatic test of 8000 volts, and the detection circuit 150 and the flexible circuit board pad 140 remain. Complete structure. The defect appearing at the edge of the connection line 162A does not cause the common potential line 160 to lose its original function. That is to say, the respective components of the active device array substrate 100 can still operate normally. Therefore, the active device array substrate 100 of the present embodiment can effectively reduce damage to its internal components due to an electrostatic discharge effect.

In summary, the common potential line of the active device array substrate of the present invention has an annular closed circuit, and at least a portion of the annular closed circuit is disposed between the flexible circuit board pad and the detection line. Therefore, when improper static charge accumulation or electrostatic discharge occurs in the peripheral line region of the active device array substrate, the annular closed circuit can effectively discharge the static electricity. That is, the active device array substrate of the present invention is less susceptible to damage by electrostatic discharge and has good quality. Of course, the display panel of the present invention has the above-described active device array substrate, so the display panel of the present invention also has good quality and is not easily damaged by the destruction of electrostatic discharge.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ display panel

100‧‧‧Active component array substrate

110‧‧‧Substrate

112‧‧‧ display area

114‧‧‧ Peripheral area

120‧‧‧Active component array

122‧‧‧ scan line

124‧‧‧Information line

126‧‧‧Shared line

128‧‧‧ pixel unit

130‧‧‧Drive wafer pads

140‧‧‧Soft circuit board pads

150‧‧‧Test line

160‧‧‧Common potential line

162‧‧‧Circular closed circuit

162A‧‧‧ connection line

170‧‧‧Electrostatic protection lines

172‧‧‧First Electrostatic Protection Element

174‧‧‧Second electrostatic protection element

180‧‧‧ transmission line

200‧‧‧ opposite substrate

300‧‧‧Display media layer

A‧‧‧ area

FIG. 1 illustrates a display panel according to an embodiment of the present invention.

2 is a schematic diagram of an active device array substrate according to an embodiment of the present invention.

3 is a partially enlarged schematic view showing a region A of the active device array substrate of FIG. 2.

100. . . Active device array substrate

110. . . Substrate

112. . . Display area

114. . . Peripheral area

120. . . Active component array

122. . . Scanning line

124. . . Data line

126. . . Shared line

128. . . Pixel unit

130. . . Drive wafer pad

140. . . Flexible circuit board pad

150. . . Detection line

160. . . Shared potential line

162. . . Ring closed circuit

162A. . . Cable

170. . . Electrostatic protection circuit

172. . . First electrostatic protection element

174. . . Second electrostatic protection element

180. . . Transmission line

A. . . region

Claims (10)

An active device array substrate includes: a substrate having a display area and a peripheral line area located around the display area; an active device array located in the display area; and a plurality of driving die pads located in the peripheral circuit area And electrically connected to the active device array; a plurality of flexible circuit board pads located in the peripheral circuit region and electrically connected to the driving chip pads; a detecting circuit located at the driving chip pads and the Between the flexible circuit board pads; a common potential line electrically connected to the active device array, wherein the common potential line includes an annular closed circuit surrounding the active device array, and the annular closed circuit has the detection circuit and a connecting line between the flexible circuit board pads; and an electrostatic protection circuit electrically connected to the active device array and the common potential line. The active device array substrate of claim 1, wherein the active device array comprises: a plurality of scanning lines electrically connected to the static electricity protection circuit and a portion of the driving wafer pads; and a plurality of data lines, Intersecting with the scan lines and electrically connecting to the ESD protection line and another portion of the drive wafer pads; a plurality of common lines electrically connected to the common potential line and another The plurality of pixel units are arranged in the display area, and the pixel units are electrically connected to the corresponding scan lines, the data lines, and the common lines. The active device array substrate according to claim 2, further comprising a plurality of transmission lines disposed at least on one side of the active device array and electrically connecting the active device array and the driving wafer pads. The display panel of claim 3, wherein the portions of the transmission lines connected to the common lines are electrically connected to the annular closed circuit. The active device array substrate according to claim 1, wherein the static electricity protection circuit comprises a plurality of first static electricity protection elements and a plurality of second static electricity protection elements, wherein the first static electricity protection elements are connected to the active device array And between the second static protection components, and the second static protection components are connected between the first static protection components and the common potential line. A display panel includes an active device array substrate, comprising: a substrate having a display area and a peripheral line region located around the display area; an active device array located in the display area; and a plurality of driving wafer pads, Located in the peripheral circuit area and electrically connected to the active device array; a plurality of flexible circuit board pads are located in the peripheral circuit area and Electrically connected to the driving chip pads; a detecting circuit between the driving chip pads and the flexible circuit board pads; a common potential line electrically connected to the active device array, wherein the common potential The circuit includes an annular closed circuit surrounding the active device array, and the annular closed circuit has a connecting line between the detecting circuit and the flexible circuit board pads; and an electrostatic protection circuit electrically connecting the active device array And the common potential line; the pair of substrates facing the active device array substrate; and a display dielectric layer disposed between the active device array substrate and the opposite substrate. The display panel of claim 6, wherein the active device array comprises: a plurality of scan lines electrically connected to the static electricity protection circuit and a portion of the drive wafer pads; a plurality of data lines, and the The scan lines intersect and are electrically connected to the ESD protection line and another portion of the drive wafer pads; a plurality of common lines electrically connected to the common potential line and a further portion of the drive wafer pads; And a plurality of pixel units arranged in the display area, the pixel units being electrically connected to the corresponding scan lines, the data lines, and the common lines. The display panel of claim 7, wherein the display panel of claim 7 The active device array substrate further includes a plurality of transmission lines disposed at least on one side of the active device array and electrically connecting the active device array and the driving wafer pads. The display panel of claim 8, wherein the transmission lines connected to the common lines are electrically connected to the annular closed circuit. The display panel of claim 6, wherein the static electricity protection circuit comprises a plurality of first static electricity protection elements and a plurality of second static electricity protection elements, wherein the first static electricity protection elements are coupled to the active device array and Between the second static protection elements, the second static protection elements are connected between the first static protection elements and the common potential line.