TWI383434B - Method of lifting off and fabricaing array substrate for liquid crystal display device using the same - Google Patents

Description

Stripping method and method for preparing array substrate in liquid crystal display and device thereof

The present invention relates to a liquid crystal display, and more particularly to a peeling method and a method for preparing an array substrate of a liquid crystal display device (LCD) by using a lift-off method, thereby preventing degradation of image quality.

Liquid crystal displays utilize the optical anisotropy and polarization characteristics of liquid crystal molecules. Since the liquid crystal molecules have a thin and long shape, they have a specific alignment direction, and the coordination direction of the liquid crystal molecules can be controlled by application of an electric field. In other words, when the electric field strength or direction changes, the coordination direction of the liquid crystal molecules changes. Due to the non-isotropic optical properties of the liquid crystal molecules, the incident light passes through the liquid crystal molecules to cause refraction, and the image is displayed by controlling the light transmittance.

The liquid crystal display has a thin film transistor (TFT) as a switching element, which means that the liquid crystal display is an active array type liquid crystal display (AM-LCD). Since the active array type liquid crystal display has high resolution and excellent characteristics for displaying moving images, its use is quite extensive.

FIG. 1 is a schematic plan view of a conventional liquid crystal display array substrate. In Fig. 1, the pixel electrode and the common electrode are both disposed on the array substrate. This may be an in-plane switching mode LCD device.

As shown in FIG. 1, the array substrate 10 includes a display area DR and a non-display area NDR provided around the display area DR. The display area DR is an area in which an image is displayed, and It depends on the change in the arrangement of the liquid crystal molecules. The gate line 20 and the data line 30 are interleaved to define a plurality of pixel regions. Next, common lines 50 are formed on the array substrate 10, and the common line 50 is parallel to the gate lines and separated by a distance. In the non-display area NDR, the common line 50 is supplied with a common signal through the common connection line 70.

If the common connection line 70 is formed in the same layer as the gate line 20, there is a problem of short circuit between the gate lines 20. Therefore, the common connection line 70 needs to be formed in the same layer as the data line 30. The common connection line 70 is connected to the common line 50 through a common contact hole (CMH).

A pixel electrode (not shown), a common electrode (not shown), and a thin film transistor T are disposed in each pixel region. A pixel electrode (not shown) is alternately disposed with a common electrode (not shown). The thin film transistor T is disposed at the boundary between the gate line 20 and the data line 30, and has a gate electrode, a semiconductor layer, a source electrode, and a drain electrode. The gate electrode extends from the gate line 20, the source electrode extends from the data line 30, and the drain electrode is at a distance from the source electrode.

The gate pad 42 is disposed at the end of the gate line 20, and the data pad 44 is disposed at the end of the data line 30, and the gate pad 42 and the data pad 44 are respectively passed through a tape carrier package (TCP) and The data is tape-and-reel package, and the gate drive unit (not shown) and the data drive unit (not shown) are connected. In addition, although not shown in FIG. 1, a static electricity protecting circuit line and various signal lines are disposed in the non-display area.

The shared connection line 70 converts the shared signal generated by the shared signal generating unit to the shared line 50. Therefore, the common connection line 70 has a wider line width than each of the common lines 50.

In other words, a stripping method is derived to reduce the masking process. However, due to various signal lines and patterned metal, such as the common connection line 70, the gate pad 42, the data pad 44, the electrostatic protection circuit line (not shown), and the multi-patterned inspection line for detecting the short circuit problem (multi Pattern search line; MPS) and dummy lines have a relatively large line width, so many problems occur in the stripping process. In particular, since the stripper used in removing the patterned photoresist does not penetrate into the middle of the signal line and the patterned metal, the unnecessary patterned photoresist cannot be completely removed.

The foregoing problems are explained in the description of the following figures. Fig. 2 is a partially enlarged view of a portion A of Fig. 1. Figure 3A-3C is a schematic view of the cross-sectional process along line III-III in Figure 2. Figure 2 and Figure 3A-3C show the common connection line. When there is a problem with the signal line and the metal line, for example, the gate pad electrode, the data pad electrode, and the electrostatic protection circuit line in the non-display area (not drawn) Show), multi-patterned inspection line (MPS) and dummy line.

The common connection line 70 in Fig. 2 is formed by a peeling manufacturing method. Since the stripping liquid used in the stripping method easily penetrates into the photosensitive patterned edge portions D and E in the common connecting line 70, the photosensitive patterning can be completely removed. The aforementioned photosensitive patterning is, for example, a patterned photoresist. However, the stripping solution is not Easy to penetrate into the middle part F. Next, the photosensitive layer and the photosensitive patterning are preferably patterned by the PR layer and the PR, respectively. Therefore, after the stripping process, photosensitive patterning remains. The remaining sensitization patterning will have a serious impact on the quality of the subsequent process or image display. Moreover, this problem is more serious when there is a relatively large line width.

Next, the problems that arise in the stripping method will be explained more closely. As shown in FIG. 3A, a gate insulating layer 145 is formed on the substrate 10. In the non-display area (NDR), a metal layer 60 and a patterned photoresist 82 are formed on the gate insulating layer 145. The patterned photoresist 82 is formed on the metal layer 60 by a portion of the metal layer 60.

Next, as shown in FIG. 3B, the metal layer 60 is etched using the patterned photoresist 82 as an etch mask, and a portion of the gate insulating layer 45 is exposed. Due to the etched metal layer 60, the width of the patterned photoresist 82 is greater than the width of the common line 70. A thin film layer 50, such as a protective layer, is then formed over the patterned photoresist 82 and the exposed gate insulating layer 45. As described above, the patterned photoresist 82 has a wider width than the common line 70 due to over-etching, so that the edge portion of the thin film layer 50 between the patterned photoresist 82 and the common line 70 is discontinuous.

Subsequently, as shown in Fig. 3C, the stripping liquid penetrates into the discontinuous portion of the film layer 50 to perform the peeling method. At this time, the patterned photoresist 82 and the thin film layer 50 on the patterned photoresist 82 can be removed at the same time. In this example, since the stripping liquid easily penetrates into the edge portions D and E of the common line, the patterned photoresist 82 at the edge portions D and E and the film layer 50 at the patterned photoresist 82 can be completely Was removed. However, the stripping liquid does not easily penetrate into the intermediate portion F of the common line 70, and therefore, the patterned photoresist 82 located at the intermediate portion F and the film layer 50 thereon are hardly removed. The remaining patterned photoresist 82 can have a severe impact.

In other words, there are first to fourth non-display areas on the array substrate. For example, the gate pad and the data pad are respectively located in the first and second non-display areas. When the material layers of the pixel electrodes are formed on the third and fourth regions, many problems such as short circuit and corrosion of adjacent pixel regions are generated. However, since the non-display area has a relatively large line width, the material layer of the patterned photoresist and the pixel electrode is left, thereby degrading the quality of the image display.

Accordingly, the present invention provides a method of stripping and a method of fabricating an array substrate for a liquid crystal display that solves one or more of the problems due to limitations and disadvantages of the prior art.

Other features and advantages of the present invention will be briefly described below. The objectives and other advantages of the invention will be realized and at the

In order to achieve the effects of the present invention, the present invention is a stripping method comprising forming a first material layer on a substrate; forming a patterned photoresist having a first and second holes on the first material layer. Using patterned photoresist as a patterned mask, patterning the first material layer to form a patterned material having first and second trenches, the first trench and the second trench respectively being opposite to the first hole With the second hole; Forming a second material layer on the entire surface of the substrate having the patterned photoresist and the first and second trenches; simultaneously removing the patterned photoresist and the second material layer on the patterned photoresist, wherein the first and the first A portion of the patterned material between the two trenches, and a portion of the patterned material on the sides of the first and second trenches, as a whole, form a line.

In another embodiment of the present invention, a method for fabricating an array substrate of a liquid crystal display includes forming a gate line and a gate electrode on the substrate, the substrate including a display area and first to first regions located around the display area Four non-display areas; the gate electrode is disposed in the display area; forming a data line, a data pad, a semiconductor layer, a source electrode and a drain electrode, the data line and the gate line are alternately arranged, and the data pad is disposed at one end of the data line and The semiconductor layer is disposed on the gate electrode, the source electrode is connected to the data line and is disposed on the semiconductor layer, and the drain electrode is spaced apart from the source electrode region and disposed on the semiconductor layer Forming an insulating material layer on a complete surface of the substrate having the data line, the data pad, the source electrode and the drain electrode; forming a first patterned photoresist and a second patterned photoresist, the first patterned light The first patterned photoresist has first and second holes, the first patterned photoresist exposes a portion of the drain electrode, and the first and second holes respectively correspond to the data pad First And a second portion; patterning the insulating material layer with the first and second patterned photoresist as a pattern mask to form a protective layer and a first patterned protective layer, the protective layer exposing a portion of the drain electrode, The first patterned protective layer has first and second trenches, the first and second trenches respectively exposing the first and second portions of the data pad; and having the first and second patterned photoresists, the protective layer and a complete table of the substrate of the first patterned protective layer Forming a layer of conductive material on the surface; and simultaneously removing the first and second patterned photoresist and conductive material layers on the first and second patterned photoresists by a lift-off method.

In another embodiment of the present invention, a method for fabricating an array substrate of a liquid crystal display includes forming a gate line and a gate pad on the substrate, and the gate pad is disposed at one end of the gate line; Forming a gate insulating layer, an intrinsic amorphous germanium layer, an impurity doped amorphous germanium layer and a metal layer on a complete surface of the substrate, the substrate comprising a gate line and a gate pad; a patterned metal layer, The impurity is doped with an amorphous germanium layer, an intrinsic amorphous germanium layer and a gate insulating layer to expose the gate pad and form a data line interlaced with the gate line, thereby defining a pixel region and one end of the data line a data pad; forming a conductive material layer on the entire surface of the substrate having the data line and the data pad; forming a first pattern drawing photoresist and a second pattern drawing photoresist, and the pattern drawing photoresist comprises a plurality of first and second The hole, the second pattern drawing photoresist comprises a plurality of third and fourth holes, the first and second holes respectively corresponding to the first and second portions of the gate pad, and the third and fourth holes respectively correspond to the third of the data pads And the fourth part; patterning with the first and second Blocking as a mask, patterning a layer of conductive material to form a first patterned conductive material and a second patterned conductive material, the first patterned conductive material having a plurality of first and second trenches, and a second patterning The conductive material has a plurality of third and fourth trenches, the first and second trenches respectively exposing the first and second portions of the gate pad, and the third and fourth trenches respectively exposing the third and fourth portions of the data pad a portion; forming a protective layer on a complete surface of the substrate having the first and second patterned photoresists and the first, second, third, and fourth trenches; and removing the first The second patterned light Blocks the protective layer located on it.

The features and implementations of the present invention are described in detail below with reference to the accompanying drawings.

The preferred embodiment of the present invention will be described in detail below with reference to the drawings.

Figure 4 is a partial plan view showing a line containing a groove in an embodiment of the present invention. Figure 5A-5C is a schematic view of the cross-section process along line V-V in Figure 4.

As shown in FIG. 4, a plurality of first trenches 172 and a plurality of second trenches 174 are formed on line 170. Each of the first trenches 172 and the second trenches 174 is strip-shaped or rectangular. The line 170 may be one of a common connection line, a gate pad, a data pad, an electrostatic protection circuit line, an MPS line, and a dummy line. Line 170 has a relatively wide line width. For example, line 170 has a line width greater than about 200 microns. The first grooving grooves 172 are arranged in the first row and spaced apart from each other. The second trenches 174 are arranged in the second column and are spaced apart from each other. After the line 170 is fabricated by the lift-off method, the patterned protective layer or patterned photoresist of the intermediate portion of the line 170 can be completely removed. However, away from a portion between the first trench 172 and the second trench 174, patterned guards 152 and 156 (or patterned photoresist) may remain. A more detailed explanation is as follows, and please refer to the 5A-5C drawing at the same time.

As shown in FIG. 5A, a first material layer 175 is formed on the substrate 100. Subsequently, a photoresist layer 180 is formed on the first material layer 175. Considering other cases, an inorganic insulating material having one of yttrium oxide and tantalum nitride may be deposited on the substrate 100 A gate insulating layer (not shown) is formed between the first material layers 175. The first material layer 175 may be at least one of a first layer of a transparent conductive material and a second layer of a transparent conductive metal material. The first layer of transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO). The second layer of conductive metal material may be copper (Cu), molybdenum (Mo), titanium molybdenum alloy (Mo-Ti), aluminum (Al), aluminum alloy or chromium (Cr). Figure 5A shows that the first material layer 175 comprises a photoresist layer 180 formed thereon.

Next, a mask 190 is disposed on the photoresist layer 180. The mask 190 has a transmissive area (TA) and a blocking area (BA) interlaced with each other. Considering other possible situations, a half-tone mask can be used. The halftone mask can have not only a transparent region and a barrier region but also a half-transmissive area.

Next, as shown in FIG. 5B, the photoresist layer 180 is exposed through the mask 190 and developed. Therefore, the photoresist layer 180 with respect to the translucent area TA is preferably removed, thereby exposing a portion of the first material layer 175. The photoresist layer 180 with respect to the barrier region BA remains on the first material layer 175 to form first to third patterned photoresists 182, 184, 186.

Subsequently, the exposed first material layer 175 is patterned through the first to third patterned photoresists 182, 184, and 186 to form first to third patterned lines 170a, 170b, and 170c. Furthermore, the first portion between the first and second patterned lines 170a, 170b is defined as a first trench 172 and the second portion between the second and third patterned lines 170b, 170c The part is defined as a second groove 174. First to third The end portions of the case lines 170a, 170b, and 170c are interconnected to form a line 170. In this embodiment, the first material layer 175 is over-etched, such that the widths of the first to third patterned photoresists 182, 184, 186 are respectively greater than the first to third patterned lines 170a, 170b and The width of 170c is large. The foregoing refers to an undercut structure.

As shown in FIG. 4, one of the first and second trenches 172, 174 is removed from the width W of the line 170 to facilitate the characteristics of the stripping method. Considering the electrical characteristics of the line 170, the first and second patterned grooves 172, 174 are spaced apart from each other, and the first and second grooves 172, 174 are parallel to each other and are arranged in the first and second columns, respectively. Second, the adjacent two grooves have the same distance. Due to the first and second grooves 172, 174, the stripping liquid used in the peeling method easily penetrates into the first and second grooves 172, 174.

Thereafter, on the substrate 100 having the first to third patterned photoresists 182, 184, 186, a second material layer 150 is formed. The second material layer 150 is formed of at least one of a transparent conductive material, a conductive metal material, and a protective layer. The transparent conductive material may be ITO or IZO. The conductive metal material may be copper (Cu), molybdenum (Mo), titanium-molybdenum alloy (Mo-Ti), aluminum (Al), aluminum alloy or chromium (Cr). The protective layer may be an organic insulating material or an inorganic insulating material. For example, the protective layer may be composed of tantalum oxide or tantalum nitride. The second material layer 150 is precipitated by a sputtering method.

As described above, since the widths of the first to third patterned photoresists 182, 184, and 186 are larger than the widths of the first to third patterned lines 170a, 170b, and 170c, respectively, Therefore, first to third patterned photoresists 182 are in the vicinity of each of the first to third patterned photoresists 182, 184, 186 and each of the first to third patterned lines 170a, 170b, and 170c. The edge portions of 184 and 186 are exposed. Accordingly, the second material layer 150 formed between each of the first to third patterned photoresists 182, 184, 186 and each of the first to third patterned lines 170a, 170b, and 170c is discontinuous.

Next, as shown in FIG. 5C, the stripping liquid penetrates into the first to third patterned photoresists 182, 184, 186 through the discontinuous second material layer. Then, the first and third patterned photoresists 182, 186 and the second material layer 150 located thereon are simultaneously removed. The second material layer 150 of the first and second trenches 172, 174 may remain therewith to form a first patterned material 158. The second patterned material 158 is located between the first and second patterned lines 170a, 170b and between the second and third patterned lines 170b, 170c.

By the stripping method, the second patterned photoresist 184 on the second patterned line 170b and the second material layer 150 on the second patterned photoresist 184 are completely removed. However, the first and third patterned photoresists 182, 186 on the first and third patterned lines 170a, 170c, respectively, and the protective layer 152 on the first and third patterned photoresists 182, 186, 156, there will be a part. Although the above peeling method has a large effect compared to the prior art, the aforementioned peeling method still has some problems. This problem may be caused by the arrangement of the grooves.

Fig. 6 is a plan enlarged view of a portion H in Fig. 4. As shown in Figure 6 It is shown that in the stripping method, the stripping liquid penetrates to the edges of the first and second grooves 172, 174 along the arrow method (in Fig. 6, when the stripping liquid penetrates into each edge, the arrow line is Pointing to the corners of the first and second grooves). Therefore, the first and third patterned photoresists 182, 186 separated from the first and second patterned photoresists 172, 174 may not be completely removed, and some portions remain. This phenomenon has an impact on subsequent processes and LCD devices. In particular, the residual patterned photoresist can cause damage to the abrasive used in grinding an alignment layer, thus causing line defects. Second, the residual patterned photoresist reacts with the liquid crystal molecules to cause a chemical reaction, which in turn affects the image.

In the following description, the foregoing problems will be solved by the respective embodiments. Figure 7 is a partial plan view showing a line having a groove in an embodiment of the present invention. Figure 8, is a schematic view of the cross-sectional process along line VIII-VIII of Figure 7.

As shown in FIG. 7, a plurality of first trenches 273 and a plurality of second trenches 274 are formed on line 270. The plurality of third grooves 273 are arranged in the (2N-1)th column to be spaced apart from each other, and the plurality of second grooves 274 are arranged in the (2N)th column to be spaced apart from each other. Wherein, the aforementioned N is a positive integer. Each of the second trenches 274 corresponds to a front portion of two adjacent first trenches 273, and each of the first trenches 273 corresponds to a front portion of two adjacent second trenches 274. Line 270 has a line width greater than about 200 microns. Due to the first and second trenches 273, 274 of Figure 7, the position of each line 270 is at a distance from the first trench to the second trench 273, 274, with a relatively low offset. Therefore, the problem of the patterned photoresist remaining in the peeling method can be avoided.

Line 270, as shown in Figure 7, was prepared in the following manner. As shown in Figure 8A A first material layer 260 is formed on the substrate 200. Next, a photoresist layer 280 is formed on the first material layer 260 by applying a photoresist. Considering other possible cases, a gate insulating layer (not shown) may be formed between the substrate 200 and the first material layer 260 by depositing an inorganic insulating material having one of yttrium oxide and tantalum nitride. The first material layer 260 may be at least one of a first layer of a transparent conductive material and a second layer of a transparent conductive metal material. The first layer of transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO). The second layer of conductive metal material may be copper (Cu), molybdenum (Mo), titanium molybdenum alloy (Mo-Ti), aluminum (Al), aluminum alloy or chromium (Cr). Figure 8A shows that the first material layer 260 includes a photoresist layer 280 formed thereon.

Next, a mask 290 is disposed on the photoresist layer 280. The mask 290 has a transmissive area (TA) and a blocking area (BA) interlaced with each other. Considering other possible situations, a half-tone mask can be used. The halftone mask can have not only a transparent region and a barrier region but also a half-transmissive area.

Next, as shown in FIG. 8B, the photoresist layer 280 is exposed through the mask 290 and developed. Therefore, the photoresist layer 280 with respect to the translucent area TA can be preferably removed, thereby exposing a portion of the first material layer 260, as shown in FIG. 8B. The photoresist layer 280 with respect to the barrier region BA remains on the first material layer 260 to form first to fourth patterned photoresists 282, 284, 286, 288, as shown in FIG. 8B.

Subsequently, as shown in FIG. 8C, the exposed first material layer 260 is patterned through the first to fourth patterned photoresists 282, 284, 286, and 288 to form a first One to second grooves 273, 274. The first to fourth patterned lines 270a, 270b, 270c, and 270d corresponding to the first to fourth patterned photoresists 282, 284, 286, and 288, respectively, are spaced apart from each other. End portions of the first to fourth patterning lines 270a, 270b, 270c, 270d are connected to each other to form a line 270. A space between the first to fourth patterning lines 270a, 270b, 270c, 270d is defined as first and second grooves 273, 274.

The first and second grooves 273, 274 correspond to a portion of the line 270 which is removed between the widths W of the wires 270 in order to improve the characteristics of the stripping method. The first and second grooves 273, 274 are arranged as shown in Fig. 7.

In detail, each of the first and second grooves 273, 274 is strip-shaped. The third grooves 273 are arranged in the (2N-1)th column to be spaced apart from each other, and the second grooves 274 are arranged in the (2N)th column to be separated from each other (the aforementioned N is a positive integer) ). Each of the second trenches 274 corresponds to a front portion of two adjacent first trenches 273, and each of the first trenches 273 corresponds to a front portion of two adjacent second trenches 274. The position of each line 270 is at a distance from the first trench to the second trench 273, 274 with a relatively low offset. Therefore, the stripping liquid used in the stripping method can easily penetrate the patterned photoresist in a complete region of the line 270. The first and second grooves 273, 274 are provided in consideration of the distortion of the line 270 area and electrical characteristics.

In this embodiment, the first material layer 260 is patterned using isotropic wet etching. Under the first to fourth patterned photoresists 282, 284, 286, 288, the first material layer 260 is over-etched, as such, compared to the first through fourth patterned lines 270a, 270b, respectively. 270c, 270d, the first to fourth patterned photoresists 282, 284, 286, 288 have a larger line width. In other words, first to fourth patterning is performed in the vicinity of each of the first to fourth patterned photoresists 282, 284, 286, 288 and the first to fourth patterning lines 270a, 270b, 270c, 270d The edge portions of the photoresists 282, 284, 286, 288 are exposed. In the lift-off method, the stripper may penetrate into the exposed edge portions of the first to fourth patterned photoresists 282, 284, 286, 288.

Thereafter, a second material layer 250 is formed on the substrate having the first to fourth patterned photoresists 282, 284, 286, 288. The second material layer 250 is formed of at least one of a transparent conductive material, a conductive metal material, and a protective layer. The transparent conductive material may be ITO or IZO. The conductive metal material may be copper (Cu), molybdenum (Mo), titanium-molybdenum alloy (Mo-Ti), aluminum (Al), aluminum alloy or chromium (Cr). The protective layer may be an organic insulating material or an inorganic insulating material. For example, the protective layer may be composed of tantalum oxide or tantalum nitride. The second material layer 150 is precipitated by a sputtering method. In particular, the protective layer may be precipitated by a sputtering method instead of being formed by a plasma chemical vapor deposition method.

In general, the protective layer of a liquid crystal display is deposited by an inorganic insulating material by a plasma chemical vapor deposition method, however, since the plasma chemical vapor deposition method requires a relatively high temperature, for example, higher than about 350. The degree C, plus the first to fourth patterned photoresists 282, 284, 286, 288 have a heat resistance of about 150 degrees C, so the first to fourth patterns are patterned by the plasma chemical vapor deposition method. Photoresist 282, 284, 286, 288 cause damage. When the protective layer is deposited by a plasma chemical vapor deposition method, the first to fourth patterned photoresists 282, 284, 286, 288 may collapse, and Will be completely covered by the protective layer. In this embodiment, since the peeling liquid portion penetrates into the first to fourth patterned photoresists 282, 284, 286, and 288, many problems occur in the peeling method. Furthermore, the residual patterned photoresist reacts with the liquid crystal display molecules to cause a chemical defect. In order to solve these problems, the protective layer is deposited by sputtering to have an operating temperature of less than about 150 degrees C.

When the protective layer second material layer 250 is deposited by a sputtering method having a temperature lower than the first to fourth patterned photoresists 282, 284, 286, 288, the first to fourth patterned photoresists are not 282, 284, 286, 288 produced damage. Second, the second material layer 250 can be deposited on a reproducible substrate, such as a plastic substrate.

Next, as shown in FIG. 8D, a lift-off process is performed on the substrate 200 having the second material layer 250 and the first to fourth patterned photoresists 282, 284, 286, and 288 with a stripping liquid. Thus, the first to fourth patterned photoresists 282, 284, 286, 288 and the second material layer 250 thereon can be removed simultaneously. The second material layer remains thereon relative to the first and second trenches 273, 274 to form a patterned material 250.

In this embodiment, the first trench 273 and the second trench 274 may be arranged as shown in FIG. That is, each second trench 274 corresponds to a space between two adjacent first trenches 273. Therefore, the stripping liquid easily penetrates into the entire portions of the first to fourth patterned photoresists 282, 284, 286, and 288. That is, since the first and second grooves 273, 274 are arranged as shown in Fig. 7, the characteristics of the peeling process can be improved. Secondly, since the material layer on the patterned photoresist is formed by a sputtering method, no damage occurs in the peeling method.

Figure 9 is an enlarged schematic view of a portion I of Figure 7. As shown in Fig. 9, in the peeling process, the stripping liquid penetrates into the edge portions of the first and second grooves 273, 274 in the direction of the arrow (when the stripping liquid penetrates all the edges thereof), the arrow Pointed to the corners of the first and second grooves). Because the first and second trenches 273, 274 are alternately arranged, the first to fourth patterned photoresists 282, 284, 286, 288 and the second material layer of each region of the line 270 can be easily removed in the stripping process. Remove it.

Figures 4-9 show a schematic view of the first and second grooves being strip-shaped. However, it can also be in various other shapes. 10A-10F are schematic views of the grooves in the embodiment of the present invention. As noted above, line 370 in Figures 10A-10F is comprised of one of a signal line and a patterned metal having a line width greater than about 20 microns.

As shown in FIG. 10A, at least one groove 371 is disposed on the line 370. The groove 371 is serrated. As shown in FIG. 10B, the grooves 372 may be cross-shaped. The two intersecting lines are diagonal to each other. That is, the groove 372 may be an obtuse or acute angle at a portion where the two lines intersect. As shown in FIG. 10C, the groove 373 may have a cross shape. The lines of the grooves 373 intersect at a mutually perpendicular angle. As shown in FIG. 10D, the groove 374 includes first and second groove lines 374a, 374b, and the groove 374 is in the shape of a weathercock shape. That is, the first and second groove lines 374a, 374b intersect at a mutually perpendicular angle and are spaced apart from each other perpendicularly on the extension lines of the first and second groove lines 374a, 374b. As shown in FIG. 10E, the groove 375 has a retaining wall which is patterned and has an opening. As shown in Figure 10F, the trench 376 is a diamond shape. In other embodiments, the grooves may be one of a triangle, a square, or other shape. The trench is formed on a line having a relatively large line width to improve characteristics in the lift-off process. The trenches are arranged in an island shape to maintain the electrical properties of the wires. The line may be one of a gate pad, a data pad, an MPS line, an electrostatic protection circuit line, or a dummy line.

Since the peeling liquid used in the peeling process can easily penetrate into the patterned photoresist through the groove, there is no problem in the peeling process. Moreover, since the material layer is deposited on the patterned photoresist by a sputtering method having a relatively low temperature, damage to the patterned photoresist can be avoided.

Next, a method of manufacturing an array substrate of a liquid crystal display by the above-described lift-off process will be described in detail.

Figure 11 is a plan view showing an array substrate of a liquid crystal display device in an embodiment of the present invention. Fig. 12A-12F is a schematic diagram of a part of the cross-sectional structure process along line XII-XII of Fig. 11. Figure 13A-13F is a schematic diagram of a part of the cross-sectional structure process along line XIII-XIII of Figure 11. Figure 14A-14F is a schematic diagram of the process of the section along the line XIIV-XIIV of Figure 11.

As shown in FIG. 11, the substrate 410 of the liquid crystal display includes a display area and a non-display area. The non-display area is disposed around the display area of the pixel area P. As shown in Fig. 11, the non-display area has a plurality of portions, and each portion has at least one groove. Alternatively, each portion has a plurality of grooves and the two adjacent grooves are spaced apart from each other. The foregoing part may be a gate pad, a data pad, an MPS line, an electrostatic protection circuit line or a secondary One of a dummy line, a dummy area, a gate line, or a data line. In detail, the gate line 420 is formed on the substrate 410 of the array substrate 400. The data line 440 is traversed across the gate line 420 to define the pixel area P. The thin film transistor Tr includes a gate electrode 422, a semiconductor layer (not shown), a source electrode 442, and a drain electrode 444, and the thin film transistor Tr is formed on the pixel region P. The pixel electrode 460 is connected to the thin film transistor Tr and is also formed on the pixel region P. The gate electrode 422 and the source electrode 442 are connected to the gate line 420 and the data line 440, respectively, and the drain electrode 444 is separated from the source electrode 442. The pixel electrode 460 covers the patterned metal 448 and covers the gate line 420 to form a storage capacitor Cst. The patterned metal 448 is electrically connected to one of the pixel electrode 460 and the gate line 420.

The gate pad 424 contacting the gate electrode (not shown) is disposed on one end of the gate line 420 through a gate pad contact hole (GPC); and the data of the contact pad (not shown) The pad 446 is disposed on one end of the data line 440. The gate pad 424 and the data pad 446 are disposed on the non-display area and are located around the display area of the pixel area P.

On the non-display area, first to fourth grooves HP1, HP2, HP3, and HP4 are formed. A first trench HP1 is formed on the first non-display region forming the gate pad 424, and a second trench HP2 is formed on the second non-display region forming the gate pad 424. On the third non-display area facing the second non-display area, a third groove HP3 is formed; on the fourth non-display area facing the first non-display area, a fourth groove HP4 is formed. Due to the first to fourth grooves HP1, HP2, HP3, HP4, part of the material layer can be easily removed in the stripping process The ground was removed. The pixel electrode 460 can be defined during the removal of a portion of the material layer. The first to fourth grooves HP1, HP2, HP3, HP4 may have shapes as shown in Figs. 4, 7, and 10A-10F.

The array substrate was prepared in the following process. 12A-12F is a schematic view of a pixel region P having a switching region TrA of a thin film transistor. Figures 13A-13F are schematic diagrams showing the gate pad area GPA of the gate pad. Figure 14A-14F is a schematic diagram of the data pad area DPA forming the data pad.

As shown in Figures 12A, 13A and 14D, the first mask process is performed on the substrate using at least one of copper (Cu), molybdenum (Mo), titanium-molybdenum alloy (Mo-Ti), aluminum (Al), A first metal layer (not shown) is deposited on the aluminum alloy or chromium (Cr). The first metal layer is patterned to form a gate line (not shown), a gate electrode 422 extending from the gate line to the switching region TrA, and a gate pad 424 connecting the gate line to the gate pad region GPA. Next, on the substrate including the gate line, the gate electrode 422 and the gate pad 424, a gate insulating layer 426 made of tantalum oxide or tantalum nitride is formed.

As shown in Figures 12B, 13B and 14B, the second mask process is shown. As shown in FIGS. 12B, 13B and 14B, an intrinsic amorphous germanium layer 428, an impurity doped amorphous germanium layer 430 and a second metal layer 432 are sequentially formed on the gate insulating layer 426. The second metal layer 432 may be copper (Cu), molybdenum (Mo), titanium-molybdenum alloy (Mo-Ti), aluminum (Al), aluminum alloy, or chromium (Cr). A first photoresist layer 480 is formed on the second metal layer 432. Then, a mask having a transparent region TA, a half-transmissive area (HTA), and a barrier region BA is disposed on the first photoresist layer 480. Curtain M. Translucent area HTA The transmittance is smaller than the transmittance of the transparent region TA, but larger than the barrier region BA. The half-transmissive area (HTA) corresponds to the middle portion of the gate electrode 422 and the two sides of the gate pad 424. The barrier area BA corresponds to both sides of the gate electrode 422 and the data pad, and the translucent area HTA It corresponds to other parts. The first photoresist layer 480 is exposed and developed through the mask M.

Therefore, as shown in FIGS. 12C, 13C and 14C, the first pattern drawing photoresist 482a corresponding to the barrier area BA has a first height, and the second pattern drawing photoresist 482b corresponding to the translucent area HTA has a second height. And the second height is less than the first height. In other words, the first photoresist layer 480 corresponding to the transparent region TA can be preferably removed to expose a portion of the second metal layer 432. Then, using the first and second photoresists 482a, 482b as patterned masks, sequentially exposing the exposed second metal layer 432 and the impurity-doped amorphous germanium layer 430 underneath, the intrinsic amorphous germanium layer 428 and gate insulating layer 426. Therefore, the substrate 410 corresponding to the portion of the pixel region P is exposed, and the gate pad 424 is also exposed through the gate pad contact hole GPC. A data pad 446 is formed from the second metal layer 432 on the data pad area DPA. Furthermore, a patterned metal material 432a, an impurity doped amorphous germanium layer 430 and an intrinsic amorphous germanium layer 428 are formed.

Subsequently, as shown in FIGS. 12D, 13D and 14D, ashing is performed on the first and second patterned photoresists 482a, 482b to remove the second patterned photoresist 482b and patterned from the first The photoresist 482a first forms a three-patterned photoresist 482c. The third patterned photoresist 482c has a higher height than the first patterned photoresist 482a (as shown in Figures 12C and 14C). Removing the exposed metal material layer 432a from the patterned impurity underneath The amorphous germanium 432a is doped to expose a portion of the patterned intrinsic amorphous germanium 428a. Therefore, the source electrode 442 and the drain electrode 444 spaced apart therefrom are formed on the patterned metal material 432a. The amorphous germanium 432a is doped from the patterned impurity to form the ohmic contact layer 434b. A patterned intrinsic amorphous germanium 428a between source electrode 442 and drain electrode 444 is exposed to define an active layer 434a. The gate electrode 422, the gate insulating layer 426, the semiconductor layer 434 including the active layer 434a and the ohmic contact layer 434b, the source electrode 442, and the drain electrode 444 form a transistor Tr in the switching region TrA.

As shown in Figures 12E-12F, 13E-13F and 14E-14F, it is a third mask process. As shown in FIGS. 12E, 13E, and 14E, the third patterned photoresist 482c is removed, and then an insulating material layer and a fourth patterned photoresist 484 are formed on the insulating material layer (not shown). The fourth patterned photoresist 484 corresponds to the boundary between the switching region TrA and the gate pad 424. In the cross-sectional view, the fourth patterned photoresist 484 in the gate pad region GPA is spaced apart from each other. A fourth patterned photoresist 484 in the switching region Tr exposes a portion of the drain electrode 444. A space between the adjacent two fourth patterned photoresists 484 in the gate pad region GPA defines a first trench HP1. In addition, a fourth patterned photoresist 484 is formed on the data pad 446. The fourth patterned photoresist 484 on the data pad 446 corresponds to the middle of the data pad 446 and its two sides. A space between adjacent two fourth patterned photoresists 484 defines a second trench HP2. In the figure, some of the fourth patterned photoresists appear to be separated from each other. However, the first and second trenches HP1, HP2 correspond to the holes in the fourth patterned photoresist 484, such that the fourth pattern in each region The photoresist 484 is a complete body.

Although not shown, in the non-display area facing the data pad area DPA and the gate pad area GPA, there are still other fourth patterns, so that the third and fourth grooves can be respectively defined in the non-display area. groove.

Subsequently, with the fourth patterned photoresist 484 as a mask, the protective layer 450 is formed by patterning a layer of insulating material (not shown). In this embodiment, the insulating material layer (not shown) is over-etched, such that the ends of the fourth patterned photoresist protrude from the protective layer 450. That is to say, the line width of the fourth patterned photoresist 484 is larger than the line width of the protective layer 450. It may be an undercut structure.

Subsequently, a transparent conductive material layer 452 is deposited on the fourth patterned photoresist 484 and the protective layer 450 using a transparent conductive material such as ITO or IZO. As described above, since the trailing end of the fourth patterned material 484 protrudes from the protective layer 450, there is a discontinuous layer of transparent conductive material 452 around the fourth patterned photoresist 484 and the protective layer 450. When the transparent conductive material layer 452 is deposited by plasma chemical vapor deposition at a temperature higher than 350 C, the fourth patterned photoresist 484 is damaged, thereby causing defects in the stripping process. Therefore, the transparent conductive material layer 452 is formed by a sputtering method having a temperature of less than 150 degrees C.

Thereafter, a stripping process is performed with a stripper. The stripping solution penetrates into the fourth patterned photoresist through the discontinuous structure of the transparent conductive material layer, so that the fourth patterned photoresist 484 and the transparent conductive material layer 452 located thereon can be removed. In this embodiment, the first and second grooves HP1, HP2 and the third and fourth A trench (not shown) activates the strip process. In particular, the fourth patterned photoresist 484 in the non-display area has a line width greater than about 200 microns. Therefore, if the fourth patterned photoresist 484 and the transparent conductive material layer 452 located thereon can be removed by the prior art stripping method, the fourth patterned photoresist 484 and the transparent conductive material layer 452 located thereon Cannot be completely removed. However, due to the first and second grooves HP1, HP2 and the third and fourth grooves (not shown) of the present invention, the problems caused by the peeling method of the prior art can be solved.

Due to the lift-off process, as shown in FIGS. 12F, 13F, and 14F, the pixel electrode 460 connected to the drain electrode 444 is formed in the pixel region P. The gate pad electrode 462, which is connected to the gate pad contact hole G424 and connected to the gate pad 424, is formed on the gate pad contact hole GPC, and is connected to the data pad electrode of the data pad 446 and corresponds to the second trench HP2. Formed in the data pad area DPA. Further, the transparent conductive material layer 452 with respect to the first trench HP1 remains to form an island-shaped first peeling pattern 452a. Although not shown, the residual transparent conductive material layer 452 forms a fourth peeling pattern having an island shape, and is formed on the data pad 446 and the non-display surface facing the data pad area DPA and the gate pad area GPA. Around the area.

The array substrate of the liquid crystal display is prepared by the above method and comprises the stripping process of the present invention.

Next, a method of preparing an array substrate of a liquid crystal display according to another embodiment of the present invention, which also uses the aforementioned stripping method. The component symbols used in this embodiment are similar to the 12A-12H, 13A-13H, and 14A-14H diagrams of the previous embodiment. Briefly described below.

15A-15H is a schematic cross-sectional view showing a method of manufacturing a pixel region having a switching region in this embodiment of the present invention. 16A-16H are cross-sectional views showing a method of fabricating a gate pad region in this embodiment of the present invention. 17A-17H is a schematic cross-sectional view showing a method of manufacturing a data pad region in this embodiment of the present invention.

As shown in FIGS. 15A, 16A and 17A, for the first mask process, a first metal layer (not shown) is formed on the substrate 510. The first metal layer is patterned to form a gate line (not shown), a gate 524 electrode 522 extending from the gate line to the switching region TrA, and a gate pad 524 connecting the gate line to the gate pad GPA. . Next, a gate insulating layer 526 is formed on the substrate including the gate line, the gate electrode 522, and the gate pad 524.

The second mask process is shown in Figures 15B-15D, 16B-16D and 17B-17D. As shown in FIGS. 15B, 16B and 17B, an intrinsic amorphous germanium layer 528, an impurity doped amorphous germanium layer 530 and a second metal layer 532 are sequentially formed on the gate insulating layer 526. Forming a first photoresist layer 580 on the second metal layer 532, and then patterning the first photoresist layer 580 with a mask having a transparent region, a half-transmissive area, and a barrier region, to First and second patterned photoresists 582a, 582b having different heights are formed.

Subsequently, as shown in FIGS. 15C, 16C and 17C, the first and second photoresists 582a, 582b are used as patterned masks, and the second metal layer 532, the impurity-doped amorphous germanium layer 530, and the essence are sequentially patterned. An amorphous germanium layer 528 and a gate insulating layer 526. Next, an ashing process is performed to form a third patterned photoresist 582c. Third patterned photoresist The exposed second metal layer 532, the impurity doped amorphous germanium layer 530, and the intrinsic amorphous germanium layer 528 are patterned by the third patterned photoresist 582c to form a pattern on both sides of the gate pad 524. The metal 532a, the patterned impurity doped amorphous germanium 530a, and the patterned amorphous amorphous germanium 528a.

Therefore, as shown in FIGS. 15D, 16D, and 17D, the patterned intrinsic amorphous germanium 528a, the patterned impurity doped amorphous germanium 530a, and the patterned metal 532a are stacked on the switching region TrA, and the patterned amorphous germanium 528a, The patterned impurity doped amorphous germanium 530a and the data pad 546 are stacked on the data pad region DPA.

As shown in Figures 15E-15H, 16E-16H and 17E-17H, it is a third mask process. As shown in FIGS. 15E, 16E, and 17E, a transparent conductive material layer 552 is formed, and fourth and fifth patterned materials 584a, 584b having different heights are formed on the transparent conductive material layer 552.

Subsequently, as shown in FIGS. 15F, 16F and 17F, the transparent conductive material layer 552, the patterned metal material 532a and the patterned impurity doped amorphous germanium 530a are performed by the fourth and fifth patterned photoresists 584a, 584b. The patterning is performed to form a source electrode 542, a drain electrode 544, a source contact layer 543b under the source electrode 542 and the drain electrode 544, and an active layer 534a. The gate electrode 522, the gate insulating layer 526, the semiconductor layer 534 including the ohmic contact layer 534b and the active layer 534a, the source electrode 542, and the drain electrode 544 form a transistor Tr in the switching region TrA. Thereafter, a sixth patterned photoresist 584c is formed from the fourth patterned photoresist 584a using an ashing process. On the gate pad 524, a space between the sixth patterned photoresist 584c defines a first trench The HP1, on the data pad 526, defines a second trench HP2 in the space between the sixth patterned photoresist 584c. In the figure, a portion of the sixth patterned photoresist 584c appears to be spaced apart from each other. However, the first and second trenches HP1, HP2 correspond to the holes of the sixth patterned photoresist 584c, such that the sixth patterned photoresist 584c in each region is a complete body. The transparent conductive material layer 552 is patterned by the sixth patterned photoresist 584c to form a pixel electrode 560 connecting the drain electrode 544, the patterned transparent conductive material 552a on the gate pad 524, and the data pad 546. In this embodiment, since the transparent conductive material layer 552 is over-etched, the sixth patterned photoresist 584c protrudes from the trailing end of the patterned transparent conductive material 552a.

Thereafter, as shown in FIGS. 15G, 16G, and 17G, a protective layer is formed by tantalum nitride or hafnium oxide by a sputtering method. In general, the protective layer in a liquid crystal display is formed by plasma chemical vapor deposition to deposit an inorganic insulating material. However, because the plasma chemical vapor deposition method requires a relatively high temperature, for example, above 350 degrees C, damage is caused to the sixth patterned photoresist 584c. Therefore, the protective layer 550 is formed by a sputtering method having a temperature of less than 150 degrees C.

Since the protective layer 550 around the pixel electrode 560 and the sixth patterned photoresist 584c and between the patterned transparent conductive material 552a and the sixth patterned photoresist 584c are discontinuous, in the stripping method The stripper penetrates into the sixth patterned photoresist 584c through the discontinuous structure. Therefore, the sixth patterned photoresist 584c and the protective layer 550 located thereon can be simultaneously removed. In particular, due to the first and second trenches HP1, HP2, the stripping method has a large influence on the gate pad 524 and the data pad 546, Its line width is greater than about 200 microns.

As shown in Figures 15H, 16H and 17H, the protective layer 550 in the switching region TrA covers and protects the exposed portion of the active layer 534a. The protective layer 550 opposite to the first and second trenches HP1, HP2 remains on the gate pad region GPA. The gate pad electrode 562 is disposed between the first trenches HP1 and is formed of a transparent conductive material and a contact pad pad 524. In the case, the protective layer 550 of the second trench HP2 remains in the self-pad area DPA. The data pad electrode 564 is disposed between the second trenches HP2, and is formed of a transparent conductive material to contact the data pad 546.

When a line or pattern is formed with a relatively large line width by the stripping method of the present invention, for example, about 200 μm or more, problems such as residual patterned photoresist are prevented by a plurality of grooves.

Furthermore, since the material layer provided on the patterned photoresist is formed by a sputtering method having a relatively low temperature, the patterned photoresist is not damaged.

Furthermore, the array substrate of the liquid crystal display prepared by the stripping method has better quality.

While the present invention has been described above in the foregoing embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of patent protection shall be subject to the definition of the scope of the patent application attached to this specification.

10, 100, 200‧‧‧ array substrate, substrate

145‧‧‧Brake insulation

152, 156‧‧‧ patterned protection, protective layer

150, 250‧‧‧ second material layer

158‧‧‧Second patterned material

Lines 170, 270, 370‧‧

170a, 270a‧‧‧ first patterned line

170b, 270b‧‧‧ second patterned line

170c, 270c‧‧‧ third patterned line

270d‧‧‧fourth patterned line

172, 273‧‧‧ first trench

174, 274‧‧‧ second trench

175, 260‧‧‧ first material layer

180, 280‧‧ ‧ photoresist layer

182, 282, 482a, 582a‧‧‧ first patterned photoresist

184, 284, 482a, 582b‧‧‧ second patterned photoresist

186, 286, 482c, 582c‧‧‧ third patterned photoresist

288, 584a‧‧‧ fourth patterned photoresist

584b‧‧‧ fifth patterned photoresist

584c‧‧‧ sixth patterned photoresist

190’280‧‧ ‧ curtain

20, 420‧‧ ‧ gate line

30, 440‧‧‧ data line

371~376‧‧‧ trench

374a‧‧‧First groove line

374b‧‧‧Second groove line

400‧‧‧Array substrate

410‧‧‧Substrate

42, 424, 524‧‧ ‧ gate pads

426, 526‧‧ ‧ brake insulation

422, 522‧‧ ‧ gate electrode

428, 528‧‧‧ Essential amorphous layer

428a, 528a‧‧‧ patterned essentially amorphous

430, 530‧‧‧ impurity doped amorphous layer

430a, 530a‧‧‧ patterned impurities doped with amorphous germanium

432, 532‧‧‧ second metal layer

432a‧‧‧patterned metal materials

434a, 534a‧‧‧ active layer

434b, 543b‧‧‧ 殴m contact layer

44, 446, 546‧‧‧ data pad

442, 542‧‧‧ source electrode

444, 544‧‧‧汲electrode

448‧‧‧patterned metal

45, 526‧‧ ‧ brake insulation

450, 550‧‧ ‧ protective layer

452, 552‧‧‧ Transparent conductive material layer

452a‧‧‧First stripping patterning

552a‧‧‧patterned transparent conductive material

460, 560‧ ‧ pixel electrodes

462‧‧‧Gate pole electrode

480, 580‧‧‧ first photoresist layer

484‧‧‧ Fourth patterned photoresist

50‧‧‧Shared line, film layer

510‧‧‧Substrate

534‧‧‧Semiconductor layer

532a‧‧‧patterned metal

552a‧‧‧patterned transparent conductive material

562‧‧‧ gate pad electrode

564‧‧‧data pad electrode

584a‧‧‧fourth patterned material

584b‧‧‧5 patterned materials

60‧‧‧metal layer

70‧‧‧Common cable, common line

82‧‧‧patterned photoresist

BA‧‧‧Block area

CMH‧‧ shared contact window

Cst‧‧‧ storage capacitor

D~F‧‧‧Parts

DR‧‧‧ display area

DPA‧‧‧data pad area

GPA‧‧‧ gate pad area

GPC‧‧‧Gate pad contact hole

HP1‧‧‧ first trench

HP2‧‧‧ second trench

HP3‧‧‧ third trench

HP4‧‧‧fourth groove

HTA‧‧‧translucent area

NDR‧‧‧ non-display area

M‧‧‧ mask

P‧‧‧Photo District

TA‧‧‧Transparent Zone

Tr‧‧‧thin film transistor, transistor

TrA‧‧ switch area

W‧‧‧Width

FIG. 1 is a schematic plan view of a conventional liquid crystal display array substrate.

Fig. 2 is a partially enlarged view of a portion A of Fig. 1.

Figure 3A-3C is a schematic view of the cross-sectional process along line III-III in Figure 2.

Figure 4 is a partial plan view showing a line containing a groove in an embodiment of the present invention.

Figure 5A-5C is a schematic view of the cross-section process along line V-V in Figure 4.

Fig. 6 is a plan enlarged view of a portion H in Fig. 4.

Figure 7 is a partial plan view showing a line having a groove in an embodiment of the present invention.

Figure 8, is a schematic view of the cross-sectional process along line VIII-VIII of Figure 7.

Figure 9 is an enlarged schematic view of a portion I of Figure 7.

10A-10F are schematic views of the grooves in the embodiment of the present invention.

Figure 11 is a plan view showing an array substrate of a liquid crystal display device in an embodiment of the present invention.

Fig. 12A-12F is a schematic diagram of a part of the cross-sectional structure process along line XII-XII of Fig. 11.

Figure 13A-13F is a schematic diagram of a part of the cross-sectional structure process along line XIII-XIII of Figure 11.

Figure 14A-14F is a schematic diagram of the process of the section along the line XIIV-XIIV of Figure 11.

15A-15H is a schematic cross-sectional view showing a method of manufacturing a pixel region having a switching region in this embodiment of the present invention.

16A-16H are cross-sectional views showing a method of fabricating a gate pad region in this embodiment of the present invention.

17A-17H is a schematic cross-sectional view showing a method of manufacturing a data pad region in this embodiment of the present invention.

400‧‧‧Array substrate

410‧‧‧Substrate

420‧‧ ‧ gate line

422‧‧‧gate electrode

424‧‧‧Gate pad

442‧‧‧ source electrode

444‧‧‧汲electrode

446‧‧‧Material pads

448‧‧‧patterned metal

460‧‧‧ pixel electrodes

Cst‧‧‧ storage capacitor

HP1‧‧‧ first trench

HP2‧‧‧ second trench

HP3‧‧‧ third trench

HP4‧‧‧fourth groove

GPC‧‧‧Gate pad contact hole

P‧‧‧Photo District

Tr‧‧‧thin film transistor, transistor

Claims (19)

A stripping method includes: forming a first material layer on a substrate; forming a patterned photoresist on the first material layer, the patterned photoresist comprising a plurality of first holes and a plurality of second holes; The patterned photoresist is patterned as a pattern mask to pattern the first material layer to form a patterned material having a plurality of first trenches and a plurality of second trenches, the first and second trenches respectively The width of the patterned photoresist is greater than the width of the patterned material between the first and second trenches; forming a second material layer having the patterned light Blocking a complete surface of the substrate of the first and second trenches; and removing the patterned photoresist and the second material layer on the patterned photoresist; wherein, the The patterned material between a portion of the first trench and the second trench is integrally formed with the patterned material at a portion of the first and second trench sides. The stripping method of claim 1, wherein each of the first and second grooves is selected from the group consisting of a strip, a zigzag, a cross, and a weathercock shape. The stripping method of claim 1, wherein the second material layer comprises at least one protective layer, a transparent conductive material layer and a metal conductive material layer. The stripping method of claim 1, wherein the step of forming the second material layer comprises precipitating the material by a sputtering method. The stripping method of claim 1, wherein the line has a line width greater than 200 microns. A method for fabricating an array substrate of a liquid crystal display, comprising: forming a gate line and a gate electrode on a substrate, the substrate having a display area and a first to fourth non-display area, the first to fourth non- The display area is located around the display area, and the gate electrode is disposed on the display area; forming a data line, a data pad, a semiconductor layer, a source electrode and a drain electrode on the substrate, the data line Interleaved with the gate line, the data pad is disposed at one end of the data line and on the first non-display area, the semiconductor layer is disposed on the gate electrode, and the source electrode is connected to the data line and is disposed On the semiconductor layer, the drain electrode is spaced apart from the source electrode region and disposed on the semiconductor layer; and a complete substrate of the substrate having the data line, the data pad, the source electrode and the drain electrode Forming an insulating material layer on the surface; forming a first patterned photoresist and a second patterned photoresist, the first patterned photoresist is opposite to the source and the drain electrode, and the second patterned photoresist Having a plurality of first and second holes The first patterned photoresist exposing a portion of the drain electrodes, the plurality of first and second holes, respectively first and second portions of the information should pad; Patterning the insulating material layer with the first and the second patterned photoresist as a pattern mask to form a protective layer and a first patterned protective layer, the protective layer exposing a portion of the drain electrode, The first patterned protective layer has a plurality of first and second trenches, the first and second trenches respectively exposing the first and second portions of the data pad; and having the first and the second Forming a conductive material layer on the entire surface of the substrate, the protective layer and the first patterned protective layer, the conductive material layer having a discontinuous structure; and simultaneously removing the The first and second patterned photoresists and the conductive material layer on the first and second patterned photoresists. The method for preparing an array substrate of a liquid crystal display according to claim 6, wherein the conductive material layer is a transparent conductive material or an opaque metal conductive material. The method for fabricating an array substrate of a liquid crystal display according to claim 6, wherein the step of forming the first and second patterned photoresists comprises forming a third patterned photoresist, the third patterned photoresist having a plurality of Third and fourth holes, the third and fourth holes respectively corresponding to the third and fourth portions of each of the second, third and fourth non-display regions; the patterned layer of insulating material The step includes forming a second patterned protective layer having a plurality of third and fourth trenches, the third and fourth trenches exposing the second, third, and fourth portions, respectively The third and fourth parts of the non-display area; The stripping step includes removing the third patterned photoresist and the transparent conductive material on the third patterned photoresist. The method of fabricating an array substrate of a liquid crystal display according to claim 8, wherein each of the first, second, third, and fourth grooves comprises a strip shape, a zigzag shape, a cross shape, and a weathercock shape. one. The method of fabricating an array substrate of a liquid crystal display according to claim 6, wherein each of the data pads and the second, third, and fourth non-display regions have a line width greater than 200 micrometers. A method for fabricating an array substrate of a liquid crystal display, comprising: forming a gate line and a gate pad on a substrate, wherein the gate pad is disposed at one end of the gate line; forming a gate insulating layer and an essence in sequence An amorphous germanium layer, an impurity doped amorphous germanium layer and a metal layer on a complete surface of the substrate, the substrate comprising the gate line and the gate pad; patterning the metal layer, the impurity doping An amorphous germanium layer, the intrinsic amorphous germanium layer and the gate insulating layer to expose the gate pad and form a data line interlaced with the gate line, thereby defining a pixel region and one end of the data line a data pad; forming a conductive material layer on the substrate having the data line and the complete surface of the data pad; forming a first pattern drawing photoresist and a second pattern drawing photoresist, the pattern drawing photoresist comprises a plurality of First and second holes, the second pattern drawing photoresist comprises a plurality of Third and fourth holes, the first and second holes respectively corresponding to the first and second portions of the gate pad, and the third and fourth holes respectively correspond to the third and fourth portions of the data pad And patterning the conductive material layer with the first and second patterned photoresists as a mask to form a first patterned conductive material and a second patterned conductive material, the first patterned conductive material having a plurality of first and second trenches, the second patterned conductive material having a plurality of third and fourth trenches, the first and second trenches respectively exposing the first and second gates of the gate pad a portion of the third and fourth trenches respectively exposing the third and fourth portions of the data pad; and having the first, the second patterned photoresist and the first, the second, the third Forming a protective layer on a complete surface of the substrate with the fourth trench, the protective layer having a discontinuous structure; and removing the first, the second patterned photoresist and located in a stripping process The first, the second patterned photoresist is on the protective layer. The method for preparing an array substrate of a liquid crystal display according to claim 11, wherein the conductive material layer is a transparent conductive material or an opaque metal conductive material. The method for fabricating an array substrate of a liquid crystal display according to claim 11, wherein the step of forming the gate line and the gate electrode comprises forming a gate electrode connecting the gate line; patterning the metal layer, the impurity The step of doping the amorphous germanium layer, the intrinsic amorphous germanium layer and the gate insulating layer comprises forming a patterned intrinsic amorphous germanium, a patterning An impurity doped amorphous germanium and a patterned metal layer are stacked on the gate electrode; and the step of patterning the conductive material layer includes removing the exposed patterned metal and a portion of the patterned impurity doped amorphous germanium, And forming a pixel electrode in the pixel region, and connecting a portion of the patterned metal; and removing the first and second patterned photoresist and the protective layer comprises removing the third pattern The photoresist and the protective layer on the third patterned photoresist layer. The method of fabricating an array substrate of a liquid crystal display according to claim 11, wherein each of the first, second, third, and fourth grooves comprises a strip shape, a zigzag shape, a cross shape, and a weathercock shape. one. The method of fabricating an array substrate of a liquid crystal display according to claim 11, wherein each of the gate pads and the data pad has a line width greater than 200 microns. The method of fabricating an array substrate of a liquid crystal display according to claim 15, wherein the step of forming the protective layer comprises using a sputtering method. A liquid crystal display comprising: a substrate comprising a display area and a non-display area, the non-display area having a plurality of portions, each of the portions having at least one trench, wherein one of the portions is a gate pad , data pad, MPS line, electrostatic protection circuit line, dummy line, dummy area or gate line. The liquid crystal display according to claim 17, wherein the trenches are filled with a material which is a transparent conductive material, an opaque metal conductive material or a protective material. The liquid crystal display of claim 17, wherein one of the portions has a plurality of grooves, and the two adjacent grooves are spaced apart from each other.