KR101072379B1 - Method of lift-off and fabricating array substrate for liquid crystal display device using the same - Google Patents

Method of lift-off and fabricating array substrate for liquid crystal display device using the same Download PDF

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KR101072379B1
KR101072379B1 KR1020080046998A KR20080046998A KR101072379B1 KR 101072379 B1 KR101072379 B1 KR 101072379B1 KR 1020080046998 A KR1020080046998 A KR 1020080046998A KR 20080046998 A KR20080046998 A KR 20080046998A KR 101072379 B1 KR101072379 B1 KR 101072379B1
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pattern
material layer
forming
layer
gate
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KR1020080046998A
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Korean (ko)
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KR20090009697A (en
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임주수
김홍식
곽희영
홍현석
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엘지디스플레이 주식회사
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Priority claimed from US12/219,306 external-priority patent/US7988871B2/en
Publication of KR20090009697A publication Critical patent/KR20090009697A/en
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Abstract

The present invention relates to a lift-off method and a manufacturing method of an array substrate for a liquid crystal display device using the same, and more particularly, to improve a lift-off process characteristic for a large area pattern.
To this end, the present invention is to form a groove pattern for the smooth penetration of the stripper used in the lift-off process for the large area pattern, to prevent defects due to the photoresist pattern remaining after the lift-off process.
In addition, in the present invention, by depositing the target material layer of the lift-off process by sputtering method capable of low temperature deposition on the photoresist pattern, damage to the photoresist pattern is prevented, thereby improving the lift-off process characteristics and the quality of the liquid crystal display device. You can.

Description

Lift-off method and manufacturing method of array substrate for liquid crystal display using same {Method of lift-off and fabricating array substrate for liquid crystal display device using the same}

The present invention relates to a liquid crystal display device, and more particularly, to a lift-off method including a large area photoresist pattern and a method of manufacturing an array substrate for a liquid crystal display device using the same.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display (AM-LCD) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has been attracting the most attention because of its excellent resolution and ability to implement video.

Hereinafter, a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1 is a plan view showing a conventional array substrate for a liquid crystal display device, and relates to a transverse electric field type liquid crystal display device array substrate in which a pixel electrode and a common electrode are formed on the same plane.

As illustrated, a conventional array substrate 10 for a liquid crystal display device is divided into a display area DR and a non-display area NDR, and the display area DR may change an arrangement of liquid crystal molecules (not shown). This is the part that actually displays the desired image.

In this case, the plurality of gate lines 20 and the data lines 30 intersect vertically and horizontally on the array substrate 10 to define pixels in a matrix form. In addition, the plurality of common wires 50 spaced apart from each other in parallel with the gate wire 20 receive a common signal through the common connection wire 70 corresponding to the non-display area NDR.

In this case, when the common connection line 70 corresponding to the non-display area NDR is formed on the same layer as the gate line 20, a short occurs, so that the common connection line 70 is connected to the data line ( It is formed on the same layer as 30), and is configured to be connected to the common wiring 50 through a plurality of common contact holes (CMH).

A pixel electrode (not shown) and a common electrode (not shown) correspond to each of these pixels one-to-one, and a gate electrode extending from the gate line 20 is formed at an intersection of the gate line 20 and the data line 30. A thin film transistor T including a source electrode (not shown) extending from the data line 30 and a drain electrode spaced apart from the source electrode (not shown) is configured.

A plurality of gate pad electrodes 42 and data pad electrodes 44 are formed at one end of the gate lines 20 and the data lines 30, respectively. In this case, the gate and data pad electrodes 42 and 44 are respectively mounted on the gate and the data driver (not shown) through the gate and the data TCP (tape carrier package, not shown).

Although not shown in detail in the drawings, an antistatic circuit wiring (not shown) and various signal wirings may be further included to prevent the generation of static electricity corresponding to the non-display area NDR.

In this case, the common connection line 70 transfers a common signal from a common signal generation unit (not shown) to a plurality of common wires 50 corresponding to the display area DR. The area 70 is generally configured to have a larger area than the common line 50 branched into the display area DR.

However, various signal wirings including the aforementioned common connection wiring 70 (gate and data pad electrodes 42 and 44, antistatic circuit wiring (not shown), and MPS (Multi Pattern Search) wiring for determining the presence or absence of a short circuit And dummy wirings (not shown), etc., do not easily penetrate the stripper to the central portion of various signal lines designed in a large area during the lift-off process, which is a core process of the three mask process. It is an obstacle to the reduction.

This will be described in detail with reference to the accompanying drawings.

2 is an enlarged plan view of a portion A of FIG. 1, and FIGS. 3A to 3C are cross-sectional views illustrating a manufacturing process of a portion cut along the line III-III of FIG. 2. 2 and 3A to 3C show a common connection wiring, but this is only an example, and the above problems are the gate pad electrode, the data pad electrode, the antistatic circuit wiring, the MPS wiring, and the dummy formed in the non-display area. It occurs in various signal wirings and metal patterns such as wiring. Hereinafter, the above-mentioned signal wiring and metal pattern are collectively called wiring.

As shown in FIG. 2, in the case of the wiring 70 in which the lift-off process is performed, since the stripper used in the lift-off process is easily penetrated at the edge portions D and E of the wiring, all the photosensitive patterns are removed. It becomes a state. However, it is difficult for the stripper to penetrate into the central portion F of the wiring 70, so that after the lift-off process, the photosensitive pattern and the layer of material stacked thereon are not completely removed, which causes later process failure or direct This affects the display quality. This is more problematic in the case where the wiring 70 is wide.

Looking at the problem of the lift-off process in detail, first as shown in Figure 3a, to form a gate insulating film 45 on the substrate (10). In this case, the metal layer 60 is formed on the gate insulating layer 45 in the non-display area NDR of the substrate, and the photosensitive pattern 82 is formed to correspond to a part of the metal layer 60.

Next, as shown in FIG. 3B, the metal layer (60 in FIG. 3A) is etched using the photosensitive pattern 82 as an etching (etch) mask, thereby forming the wiring 70 and forming the gate insulating film 45. Expose some. In this case, the metal layer 60 (in FIG. 3A) is over-etched, so that the width of the photosensitive pattern 82 is greater than the width of the wiring 70. Next, a material layer 50, such as a protective layer, is formed on the photosensitive pattern 82 and the exposed gate insulating layer 45.

As described above, since the photosensitive pattern 82 has a width larger than that of the wiring 70 due to overetching of the metal layer 60 of FIG. 3A, the material layer 50 formed thereon is exposed to the photosensitive layer. A disconnection phenomenon occurs at the boundary between the pattern 82 and the wiring 70.

Next, as shown in FIG. 3C, when the stripper is penetrated into the break portion of the material layer 50 of FIG. 3B and the photosensitive pattern 82 of FIG. 3B is removed, the liftoff process is performed. The photosensitive pattern (82 in FIG. 3B) and the material layer (50 in FIG. 3B) thereon are simultaneously removed. At this time, the stripper easily penetrates the edges D and E of the wiring 70 so that the photosensitive pattern 82 of FIG. 3B and the material layer 50 of FIG. 3B are removed. However, since the penetration of the stripper into the central portion F is not easy, all of the photosensitive patterns 82 of FIG. 3B are not removed and the photosensitive material pattern 84 remains, causing a failure.

On the other hand, if a material layer constituting the pixel electrode remains in a neighboring non-display area facing the gate pad and the data pad, the display quality may be degraded due to short circuit between adjacent pixels or corrosion of the material layer. It must be removed. However, since the area is wide, during the liftoff process, the pixel electrode material layer is left together with the photosensitive pattern, so that the problem of deterioration of display quality remains.

The present invention has been made to solve the above-described problem, to facilitate the penetration of the stripper to the center portion in the large-area lift-off process, to prevent defects due to the remaining of the photosensitive material.

In addition, by using the lift-off process with improved characteristics, it is intended to simplify the manufacturing process of the array substrate for a liquid crystal display device.

In order to achieve the above object, the present invention comprises the steps of forming a first material layer on the substrate; Forming a photoresist pattern on the first material layer, the photoresist pattern having first and second holes corresponding to the first material layer; Patterning the first material layer using the photoresist pattern as a mask to form first and second groove patterns corresponding to the first and second holes in the material pattern and the material pattern; Forming a second material layer on the first and second groove patterns and the photoresist pattern; And simultaneously removing the photoresist pattern and the second layer of material thereon.

The present invention also provides a display area, a gate wiring extending in one direction on a substrate on which first, second, third, and fourth non-display areas are defined around the display area, and connecting the gate wiring to the display area. Forming a gate electrode; A data line crossing the gate line, a data pad connected to the data line and positioned in the first non-display area, a semiconductor layer on the gate electrode, and a source electrode and a drain spaced apart from each other on the semiconductor layer. Forming an electrode; Forming an insulating material layer on an entire surface of the substrate including the data line, the data pad, the source electrode, and the drain electrode; A first photoresist pattern corresponding to the source and drain electrodes on the insulating material layer, and first and second holes corresponding to the data pads and corresponding to the first and second regions of the data pads; Forming a photoresist pattern; Patterning the insulating material layer using the first and second photoresist patterns to expose a portion of the drain electrode, and first and second portions to expose each of the first and second regions of the data pad. Forming a second groove pattern; Forming a transparent conductive material layer on an entire surface of the substrate on which the exposed drain electrode, the first and second groove patterns, and the first and second photoresist patterns are formed; A method of manufacturing an array substrate for a liquid crystal display device, the method comprising simultaneously removing the first and second photoresist patterns and the transparent conductive material layer thereon by a lift-off process.

In addition, the present invention includes the steps of forming a gate wiring extending in one direction on the substrate, and a gate pad at one end of the gate wiring; Forming a gate insulating film, a pure amorphous silicon layer, an impurity amorphous silicon layer, and a metal material layer on an entire surface of the substrate including the gate wiring and the gate pad; Patterning the metal material layer, the impurity amorphous silicon layer, the pure amorphous silicon layer, and the gate insulating film sequentially to define a data line crossing the gate line to define a pixel region, and a data pad positioned at one end of the data line. Forming and exposing the gate pads; Forming a transparent conductive material layer on an entire surface of the substrate including the data line and the data pad; A first photoresist pattern having first and second holes corresponding to the first and second regions of the gate pad and corresponding to the first and second regions of the data pad on the transparent conductive material layer; Forming a second photoresist pattern having third and fourth holes; Patterning the transparent conductive material layer using the first and second photoresist patterns to thereby expose the gate pads corresponding to the first and second holes, and the third and third groove patterns. Forming third and fourth groove patterns exposing the data pads corresponding to fourth holes; Forming a protective layer on an entire surface of the substrate on which the first to fourth groove patterns and the first and second photoresist patterns are formed; A method of manufacturing an array substrate for a liquid crystal display device, the method comprising: simultaneously removing the first and second photoresist patterns and the protective layer thereon by a lift-off process.

First, when the lift-off process is performed using a photoresist pattern having a large width, a groove pattern is formed in the photoresist pattern to facilitate penetration of the stripper, thereby preventing defects occurring in the lift-off process. do.

Second, when the lift-off process is performed, a protective layer or the like is formed on a photoresist pattern having a heat resistance of about 150 ° C. by using a sputtering method, which is a low temperature process, thereby preventing the photoresist pattern from being damaged. To improve.

Third, by manufacturing the array substrate for the liquid crystal display device using the lift-off process and improving the lift-off process characteristics using the groove pattern, the display quality and the yield can be improved, and the manufacturing time and the manufacturing cost can be reduced. .

As a part of solving the above-described problem, a method of improving the lift-off process by forming groove patterns on various wirings will be described in detail with reference to the accompanying drawings.

First Embodiment

4 is a plan view showing a part of a wiring including a groove pattern according to the present invention, and FIGS. 5A to 5C are cross-sectional views illustrating a cross section taken along the line VV of FIG. 4 according to a process sequence.

First, as shown in FIG. 4, the first groove pattern 172 and the second groove pattern 174 are formed on the wiring 170. Each of the first and second groove patterns 172 and 174 has a bar shape (or a square pattern). The wiring 170 includes all wirings and metal patterns having relatively large widths, such as a common connection wiring, a gate pad electrode, a data pad electrode, an antistatic circuit wiring, an MPS wiring, and a dummy wiring. In this case, the width W of the wiring 170 is 200 μm or more. The plurality of first groove patterns 172 are spaced apart from each other in a first column on the wiring 170. In addition, the plurality of second groove patterns 174 are spaced apart from each other in a second column on the wiring 170. In this case, all of the passivation pattern (or photosensitive pattern) in the center portion are removed, but the passivation layer patterns 152 and 156 remain in the non-facing portions of the first and second groove patterns 172 and 174, which are lifted off. The process is described in detail with reference to FIGS. 5A to 5C.

Referring to FIG. 5A, after forming the first material layer 175 on the substrate 100, a photoresist is applied to form the photosensitive layer 180. In this case, a gate insulating layer (not shown) including one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride may be formed between the first material layer 175 and the substrate 100 according to the object of the process. .

In this case, the first material layer 175 may include a first metal layer (not shown) and copper (Cu) formed of one selected from a group of transparent conductive metals such as indium tin oxide (ITO) or indium zinc oxide (IZO). ) Or a second metal layer formed of one or more selected from the group of conductive metals such as molybdenum (Mo), molybdenum alloy (MoTi), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr), or It may be composed of only one of the first and second metal layers.

Next, the mask 190 including the transmission part TA and the blocking part BA is aligned on the substrate 100 including the first material layer 175 and the photosensitive layer 180. The transmission part TA and the blocking part BA are repeatedly configured regularly.

In this case, a halftone mask including a transmissive part TA, a blocking part BA, and a transflective part (not shown) may be applied according to process conditions.

Next, as shown in FIG. 5B, when the process of exposing and developing the mask 100 (190 of FIG. 5A) toward the substrate 100 is performed, the photosensitive layer corresponding to the transmission part (TA of FIG. 5A) is formed. 5A, all of the first material layer 175 of FIG. 5A is exposed, and the photosensitive layer 180 (FIG. 5A) corresponding to the blocking part BA of FIG. 5A is exposed. As such, the first to third photosensitive patterns 182, 184, and 186 remain respectively.

By using the first to third photosensitive patterns 182 to 186 as a mask to pattern the exposed first material layer 175 of FIG. 5A, the first to third wiring patterns 170a, 170b and 170c are formed. In this case, the exposed first material layer 175 of FIG. 5A is removed to form first and second groove patterns 172 and 174 between the first to third wiring patterns 170a, 170b and 170c. End portions of the first to third wiring patterns 170a, 170b, and 170c are connected to each other to form a wiring 170. In this case, the first material layer 175 of FIG. 5A is over-etched, and thus, each of the first to third photosensitive patterns 182, 184, and 186 may have the first to third wiring patterns ( 170a, 170b, 170c) has a larger width.

In this case, as shown in FIG. 4, the first and second groove patterns 172 and 174 may be formed within the width W of the wiring 170 to improve lift-off capability. The first and second groove patterns 172 and 174 corresponding to the upper side and the lower side are separated from each other by patterning a portion of the wiring 170. It is generally formed to be spaced in parallel.

This configuration is intended to facilitate the penetration of a stripper into the first and second groove patterns 172 and 174 when the lift off process is performed.

Next, a second material layer 150 is formed on the substrate 100 including the first to third photosensitive patterns (182, 184, and 186 of FIG. 5B). The second material layer 150 is a transparent conductive metal material layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) or copper (Cu), molybdenum (Mo), molybdenum alloy (MoTi), A protective layer made of a conductive metal material layer such as aluminum (Al), aluminum alloy (AlNd), and chromium (Cr), an organic insulating material, or an inorganic insulating material. The second material layer 150 is formed using a sputtering method, which will be described later.

As described above, each of the first to third photosensitive patterns 182, 184, and 186 has a width greater than that of the first to third wiring patterns 170a, 170b, and 170c to expose the lower portion of the edge thereof. In the second material layer 150, a disconnection phenomenon occurs at a boundary between the wiring patterns 170a, 170b, and 170c and the photosensitive patterns 182, 184, and 186.

Next, as shown in FIG. 5C, a lift-off process using a stripper is performed, whereby a breakage of the second material layer 150 in FIG. 5B occurs in the first and second groove patterns 172 and 174. The first to third photosensitive patterns 182, 184, and 186 located above the wiring 170 including the first and second groove patterns 172 and 174 to induce the penetration of the stripper into the portions thereof. Simultaneously removing the second material layer (150 in FIG. 5B) is performed. At this time, the second material layer (150 of FIG. 5B) corresponding to the first and second groove patterns 172 and 174 on which the photosensitive patterns 182, 184, and 186 are not formed is not removed and the first material pattern ( 158).

However, when the above-described lift-off process is performed, when the first and second groove patterns 172 and 174 designed as a plurality of rectangular patterns are spaced apart in parallel at equal intervals, the second wiring pattern 170b is formed. The second photoresist pattern 184 on the top and the second material layer 150 (see FIG. 5B) on the top are removed, but the first and third photoresist patterns 182 on the first and third wiring patterns 170a and 170c are removed. , 186 and the second and third material patterns 152 and 156 thereon may remain, causing a lift off process failure.

FIG. 6 is an enlarged view of portion H of FIG. 4, which will be described in detail with reference to this. In the lift-off process, the stripper penetrates in the direction of an arrow (→) at the corners of the first and second groove patterns 172 and 174. As a result, the first and third photosensitive patterns (182 and 186 of FIG. 5C), which are far from the edges, are not removed. Therefore, in the subsequent forming process of the alignment layer (not shown) in the cell process step, the rubbing cloth (not shown) may be damaged by the step by the remaining first and third photosensitive patterns 182 and 186, causing vertical staining. The remaining first and third photosensitive patterns 182 and 186 and the liquid crystal (not shown) may react to cause poor image quality such as an afterimage.

--- Second Embodiment ---

7 is a plan view showing a part of a signal wire including a groove pattern according to the present invention, and FIGS. 8A to 8D are cross-sectional views illustrating a process sequence by cutting along the line VII-VII of FIG. 7.

As illustrated in FIG. 7, a plurality of first groove patterns 273 and a plurality of second groove patterns 274 are formed in the wiring 270. In this case, the plurality of first groove patterns 273 are positioned horizontally (2n-1) and spaced apart from each other, and the plurality of second groove patterns 274 are positioned horizontally (2n) and spaced apart from each other. Each of the plurality of second groove patterns 274 is positioned to correspond to a spaced area of the neighboring first groove pattern 273. (Where n is a positive integer.) The width W of the wiring 270 is 200 µm or more, and when the first and second groove patterns 273 and 274 are arranged as described above, the wiring ( Each point on the 270 has a small distance deviation from the first and second groove patterns 273 and 274, thereby preventing the photoresist pattern from remaining during the lift-off process.

Referring to the manufacturing process for the wiring 270 of FIG. 7, first, as shown in FIG. 8A, after forming the first material layer 260 on the substrate 200, a photoresist is applied to the photosensitive layer 280. ). Depending on the process conditions, a gate insulating layer (not shown) made of silicon oxide or silicon nitride may be formed between the first material layer 260 and the substrate 200.

In this case, the first material layer 260 is a first metal layer (not shown) and copper (Cu) formed of one selected from a group of transparent conductive metals such as indium tin oxide (ITO) or indium zinc oxide (IZO). ), A structure in which a second metal layer formed of at least one selected from a group of conductive metals such as molybdenum (Mo), molybdenum alloy (MoTi), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) is laminated, or It may be any one of the first and second metal layers.

Next, the mask 290 including the transmission part TA and the blocking part BA is aligned on the substrate 200 including the first material layer 260 and the photosensitive layer 280. The transmission part TA and the blocking part BA are formed.

In this case, a halftone mask including a transmissive part TA, a blocking part BA, and a transflective part (not shown) may be applied according to process conditions.

Next, as shown in FIG. 8B, when a process step of exposing and developing the mask 200 (290 in FIG. 8A) toward the substrate 200 is performed, the photosensitive layer corresponding to the transmission part (TA in FIG. 8A) is formed. 8A and 280 are all removed to expose a part of the first material layer 260 thereunder, and the photosensitive layer 280 of FIG. 8A corresponding to the blocking part BA of FIG. 8A is left as it is. Are present, leaving the first to fourth photosensitive patterns 282, 284, 286 and 288, respectively.

Next, as shown in FIG. 8C, the exposed first material layer 260 of FIG. 8B is patterned using the first to fourth photosensitive patterns 282, 284, 286 and 288 as masks. Steps are performed to form wirings 270 in which the first and second groove patterns 273 and 274 are formed. In detail, the first to fourth wiring patterns 270a, 270b, 270c, and 270d are spaced apart from each other to correspond to the photosensitive patterns 282, 284, 286, and 288, and the ends thereof are connected to each other to form the wiring 270. Will be achieved. Here, the spaced apart portions of the first to fourth wiring patterns 270a, 270b, 270c, and 270d are defined as the first and second groove patterns 273 and 274.

The first and second groove patterns 273 and 274 are formed by patterning a portion of the wiring 270 in the width W of the wiring 270 to improve lift-off capability. It has an arrangement as shown in.

In detail, the first and second groove patterns 273 and 274 have a bar shape, and the first groove pattern 273 is transversely (2n-1), and the second groove pattern 274 is (2n) It is located laterally. In addition, the first groove patterns 273 of each lateral side are spaced apart from each other, and the second groove patterns 274 are formed to be spaced apart from each other in correspondence to the spaced areas of the first groove patterns 273. Therefore, each point of the wiring 270 has less distance deviation from the first and second groove patterns 273 and 274, so that the stripper used in the lift-off process can easily penetrate the entire area of the wiring 270. can do.

In this case, the first and second groove patterns 273 and 274 are formed of a rectangular island pattern for the electrical contact of the wiring 270, and the signal distortion is not generated in consideration of the area ratio of the wiring 270. It is preferable to form in the range.

Here, the step of patterning the aforementioned first material layer 260 of FIG. 8B is performed by wet etching having isotropy, and is located below the first to fourth photosensitive patterns 282, 284, 286, and 288. The first material layer 260 of FIG. 8A is overetched. Therefore, the width of each of the first to fourth photosensitive patterns 282, 284, 286, and 288 is larger than the width of the first to fourth wiring patterns 270a, 270b, 270c, and 270d disposed below the first to fourth photosensitive patterns 282, 284, 286, and 288. That is, the edge lower surfaces of the first to fourth photosensitive patterns 282, 284, 286 and 288 are partially exposed.

The above configuration is a stripper to the exposed edge lower surface of the first to fourth photosensitive patterns 282, 284, 286 and 288 when the lift-off process proceeds to a subsequent process. It is intended to induce easy penetration.

Next, a step of forming the second material layer 250 on the substrate 200 including the first to fourth photosensitive patterns 282, 284, 286, and 288 is performed. The second material layer 250 may be a transparent conductive metal material layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) or copper (Cu), molybdenum (Mo), molybdenum alloy (MoTi), A protective layer made of a conductive metal material layer such as aluminum (Al), aluminum alloy (AlNd), and chromium (Cr), an organic insulating material, or an inorganic insulating material. The second material layer 250 is formed using a sputtering method. In particular, the protective layer should be formed using sputtering rather than plasma chemical vapor deposition.

In general, the protective layer of the liquid crystal display is selected from the group of inorganic insulating materials and is formed by using plasma chemical vapor deposition. However, when the deposition process using the plasma chemical vapor deposition method requires a high temperature process of 350 ℃ or more, the first to fourth photosensitive patterns (282, 284, 286) formed of an organic insulating material having a photosensitive characteristic under the protective layer , 288 is only heat resistance up to about 150 ° C, the first to fourth photosensitive patterns 282, 284, 286, 288 may be deformed.

Continued deposition of the protective layer in the above-described problem condition results in the first to fourth photosensitive patterns 282, 284, 286, and 288 being completely covered with the protective layer, thereby lifting off. As the stripper does not penetrate during the lift-off process, the first to fourth photosensitive patterns 282, 284, 286, and 288 and the protective layer may remain in a lift-off process defect. In addition, in the state in which the array substrate for a liquid crystal display device is completed, when the above-mentioned problem occurs, the remaining first to fourth photosensitive patterns 282, 284, 286, and 288 may react with the liquid crystal, resulting in poor image quality such as an afterimage. Can be.

In order to solve this problem, the present invention is characterized by forming a protective layer at a process temperature of 150 ° C. or less by using a sputtering method.

When the sputtering method is used, an inorganic insulating material can be deposited at a lower temperature than the heat resistance of the first to fourth photosensitive patterns 282, 284, 286, and 288, and thus, the first to fourth photosensitive patterns ( 282, 284, 286, and 288 do not have to be pressed or deformed, and there is an advantage that can be applied to a flexible substrate, such as a plastic rather than a glass substrate.

Next, as shown in FIG. 8D, the substrate 200 including the second material layer 250 of FIG. 8C and the first to fourth photosensitive patterns 282, 284, 286, and 288 of FIG. 8C. The lift-off process step using a stripper is carried out to form a first to fourth photosensitive pattern (282, 284, 286, 288 of FIG. 8C) and the first to fourth photosensitive patterns (282, 284, 286, of FIG. 8C). 288) The second layer of material (250 in FIG. 8C) covering each top is simultaneously removed. In this case, the second material layer 250 (refer to FIG. 8C) is not removed from the first and second groove patterns 273 and 274 to form the material pattern 252.

In the present invention, as shown in Fig. 7, the plurality of first and second groove patterns (273, 274) is designed to interlock with each other in a zigzag shape, the foregoing configuration is the same as the first embodiment Alternatively, by interposing the first and second groove patterns 273 and 274, the penetration of the stripper may be easily induced even in the center portion of the wiring 270.

That is, not only can the lift-off capability be improved due to the advantage that the stripper is easily penetrated through the four corners of the first and second groove patterns 273 and 274, but also according to the above-described sputtering process. It has the advantage of preventing defects.

FIG. 9 is an enlarged view of part I of FIG. 7, which will be described in detail with reference to this. In the lift-off process, the stripper penetrates in the arrow direction (→) at four corners of the first and second groove patterns 273 and 274. When the first and second groove patterns 273 and 274 are designed to have an island shape, and the four corners of the first and second groove patterns 273 and 274 are alternately arranged, The first to fourth photosensitive patterns (282, 284, 286, and 288 of FIG. 8C) and the second material layer (250 of FIG. 8C) corresponding to all positions of the wiring 270 may be easily removed. Although the stripper is shown as penetrating at four corners of the first and second groove patterns 273 and 274 in the drawing, the stripper penetrates through the entire edge.

In this case, only the configuration of the first and second groove patterns 273 and 274 in a zigzag form has been described. However, the present invention is not limited thereto, and it will be apparent that various types of groove patterns may be applied. .

Hereinafter, various types of groove patterns will be described with reference to the accompanying drawings.

10A to 10F are plan views illustrating the shape of the groove pattern according to the exemplary embodiment of the present invention. As described above, the wiring includes both various signal wiring and material patterns having a width of 200 μm or more.

Referring to FIGS. 10A to 10F, the groove patterns designed in various shapes will be described. First, FIG. 10A shows that the island-shaped groove pattern 371 is formed in the form of a saw tooth in response to the wiring 370. will be. That is, at least one groove pattern 371 having a zigzag shape is formed. In the groove pattern 372 of FIG. 10B, two groove lines cross each other at an angle. That is, the groove pattern 372 has a cross shape that forms an acute angle and an obtuse angle at the intersection point. In FIG. 10C, the groove patterns 373 vertically cross each other to correspond to the wiring 370.

In addition, FIG. 10D illustrates a vertical portion where the first groove pattern 374a and the second groove pattern 374b vertically cross each other, extend vertically from the first groove pattern 374a, and the second groove pattern 374b. Shows a weathercock-shaped groove pattern 374 in which the horizontal portion extending horizontally becomes vertical. In the groove pattern 375 of FIG. 10E, a partition wall having an opening in a bar-shaped pattern is formed. . 10F also shows a rhombus groove pattern 376. The groove pattern 376 of FIG. 10F may have not only a rhombus shape but also various shapes such as a triangle and a square.

At this time, since the groove patterns of the various shapes described above are additionally designed to improve the lift-off capability of the wiring formed in a large area, the groove patterns designed in the plurality of shapes are regularly or irregularly spaced at regular intervals within the width of the wiring. Can be configured repeatedly. The wiring includes all signal wirings and material patterns having a width of about 200 μm or more, such as gate and data pads, MPS wiring, antistatic circuit wiring, and dummy wiring.

In particular, the groove pattern is separated into an upper side and a lower side, and it is most preferable to design an island pattern corresponding to the width of the wiring.

Such a configuration has the advantage of being able to easily induce the penetration of the stripper through the sides and corners of the groove pattern to improve the lift-off capability.

Therefore, in the present invention, in order to improve the lift-off capability of various signal wires, a material layer on the photoresist layer is formed by sputtering, and groove patterns having various shapes are formed in the inside corresponding to the width of the signal wires. By doing so, there is an advantage that can minimize the defects due to the lift off process.

Third Embodiment

The manufacturing method of the array substrate for liquid crystal display devices using the above lift-off method is demonstrated.

First, FIG. 11 is a schematic plan view of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention. 12A to 12F are process cross-sectional views of portions cut along the line XII-XII in FIG. 11, and FIGS. 13A to 13F are process cross-sectional views of portions cut along the line XIII-XIII in FIG. 11, and FIGS. 14A to 12F. 14f is a cross sectional view of the section taken along the line XIV-XIV in FIG. 11.

First, as shown in FIG. 11, in the liquid crystal display array substrate 400 according to the present invention, the gate line 420 and the data line 440 intersect the pixel region P on the substrate 410. In the pixel region P, a thin film transistor Tr including a gate electrode 422, a semiconductor layer, a source electrode 442, and a drain electrode 444, and the thin film transistor Tr. And a pixel electrode 460 connected to the gate electrode 422 and the source electrode 442, respectively, connected to the gate line 420 and the data line 440. The 444 is spaced apart from the source electrode 442. The pixel electrode 460 is configured to overlap the metal pattern 448 overlapping the gate wiring 420 to form a storage capacitor Cst. The metal pattern 448 may be formed on the pixel electrode 460 or the image. The gate wiring 420 and are electrically connected.

In addition, a gate pad 424 in contact with a gate pad electrode (not shown) and a gate pad contact hole GPC is positioned at one end of the gate wire 420, and at one end of the data wire 440. The data pad 446 is in contact with the pad electrode (not shown). The gate pad 424 and the data pad 446 are located in a non-display area around the display area formed of the pixel area P.

A large feature of the third embodiment of the present invention lies in the first to fourth groove patterns HP1, HP2, HP3, and HP4 formed in the non-display area. The first groove pattern HP1 is formed in the first non-display area in which the gate pad 424 is formed among the non-display areas, and the second groove pattern HP2 corresponds to the data pad 446 and its vicinity. The third and fourth groove patterns HP3 and HP4 are positioned in the non-display area, respectively, and the third and fourth non-display areas facing the second non-display area and the first non-display area. The first to fourth groove patterns HP1, HP2, HP3, and HP4 serve to smoothly lift off the material layer constituting the pixel electrode 460, and FIGS. 4, 7, and 10A. To one of the embodiments shown in FIG. 10F. According to the present exemplary embodiment, the material layer constituting the pixel electrode 460 remains in correspondence with the first to fourth groove patterns HP1, HP2, HP3, and HP4, and is removed in the non-display area except for this.

The manufacturing process of the above-mentioned liquid crystal substrate for a liquid crystal display device will be described. 12A through 12F illustrate a switching region TrA in which a thin film transistor is formed, FIGS. 13A through 13F illustrate a gate pad region GPA in which a gate pad is formed, and FIGS. 14A through 14F illustrate a data pad in which a data pad is formed. Show the area (DPA).

First, referring to FIGS. 12A, 13A, and 14A illustrating a first mask process, copper (Cu), molybdenum (Mo), molybdenum alloy (MoTi), aluminum (Al), and aluminum alloy on the substrate 410 Depositing a first metal material including at least one of (AlNd) and chromium (Cr) to deposit a first metal material layer (not shown), and performing a first mask process to form a gate wiring (not shown), A gate electrode 422 extending from the gate wiring (not shown) is formed in the switching region TrA, and a gate pad 424 connected to the gate wiring (not shown) is formed in the gate pad region GPA. . Next, a gate insulating film 426 made of silicon oxide or silicon nitride is formed on the entire surface of the substrate 410.

Next, FIGS. 12B-12D, 13B-13D, and 14B- 14D show a second mask process. 12B, 13B, and 14B, the pure amorphous silicon layer 428, the impurity amorphous silicon layer 430, and the second metal material layer 432 are successively stacked on the gate insulating film 426. . The second metal material layer 432 includes at least one of copper (Cu), molybdenum (Mo), molybdenum alloy (MoTi), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr). A first photoresist layer 480 is formed by stacking a material, such as a photoresist (PR), on the second metal material layer 432, and a transmissive area TA and a transflective area HTA thereon. ) And the blocking area BA are positioned. The transmissivity of the transflective area HTA is smaller than the transmissivity of the transmissive area TA and has a value greater than the transmissivity of the blocking area BA. The transflective area HTA corresponds to a central portion of the gate electrode 422 and both sides of the gate pad 424, and the blocking area BA is disposed on both sides of the gate electrode 422 and a data pad (not shown). The transmission area TA corresponds to the remaining area.

When the exposure and development processes are performed on the first photoresist layer 480 using the mask M, as shown in FIGS. 12C, 13C, and 14C, the blocking portion (FIGS. 12B and 14B) is described. First photoresist pattern 482a having a first height corresponding to BA) and a second photoresist having a second height smaller than the first height corresponding to the transflective portions (HTAs in FIGS. 12B and 13B). Pattern 482b is formed. Meanwhile, in the region corresponding to the transmission part (TA of FIGS. 12B, 13B, and 14B), all of the first photoresist layer (480 of FIG. 12B) is removed to expose the second metal material layer (432 of FIG. 12B). do. Next, the second metal material layer (432 of FIG. 12B) and the impurity amorphous silicon layer (430 of FIG. 12B) exposed below the first and second photoresist patterns 482a and 482b and the pure amorphous layer. The silicon layer (428 in Fig. 12B) and the gate insulating film 426 are removed. As a result, the substrate 410 is exposed in the pixel area P, and the gate pad 424 is exposed through the gate pad contact hole GPC in the gate pad area GPA, and the data is exposed in the data pad area DPA. The data pad 446 is formed from the second metal material layer 432 of FIG. 14B. As the second metal material layer 432 of FIG. 12B, the impurity amorphous silicon layer 430 of FIG. 12B, and the pure amorphous silicon layer 428 of FIG. 12B are patterned, the metal material pattern 432a is patterned. The impurity amorphous silicon pattern 430a and the pure amorphous silicon pattern 428a are formed.

Next, as shown in FIGS. 12D, 13D, and 14D, an ashing process is performed on the first and second photoresist patterns 482a and 482b of FIGS. 12C, 13C, and 14C. The second photoresist pattern 482b of FIGS. 12C, 13C, and 14C is removed, and the third photoresist pattern 482c whose height is reduced from the first photoresist pattern (482A of FIGS. 12C and 14C) is removed. Form. In addition, the metal material pattern (432a of FIGS. 12C and 13C) exposed by the removal of the second photoresist pattern (FIGS. 12C, 13C and 482B of FIG. 14C) and the impurity amorphous silicon pattern (FIG. 12C and FIG. 430a of 13c is removed to expose the underlying pure amorphous silicon pattern 428a. As a result, source and drain electrodes 442 and 444 spaced apart from each other by the pattern of the metal material pattern 432a are formed corresponding to the gate electrode 422, and the ohmic contact layer 434b spaced apart from each other under the gate electrode 422 ) Is formed. In addition, the exposed pure amorphous silicon pattern 428a positioned under the ohmic contact layer 434b forms an active layer (434a in FIG. 12C). Here, the semiconductor layer 434 including the gate electrode 422, the gate insulating layer 426, the active layer 434a, and the ohmic contact layer 434b, and the source and drain electrodes 442 and 444 may be a thin film transistor Tr. Configure

12E and 12F, 13E and 13F, 14E and 14F show a third mask process. 12E, 13E, and 14E, after removing the third photoresist pattern 482c, an insulating material layer (not shown) is formed using silicon oxide or silicon nitride, and a fourth photo is formed thereon. A resist pattern 484 is formed. The fourth photoresist pattern 484 is formed corresponding to the entire switching region TrA, and is spaced apart from each other around the gate pad 424. The fourth photoresist pattern 484 corresponding to the switching region TrA exposes a portion of the drain electrode 444. A space between the fourth photoresist pattern 484 spaced apart from each other around the gate pad 424 constitutes the first groove pattern HP1. In addition, a fourth photoresist pattern 484 is formed corresponding to both ends and the center portion of the data pad 446, and a space between the fourth photoresist pattern 484 in the center portion and the fourth photoresist pattern 484 at both ends is formed. 2 A groove pattern HP2 is formed. 4, the fourth photoresist pattern 484 may be separated by the first and second groove patterns HP1 and HP2, but the first and second groove patterns HP1 and HP2 may be separated from each other. The fourth photoresist patterns 484 positioned are connected to each other. Although not illustrated, as described with reference to FIG. 11, a plurality of fourth photoresist patterns spaced apart from each other may be formed in the non-display area facing the data pad and the gate pad to form the third and fourth groove patterns. It consists.

Next, the protective layer 450 is formed by patterning a lower insulating material layer (not shown) using the fourth photoresist pattern 484. In this case, the insulating material layer (not shown) is overetched, so that the fourth photoresist pattern 484 protrudes from the protective layer 450. That is, the fourth photoresist pattern 484 has a width larger than that of the protective layer 450.

Next, a transparent conductive material layer 452 is formed by depositing a material such as ITO or IZO. As described above, an end of the fourth photoresist pattern 484 has a shape protruding from the protective layer 450. As a result, a break occurs in the transparent conductive material layer 452 at the boundary thereof. In the case of the plasma chemical vapor deposition method which proceeds at a high temperature process of 350 ° C. or higher, damage occurs to the lower photoresist pattern, and a lift-off process defect occurs. Accordingly, in the present invention, the transparent conductive material layer 452 is formed by the sputtering method having a process temperature of 150 ° C. or less. In this configuration, the lift-off process is performed by using the stripper, and the stripper penetrates into the portion where the transparent conductive material layer 452 is broken, whereby the fourth photoresist pattern 484 and the transparent conductive material layer thereon. 452 are removed together.

At this time, the first groove pattern HP1, the second groove pattern HP2, and the third and fourth groove patterns (not shown) formed in the periphery of the gate pad 424, the data pad 446, and the periphery thereof. ), The lift-off process proceeds smoothly. That is, as described above, when the lift-off process is performed on the data pad 446 and its periphery, the width of the photoresist pattern used therein is 200 µm or more, so that defects caused by the residual photoresist material or the like may occur. do. However, according to the present invention, since the stripper easily penetrates to the center portion of the photoresist pattern by the plurality of first to fourth groove patterns, it is possible to solve the conventional problems such as residual photoresist material.

12F, 13F, and 14F, as illustrated in FIGS. 12F, 13F, and 14F, a pixel electrode 460 connected to the drain electrode 444 is formed corresponding to the pixel region P, and a gate is formed. A gate pad electrode 462 is formed in the pad area GPA to be in contact with the gate pad 424 and the gate pad contact hole GPC, and the second pad pattern HP2 is formed in the data pad area DPA. Correspondingly, a data pad electrode 464 is formed in contact with the data pad 446. In addition, the transparent conductive material layer 452 of FIG. 13E remains around the gate pad region GPA to correspond to the first groove pattern HP1 to form an island-shaped first liftoff pattern 452a. Although not shown, transparent conductive material layers remain in the form of islands in the non-display area surrounding the data pad 446 and facing the gate and data pad areas GPA and DPA to form second to fourth lift-off patterns. .

By the above process, the array substrate for liquid crystal display devices was manufactured by the three mask process containing a lift-off process.

Fourth Embodiment

In the fourth embodiment, a manufacturing process of an array substrate for a three mask liquid crystal display device in which a lift-off process is performed on the protective layer will be described. Processes similar to those in the third embodiment will be briefly described.

15A to 15H are cross-sectional views illustrating manufacturing processes of a pixel area including a switching region, FIGS. 16A to 16H are cross-sectional views illustrating a manufacturing process of a gate pad region, and FIGS. 17A to 17H are cross-sectional views illustrating a manufacturing process of a data pad region of FIGS. to be.

Referring to FIGS. 15A, 16A, and 17A, which illustrate a first mask process, a gate electrode 522 and a gate are formed in a switching region TrA by depositing and patterning a first metal material (not shown) on a substrate 510. The gate pad 524 is formed in the pad region GPA. Next, a gate insulating film 526 is formed.

Next, FIGS. 15B-15D, 16B-16D and 17B-17D show a second mask process. As shown in FIGS. 15B, 16B, and 17B, a pure amorphous silicon layer 528, an impurity amorphous silicon layer 530, a second metal material layer 532, and a first photo are formed on the gate insulating layer 526. A resist layer (not shown) is laminated. Next, the first and second photoresist patterns 582a and 582b having different heights are exposed and developed by exposing and developing the first photoresist layer using a mask including a transmissive region, a transflective region, and a blocking region. To form.

Next, as shown in FIGS. 15C, 16C, and 17C, the pure amorphous silicon layer 528, the impurity amorphous silicon layer 530, and the second metal using the first and second photoresist patterns 582a and 582b. The material layer 532 and the gate insulating layer 526 are patterned to expose the gate pad 524. Next, an ashing process is performed to form a third photoresist pattern 582c, and the pure amorphous silicon layer 528, the impurity amorphous silicon layer 530, and the first exposed photoresist are formed using the third photoresist pattern 582c. 2, the metal material layer 532 is removed to form the pure amorphous silicon pattern 528a, the impurity amorphous silicon pattern 530a, and the metal material pattern 532a stacked on both sides of the gate pad 524.

As a result, as shown in FIGS. 15D, 16D, and 17D, the pure amorphous silicon pattern 528a, the impurity amorphous silicon pattern 530a, and the metal material pattern 532a are stacked in the switching region TrA. The pure amorphous silicon pattern 528a, the impurity amorphous silicon pattern 530a, and the data pad 546 are stacked in the pad region DPA.

15E and 15H, 16E and 16H, 17E and 17H show a third mask process. As shown in FIGS. 15E, 16E, and 17E, a transparent conductive material layer 552 is formed, and fourth and fifth photoresist patterns 584a and 584b having different heights are formed thereon.

Next, as illustrated in FIGS. 15F, 16F, and 17F, the transparent conductive material layer 552, the metal material pattern 532a, and the fourth and fifth photoresist patterns 584a and 584b may be used. By patterning the impurity amorphous silicon pattern 530a, the ohmic contact layer 534b is formed under the source electrode 542 and the drain electrode 544, which are spaced apart from each other, and an active layer 534a is partially exposed. Form. The active layer 534a and the ohmic contact layer 534b form a semiconductor layer 534, and the gate electrode 522, the gate insulating layer 526, the semiconductor layer 534, and the source and drain electrodes 542 and 544. Silver constitutes a thin film transistor Tr. The ashing process is performed to form a sixth photoresist pattern 584c. The space between the sixth photoresist pattern 584c on the gate pad 524 forms the first groove pattern HP1, and the space between the sixth photoresist pattern 584c on the data pad 546 is the second groove pattern. (HP2). In the drawing, the sixth photoresist pattern 584c may be separated by the first and second groove patterns HP1 and HP2, but both sides of each of the first and second groove patterns HP1 and HP2 may be separated. The sixth photoresist pattern 584c positioned is connected to each other. A pixel electrode connected to the drain electrode 544 in the pixel region P by patterning a lower transparent conductive material layer 552 of FIGS. 15E, 16E, and 17E by using the sixth photoresist pattern 584c. 560 is formed, and a transparent conductive material pattern 552a is formed on the gate pad 524 and the data pad 546. At this time, the transparent conductive material layer (552 of FIGS. 15E, 16E, and 17E) is overetched so that the sixth photoresist pattern 584c protrudes from the end of the pixel electrode 560 and the transparent conductive material pattern 552a. do.

Next, as shown in FIGS. 15G, 16G, and 17G, a protective layer 550 made of silicon oxide or silicon nitride is formed by sputtering. In general, the protective layer 550 is formed by a plasma chemical vapor deposition method. However, when the plasma chemical vapor deposition method proceeds to a high temperature process of 350 ° C. or higher, damage occurs to the lower photoresist pattern, and a lift-off process defect occurs. Therefore, in this invention, the protective layer 550 is formed by the sputtering method which has a process temperature of 150 degrees C or less.

The protective layer 550 is disconnected between the pixel electrode 560 and the sixth photoresist pattern 584c and between the transparent conductive material pattern 552a and the sixth photoresist pattern 584c, and the lift-off process is performed. As it proceeds, the stripper penetrates into a portion where break occurs, and the sixth photoresist pattern 584c and the protective layer 550 thereon are removed together. In particular, in the gate pad 526 and the data pad 546 having a width of 200 μm or more, the stripper is easily penetrated by the first and second groove patterns HP1 and HP2, so that a smooth lift-off process is performed. .

As a result, as shown in FIGS. 15H, 16H, and 17H, the active layer 534a exposed in the switching region TrA is covered and protected by the protective layer 550, and the gate pad region GPA is protected. The protective layer 550 remains in correspondence with the first groove pattern HP1, and the gate pad electrode 562 made of a transparent conductive material is connected to the gate pad 526. In addition, the protective layer 550 remains in the data pad region DPA corresponding to the second groove pattern HP2, and the data pad electrode 564 made of a transparent conductive material is connected to the data pad 546. .

However, the present invention is not limited to the above embodiment, and it will be apparent that various modifications and variations are possible.

1 is a plan view showing a conventional array substrate for a liquid crystal display device.

FIG. 2 is an enlarged plan view of a portion A of FIG. 1; FIG.

3A to 3C are cross-sectional views illustrating a manufacturing process of a portion cut along the line III-III of FIG. 2.

4 is a plan view showing a part of a wiring including a groove pattern according to the present invention.

5A to 5C are cross-sectional views illustrating a process sequence by cutting along line V-V of FIG. 4.

FIG. 6 is an enlarged view of a portion H of FIG. 4; FIG.

7 is a plan view showing a part of a wiring including a groove pattern according to the present invention.

8A to 8D are cross sectional views taken along a line VII-VII of FIG. 7, according to a process sequence.

9 is an enlarged view of a portion I of FIG. 7;

10A to 10F are plan views showing the shape of the groove pattern according to the embodiment of the present invention.

11 is a schematic plan view of an array substrate for a liquid crystal display device according to an embodiment of the present invention.

12A to 12F are cross-sectional views of a section taken along the line XII-XII in FIG. 11.

13A-13F show the process stages of the cut along the line XIII-XIII of FIG. 11.

14A-14F are process cross-sectional views of the cut along the line XIV-XIV in FIG. 11;

15A to 15H are cross-sectional views of a manufacturing process of a pixel region including a switching region.

16A-16H are cross-sectional views of a manufacturing process for the gate pad region.

17A-17H are cross-sectional views of a manufacturing process for a data pad region.

* Explanation of symbols for the main parts of the drawings *

200: substrate 270: wiring

273, 274: home pattern

Claims (10)

  1. Forming a first layer of material on the substrate;
    Forming a photoresist pattern on the first material layer, the photoresist pattern having first and second holes exposing first and second portions of the first material layer;
    Patterning the first material layer using the photoresist pattern as a mask to form first and second groove patterns corresponding to the first and second holes in the material pattern and the material pattern;
    Forming a second material layer on the first and second groove patterns and the photoresist pattern;
    Simultaneously removing the photoresist pattern and the second material layer thereon
    Lift off method comprising a.
  2. The method of claim 1,
    Each of the first and second groove patterns may be any one of a bar shape, a sawtooth shape, a cross shape, a pinwheel shape, a shape having a partition having an opening in the bar shape pattern, and a rhombus shape.
  3. The method of claim 1,
    The second material layer is a lift layer, characterized in that a protective layer made of any one of silicon oxide and silicon nitride, or a transparent conductive material layer made of any one of indium tin oxide (ITO) and indium zinc oxide (IZO). Off way.
  4. The method of claim 3, wherein
    And wherein said second material layer is formed by sputtering.
  5. The method of claim 1,
    The width of the material pattern is 200㎛ or more, the liftoff method, characterized in that less than the width of the first material layer.
  6. Forming a display area, a gate wiring extending in one direction on a substrate on which first, second, third, and fourth non-display areas are defined, and a gate electrode connected to the gate wiring in the display area; Making a step;
    A data line crossing the gate line, a data pad connected to the data line and positioned in the first non-display area, a semiconductor layer on the gate electrode, and a source electrode spaced apart from each other on the semiconductor layer; Forming a drain electrode;
    Forming an insulating material layer on an entire surface of the substrate including the data line, the data pad, the source electrode, and the drain electrode;
    A first photoresist pattern corresponding to the source and drain electrodes on the insulating material layer, and first and second holes corresponding to the data pads and corresponding to the first and second regions of the data pads; Forming a photoresist pattern;
    Patterning the insulating material layer using the first and second photoresist patterns to expose a portion of the drain electrode, and first and second portions to expose each of the first and second regions of the data pad. Forming a second groove pattern;
    Forming a transparent conductive material layer on an entire surface of the substrate on which the exposed drain electrode, the first and second groove patterns, and the first and second photoresist patterns are formed;
    Simultaneously removing the first and second photoresist patterns and the transparent conductive material layer thereon by a lift-off process
    Method of manufacturing an array substrate for a liquid crystal display device comprising a.
  7. The method of claim 6,
    The forming of the first photoresist pattern and the second photoresist pattern may include forming a first photoresist pattern and a second photoresist pattern having third and fourth holes corresponding to third and fourth regions of the second, third and fourth non-display areas, respectively. 3 forming a photoresist pattern,
    Patterning the insulating material layer includes removing the insulating material layer corresponding to the third and fourth regions to form third and fourth groove patterns,
    The lift-off process includes removing the third photoresist pattern and the transparent conductive material layer thereon at the same time.
  8. The method of claim 7, wherein
    The width of the data pad, the second, third and fourth non-display areas is 200 µm or more and less than or equal to the width of the substrate.
  9. Forming a gate line extending in one direction on the substrate and a gate pad at one end of the gate line;
    Forming a gate insulating film, a pure amorphous silicon layer, an impurity amorphous silicon layer, and a metal material layer on an entire surface of the substrate including the gate wiring and the gate pad;
    The metal material layer, the impurity amorphous silicon layer, the pure amorphous silicon layer, and the gate insulating layer are sequentially patterned to form a data line defining a pixel region crossing the gate line and a data pad positioned at one end of the data line. Exposing the gate pad;
    Forming a transparent conductive material layer on an entire surface of the substrate including the data line and the data pad;
    A first photoresist pattern having first and second holes corresponding to the first and second regions of the gate pad and corresponding to the first and second regions of the data pad on the transparent conductive material layer; Forming a second photoresist pattern having third and fourth holes;
    Patterning the transparent conductive material layer using the first and second photoresist patterns to thereby expose the gate pads corresponding to the first and second holes, and the third and third groove patterns. Forming third and fourth groove patterns exposing the data pads corresponding to fourth holes;
    Forming a protective layer on an entire surface of the substrate on which the first to fourth groove patterns and the first and second photoresist patterns are formed;
    Simultaneously removing the first and second photoresist patterns and the protective layer thereon by a lift-off process
    Method of manufacturing an array substrate for a liquid crystal display device comprising a.
  10. The method of claim 9,
    Forming the gate line and the gate pad includes forming a gate electrode connected to the gate line,
    Sequentially patterning the metal material layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer comprises forming a pure amorphous silicon pattern, an impurity amorphous silicon pattern, and a metal material pattern stacked on the gate electrode,
    Forming the first and second photoresist patterns includes exposing a central portion of the metal material pattern, and forming a third photoresist pattern corresponding to the pixel region.
    The patterning of the transparent conductive material layer may include removing an impurity amorphous silicon pattern at a center portion and a lower portion of the metal material pattern, and forming a pixel electrode connected to one end of the metal material pattern corresponding to the pixel region. Including,
    The removing of the protective layer may include simultaneously removing the third photoresist pattern and the protective layer on the upper portion of the third photoresist pattern.
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US7279370B2 (en) 2003-10-11 2007-10-09 Lg.Philips Lcd Co., Ltd. Thin film transistor array substrate and method of fabricating the same
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