TWI381549B - Light-emitting diode package - Google Patents
Light-emitting diode package Download PDFInfo
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- TWI381549B TWI381549B TW097115580A TW97115580A TWI381549B TW I381549 B TWI381549 B TW I381549B TW 097115580 A TW097115580 A TW 097115580A TW 97115580 A TW97115580 A TW 97115580A TW I381549 B TWI381549 B TW I381549B
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- emitting diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Description
本發明是有關於一種發光二極體封裝(light－emitting diode package)，且特別是有關於一種具有高發光效率的發光二極體封裝。The present invention relates to a light-emitting diode package, and more particularly to a light emitting diode package having high luminous efficiency.
發光二極體屬於半導體元件，其發光晶片之材料主要為III－V族化學元素，如：磷化錄(GaP)、砷化鎵(GaAs)等化合物半導體，其發光原理係將電能轉換為光，也就是對化合物半導體施加電流，透過電子與電洞的結合，將能量以光的形式釋出，進而達成發光的效果。由於發光二極體的發光現象不是藉由加熱發光或放電發光，因此發光二極體的壽命長達十萬小時以上，且無須暖燈時間(idling time)。此外，發光二極體更具有反應速度快(約為10－9 秒)、體積小、用電省、污染低、高可靠度、適合量產等優點，所以發光二極體所能應用的領域十分廣泛，如大型看板、交通號誌燈、手機、掃描器、傳真機之光源以及照明裝置等。由於發光二極體的發光亮度與發光效率持續地提昇，同時白光的發光二極體也被成功地量產，所以逐漸有發光二極體被應用在顯示器、照明裝置等產品中。The light-emitting diode belongs to a semiconductor component, and the material of the light-emitting chip is mainly a group III-V chemical element, such as a compound semiconductor such as phosphating (GaP) or gallium arsenide (GaAs), and the light-emitting principle is to convert electrical energy into light. That is, a current is applied to the compound semiconductor, and the combination of electrons and holes is used to release the energy in the form of light, thereby achieving the effect of luminescence. Since the luminescence phenomenon of the illuminating diode is not by heating or discharging, the life of the illuminating diode is as long as 100,000 hours or more, and no idling time is required. In addition, the light-emitting diode has the advantages of fast reaction speed (about 10 -9 seconds), small volume, low power consumption, low pollution, high reliability, and suitable for mass production, so the field in which the light-emitting diode can be applied is applicable. It is very extensive, such as large billboards, traffic lights, mobile phones, scanners, fax machine light sources and lighting devices. Since the luminance and the luminous efficiency of the light-emitting diode are continuously improved, and the white light emitting diode is also successfully mass-produced, the light-emitting diode is gradually applied to products such as displays and lighting devices.
圖1為習知發光二極體封裝之剖面示意圖。請參照圖1，習知的發光二極體封裝100包括一導線架110、一發光二極體晶片120以及一封裝膠體130。其中，導線架110的表面110a為鏡面(specular surface)用以反射發光二極體晶片120所發出 的光線。發光二極體晶片120配置於導線架110上，並與導線架110電性連接。此外，封裝膠體130包覆發光二極體晶片120以及部分導線架110，以使部分導線架110暴露於封裝膠體130外，以作為外部電極E。1 is a schematic cross-sectional view of a conventional light emitting diode package. Referring to FIG. 1 , a conventional LED package 100 includes a lead frame 110 , a light emitting diode chip 120 , and an encapsulant 130 . The surface 110a of the lead frame 110 is a specular surface for reflecting the emitted light emitting diode chip 120. The light. The LED chip 120 is disposed on the lead frame 110 and electrically connected to the lead frame 110. In addition, the encapsulant 130 encloses the LED chip 120 and a portion of the lead frame 110 such that a portion of the lead frame 110 is exposed outside the encapsulant 130 as the external electrode E.
如圖1所示，封裝膠體130係由一外殼132以及一第一透光部134所構成。外殼132具有一凹陷132a，發光二極體晶片120位於該凹陷132a內，且凹陷132a具有傾斜程度固定的側壁S。透光部134則配置於凹陷132a中並與外殼132連接，透光部134包覆發光二極體晶片120以及未被外殼132包覆之導線架110的部分區域。As shown in FIG. 1 , the encapsulant 130 is composed of a casing 132 and a first light transmitting portion 134 . The outer casing 132 has a recess 132a in which the light emitting diode wafer 120 is located, and the recess 132a has a side wall S having a fixed inclination. The light transmitting portion 134 is disposed in the recess 132a and connected to the outer casing 132. The light transmitting portion 134 covers the light emitting diode wafer 120 and a partial region of the lead frame 110 not covered by the outer casing 132.
由圖1可清楚得知，雖然表面為鏡面的導線架110對於光線的反射效果十分良好，但被透光部134包覆的部分導線架110會將發光二極體晶片120所發出的光線反射，且被導線架110反射後的光線極有可能因為全反射現象而被侷限於封裝膠體130的透光部134內部，進而造成發光二極體封裝100的整體發光效率不彰。As is clear from FIG. 1, although the lead frame 110 having a mirror surface has a good reflection effect on light, a part of the lead frame 110 covered by the light transmitting portion 134 reflects the light emitted from the LED chip 120. The light reflected by the lead frame 110 is likely to be limited to the inside of the light transmitting portion 134 of the encapsulant 130 due to the phenomenon of total reflection, thereby causing the overall luminous efficiency of the LED package 100 to be inconsistent.
本發明提供一種發光二極體封裝，其具有良好的發光效率。The invention provides a light emitting diode package which has good luminous efficiency.
本發明提出一種發光二極體封裝，其包括一導線架、至少一發光二極體晶片以及一封裝膠體。其中，導線架具有一粗糙表面，發光二極體晶片配置於導線架上，並與導線架電性連接，粗糙表面適於使發光二極體晶片所發出的光線散射。此外，封裝膠體包覆發光二極體晶片以及部分導線架， 以使部分導線架暴露於封裝膠體外。The invention provides a light emitting diode package comprising a lead frame, at least one light emitting diode chip and an encapsulant. The lead frame has a rough surface, and the LED is disposed on the lead frame and electrically connected to the lead frame. The rough surface is adapted to scatter light emitted by the LED chip. In addition, the encapsulant encapsulates the LED chip and a portion of the lead frame. In order to expose part of the lead frame to the outside of the encapsulant.
在本發明之一實施例中，上述之導線架包括多個引腳，各個引腳具有一內引腳以及一外引腳，內引腳被封裝膠體包覆並與發光二極體晶片電性連接，而外引腳暴露於封裝膠體外。In an embodiment of the invention, the lead frame comprises a plurality of pins, each of the pins has an inner lead and an outer lead, and the inner lead is covered by the encapsulant and electrically connected to the LED. Connected while the outer leads are exposed to the outside of the package.
在本發明之一實施例中，上述之各個內引腳具有前述之粗糙表面。In an embodiment of the invention, each of the inner leads has a rough surface as described above.
在本發明之一實施例中，上述之各個內引腳與各個外引腳具有前述之粗糙表面。In an embodiment of the invention, each of the inner and outer pins has a rough surface as described above.
在本發明之一實施例中，上述之各個外引腳從封裝膠體的側壁延伸至封裝膠體的底部。In an embodiment of the invention, each of the outer leads extends from a sidewall of the encapsulant to a bottom of the encapsulant.
在本發明之一實施例中，上述之封裝膠體包括一外殼以及一透光部。其中，外殼具有一凹陷，且發光二極體晶片位於凹陷內。透光部配置於凹陷中並與外殼連接，且透光部包覆發光二極體晶片以及未被外殼包覆之內引腳的部分區域。In an embodiment of the invention, the encapsulant comprises an outer casing and a light transmitting portion. Wherein, the outer casing has a recess, and the light emitting diode chip is located in the recess. The light transmitting portion is disposed in the recess and connected to the outer casing, and the light transmitting portion covers the light emitting diode wafer and a partial region of the inner pin not covered by the outer casing.
在本發明之一實施例中，上述之被透光部包覆之內引腳的部分區域具有前述之粗糙表面。In an embodiment of the invention, the partial region of the inner lead covered by the light transmitting portion has the aforementioned rough surface.
在本發明之一實施例中，上述之被外殼包覆之內引腳的部分區域具有前述之粗糙表面。In an embodiment of the invention, the partial region of the inner lead covered by the outer casing has the aforementioned rough surface.
在本發明之一實施例中，上述之粗糙表面的粗糙度介於0.05微米至500微米之間。In an embodiment of the invention, the roughness of the rough surface is between 0.05 microns and 500 microns.
由於本發明採用具有散射表面的導線架作為晶片承載器(chip carrier)，因此，本發明之發光二極體封裝具有良好的發光效率。Since the present invention employs a lead frame having a scattering surface as a chip carrier, the light emitting diode package of the present invention has good luminous efficiency.
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。The above and other objects, features and advantages of the present invention will become more <RTIgt;
圖2與圖3為本發明第一實施例之發光二極體封裝之剖面示意圖。請參照圖2與圖3，本實施例之發光二極體封裝200包括一導線架210、至少一個發光二極體晶片220以及一封裝膠體230。其中，導線架210具有一粗糙表面210a，發光二極體晶片220配置於導線架210上，並與導線架210電性連接。在本實施例中，發光二極體晶片220例如是透過焊線(bonding wire)240與導線架210電性連接，當然，發光二極體晶片220亦可以透過覆晶技術(flip－chip technology)或是其他晶粒接合製程(die－bonding processes)達成電性連接之目的。封裝膠體230包覆發光二極體晶片220以及部分導線架210，以使部分導線架210暴露於封裝膠體230外。此外，粗糙表面210a適於使發光二極體晶片220所發出的光線散射，而在本實施例中，粗糙表面的粗糙度例如是介於0.05微米至500微米之間。2 and 3 are schematic cross-sectional views showing a light emitting diode package according to a first embodiment of the present invention. Referring to FIG. 2 and FIG. 3 , the LED package 200 of the present embodiment includes a lead frame 210 , at least one LED chip 220 , and an encapsulant 230 . The lead frame 210 has a rough surface 210a. The LED chip 220 is disposed on the lead frame 210 and electrically connected to the lead frame 210. In this embodiment, the LED chip 220 is electrically connected to the lead frame 210 through a bonding wire 240. Of course, the LED chip 220 can also pass through flip-chip technology. Or other die-bonding processes for electrical connection. The encapsulant 230 encloses the LED chip 220 and a portion of the lead frame 210 to expose a portion of the lead frame 210 to the outside of the encapsulant 230. Further, the rough surface 210a is adapted to scatter light emitted by the light-emitting diode wafer 220, and in the present embodiment, the roughness of the rough surface is, for example, between 0.05 micrometers and 500 micrometers.
如圖2與圖3所示，導線架210包括多個引腳L，各個引腳L具有一內引腳IL以及一外引腳OL，內引腳IL被封裝膠體230包覆並與發光二極體晶片220電性連接，而外引腳OL暴露於封裝膠體230外，且各個外引腳OL例如是從封裝膠體230的側壁延伸至封裝膠體230的底部。在本實施例中，導線 架210例如是銅導線架、鋁導線架等金屬材質之導線架，當然本實施例亦可根據實際需求在導線架230上鍍上一金屬鍍層(metal coatings)。此外，本發明所採用的導線架210不限定於圖2與圖3中所繪示出的型態，換言之，導線架210可根據實際設計需求而採用上置(up－set)設計或下沈設計(down set)，意即，被封裝膠體230所包覆的內引腳IL與外引腳OL可分別位在不同平面上。As shown in FIG. 2 and FIG. 3, the lead frame 210 includes a plurality of pins L. Each of the pins L has an inner lead IL and an outer lead OL. The inner lead IL is covered by the encapsulant 230 and emits light. The polar body wafers 220 are electrically connected, and the outer leads OL are exposed outside the encapsulant 230, and the respective outer leads OL extend from the sidewalls of the encapsulant 230 to the bottom of the encapsulant 230, for example. In this embodiment, the wire The frame 210 is, for example, a lead frame of a metal material such as a copper lead frame or an aluminum lead frame. Of course, in this embodiment, a metal coating may be plated on the lead frame 230 according to actual needs. In addition, the lead frame 210 used in the present invention is not limited to the type illustrated in FIG. 2 and FIG. 3, in other words, the lead frame 210 can adopt an up-set design or sink according to actual design requirements. Down set, that is, the inner pin IL and the outer pin OL covered by the encapsulation colloid 230 can be respectively located on different planes.
值得注意的是，製造者可在導線架210上的不同部位形成粗糙表面210a，而在導線架210的不同部位上形成粗糙表面210a，將可帶來不同的功效(將詳述於後)。舉例而言，製造者可以在各個內引腳IL上形成粗糙表面210a(如圖2所繪示)，當然，製造者亦可在內引腳IL以及外引腳OL上同時形成粗糙表面210a(如圖3所繪示)。It is worth noting that the manufacturer can form a rough surface 210a at different locations on the leadframe 210, while forming a rough surface 210a on different portions of the leadframe 210 will provide different efficiencies (described in detail later). For example, the manufacturer may form a rough surface 210a on each of the inner leads IL (as shown in FIG. 2). Of course, the manufacturer may simultaneously form the rough surface 210a on the inner lead IL and the outer lead OL ( As shown in Figure 3).
當製造者在導線架210的外引腳OL上形成粗糙表面210a時，此粗糙表面210a將有助於發光二極體封裝200與其他承載器(如電路板)之間的連接。當製造者在導線架210的內引腳IL上形成粗糙表面210a時，此粗糙表面210a將有助於導線架210本身與封裝膠體230之間的接合強度，使導線架210與封裝膠體230之間不容易有脫層的現象(de－lamination)發生。When the manufacturer forms a rough surface 210a on the outer lead OL of the lead frame 210, this rough surface 210a will facilitate the connection between the light emitting diode package 200 and other carriers such as a circuit board. When the manufacturer forms a rough surface 210a on the inner lead IL of the lead frame 210, the rough surface 210a will contribute to the bonding strength between the lead frame 210 itself and the encapsulant 230, so that the lead frame 210 and the encapsulant 230 are It is not easy to have a de-lamination.
承上述，圖2與圖3雖僅繪示出導線架210的單一表面為粗糙表面210a的情況，但本發明並不排除導線架210的二相對表面皆為粗糙表面210a之可能性。2 and FIG. 3, although only the single surface of the lead frame 210 is a rough surface 210a, the present invention does not exclude the possibility that both opposite surfaces of the lead frame 210 are rough surfaces 210a.
在本發明之一較佳實施例中，封裝膠體230包括一外殼 232以及一透光部234。其中，外殼232具有一凹陷232a，且發光二極體晶片220位於凹陷232a內。透光部234配置於凹陷232a中並與外殼232連接，且透光部234包覆發光二極體晶片220以及未被外殼232包覆之內引腳IL的部分區域。In a preferred embodiment of the invention, the encapsulant 230 includes a housing 232 and a light transmitting portion 234. The outer casing 232 has a recess 232a, and the light emitting diode wafer 220 is located in the recess 232a. The light transmitting portion 234 is disposed in the recess 232a and connected to the outer casing 232, and the light transmitting portion 234 covers the light emitting diode wafer 220 and a partial region of the inner lead IL not covered by the outer casing 232.
在內引腳IL的不同部位上形成粗糙表面210a同樣會帶來不同的功效，將詳述如下。當製造者在內引腳IL的A區域上形成粗糙表面210a時，此粗糙表面210a將有助於導線架210與發光二極體晶片220之間的接合強度；當製造者在內引腳IL的B區域上形成粗糙表面210a時，此粗糙表面210a將有助於導線架210與透光部234之間的接合強度；當製造者在內引腳IL的C區域上形成粗糙表面210a時，此粗糙表面210a將有助於導線架210與外殼232之間的接合強度。Forming a rough surface 210a on different portions of the inner lead IL also brings about different effects, as will be detailed below. When the manufacturer forms the rough surface 210a on the A region of the inner lead IL, the rough surface 210a will contribute to the bonding strength between the lead frame 210 and the light emitting diode wafer 220; when the manufacturer is inside the pin IL When the rough surface 210a is formed on the B region, the rough surface 210a will contribute to the bonding strength between the lead frame 210 and the light transmitting portion 234; when the manufacturer forms the rough surface 210a on the C region of the inner lead IL, This rough surface 210a will contribute to the strength of the joint between the lead frame 210 and the outer casing 232.
值得注意的是，製造者可選擇性地在A區域、B區域或C區域上形成粗糙表面210a，當然，製造者亦可在A區域、B區域與C區域中的至少兩個區域上形成粗糙表面210a。It should be noted that the manufacturer can selectively form the rough surface 210a on the A region, the B region, or the C region. Of course, the manufacturer can also form roughness on at least two of the A region, the B region, and the C region. Surface 210a.
圖4為本發明第二實施例之發光二極體封裝之剖面示意圖。請參照圖4，本實施例之發光二極體封裝200’包括一導線架210、至少一個發光二極體晶片220以及一封裝膠體230。其中，發光二極體晶片220配置於導線架210上並與導線架210電性連接。在本實施例中，發光二極體晶片220例如是透過焊線(bonding wire)240與導線架210電性連接，當然，發光二極體晶片220亦可以透過覆晶技術(flip－chip technology)或是其他晶粒接合製程(die－bonding processes)達成電性連接之 目的。封裝膠體230包覆發光二極體晶片220以及部分導線架230，以使部分導線架210暴露於封裝膠體230外。此外，封裝膠體230包括一外殼232以及一第一透光部234。外殼具有一第一凹陷232a，而發光二極體晶片220位於第一凹陷232a內，且第一凹陷232a具有多段傾斜程度不同的側壁S1、S2。第一透光部234配置於第一凹陷232a中並與外殼232連接，而第一透光部234包覆發光二極體晶片220以及未被外殼232包覆之導線架210的部分區域。4 is a cross-sectional view showing a light emitting diode package according to a second embodiment of the present invention. Referring to FIG. 4, the LED package 200' of the present embodiment includes a lead frame 210, at least one LED chip 220, and an encapsulant 230. The LED array 220 is disposed on the lead frame 210 and electrically connected to the lead frame 210. In this embodiment, the LED chip 220 is electrically connected to the lead frame 210 through a bonding wire 240. Of course, the LED chip 220 can also pass through flip-chip technology. Or other die-bonding processes to achieve electrical connection purpose. The encapsulant 230 encloses the LED chip 220 and a portion of the lead frame 230 to expose a portion of the lead frame 210 to the outside of the encapsulant 230. In addition, the encapsulant 230 includes a housing 232 and a first light transmitting portion 234. The outer casing has a first recess 232a, and the light-emitting diode wafer 220 is located in the first recess 232a, and the first recess 232a has a plurality of sidewalls S1, S2 having different degrees of inclination. The first light transmitting portion 234 is disposed in the first recess 232a and connected to the outer casing 232, and the first light transmitting portion 234 covers the light emitting diode wafer 220 and a partial region of the lead frame 210 not covered by the outer casing 232.
如圖4所示，導線架210包括多個引腳L，各個引腳L具有一內引腳IL以及一外引腳OL，內引腳IL被封裝膠體230包覆並與發光二極體晶片220電性連接，而外引腳OL暴露於封裝膠體230外，且各個外引腳OL例如是從封裝膠體230的側壁延伸至封裝膠體230的底部。在本實施例中，導線架210例如是銅導線架、鋁導線架等金屬材質之導線架，當然本實施例亦可根據實際需求在導線架230上鍍上一金屬鍍層(metal coatings)。此外，本發明所採用的導線架210不限定於圖4中所繪示出的型態，換言之，導線架210可根據實際設計需求而採用上置(up－set)設計或下沈設計(down set)，意即，被封裝膠體230所包覆的內引腳IL與外引腳OL可分別位在不同平面上。As shown in FIG. 4, the lead frame 210 includes a plurality of pins L. Each of the leads L has an inner lead IL and an outer lead OL. The inner lead IL is covered by the encapsulant 230 and is printed with the LED. 220 is electrically connected, and the outer pin OL is exposed outside the encapsulant 230, and each of the outer pins OL extends from the sidewall of the encapsulant 230 to the bottom of the encapsulant 230, for example. In the present embodiment, the lead frame 210 is, for example, a lead frame of a metal material such as a copper lead frame or an aluminum lead frame. Of course, in this embodiment, a metal coating can be plated on the lead frame 230 according to actual needs. In addition, the lead frame 210 used in the present invention is not limited to the type illustrated in FIG. 4, in other words, the lead frame 210 can adopt an up-set design or a sinking design according to actual design requirements. Set), that is, the inner pin IL and the outer pin OL covered by the encapsulation colloid 230 can be respectively located on different planes.
值得注意的是，製造者可在導線架210選擇性地形成一粗糙表面210a，此粗糙表面210a適於使發光二極體晶片220所發出的光線散射，而粗糙表面的粗糙度例如是介於0.05微米至500微米之間。在本實施例中，製造者可在導線架210 上的不同部位形成粗糙表面210a，而在導線架210的不同部位上形成粗糙表面210a，將可帶來不同的功效(將詳述於後)。舉例而言，製造者可以僅在各個內引腳IL上形成粗糙表面210a，當然，製造者亦可在內引腳IL以及外引腳OL上同時形成粗糙表面210a(如圖4所繪示)。It should be noted that the manufacturer can selectively form a rough surface 210a on the lead frame 210, and the rough surface 210a is adapted to scatter light emitted by the LED wafer 220, and the roughness of the rough surface is, for example, Between 0.05 microns and 500 microns. In this embodiment, the manufacturer can be in the lead frame 210 The different portions on the surface form a rough surface 210a, and the formation of a rough surface 210a on different portions of the lead frame 210 will bring about different effects (described later in detail). For example, the manufacturer may form the rough surface 210a only on each of the inner leads IL. Of course, the manufacturer may simultaneously form the rough surface 210a on the inner lead IL and the outer lead OL (as shown in FIG. 4). .
當製造者在導線架210的外引腳OL上形成粗糙表面210a時，此粗糙表面210a將有助於發光二極體封裝200’與其他承載器(如電路板)之間的連接。當製造者在導線架210的內引腳IL上形成粗糙表面210a時，此粗糙表面210a將有助於導線架210本身與封裝膠體230之間的接合強度，使導線架210與封裝膠體230之間不容易有脫層的現象(de－larnination)發生。When the manufacturer forms a rough surface 210a on the outer lead OL of the lead frame 210, this rough surface 210a will facilitate the connection between the light emitting diode package 200' and other carriers such as a circuit board. When the manufacturer forms a rough surface 210a on the inner lead IL of the lead frame 210, the rough surface 210a will contribute to the bonding strength between the lead frame 210 itself and the encapsulant 230, so that the lead frame 210 and the encapsulant 230 are It is not easy to have a de-larnination.
承上述，圖4雖僅繪示出導線架210的單一表面為粗糙表面210a的情況，但本發明並不排除導線架210的二相對表面皆為粗糙表面210a之可能性。In view of the above, although FIG. 4 only shows the case where the single surface of the lead frame 210 is the rough surface 210a, the present invention does not exclude the possibility that both opposite surfaces of the lead frame 210 are rough surfaces 210a.
在內引腳IL的不同部位上形成粗糙表面210a同樣會帶來不同的功效，將詳述如下。當製造者在內引腳IL的A區域上形成粗糙表面210a時，此粗糙表面210a將有助於導線架210與發光二極體晶片220之間的接合強度；當製造者在內引腳IL的B區域上形成粗糙表面210a時，此粗糙表面210a將有助於導線架210與透光部234之間的接合強度；當製造者在內引腳IL的C區域上形成粗糙表面210a時，此粗糙表面210a將有助於導線架210與外殼232之間的接合強度。Forming a rough surface 210a on different portions of the inner lead IL also brings about different effects, as will be detailed below. When the manufacturer forms the rough surface 210a on the A region of the inner lead IL, the rough surface 210a will contribute to the bonding strength between the lead frame 210 and the light emitting diode wafer 220; when the manufacturer is inside the pin IL When the rough surface 210a is formed on the B region, the rough surface 210a will contribute to the bonding strength between the lead frame 210 and the light transmitting portion 234; when the manufacturer forms the rough surface 210a on the C region of the inner lead IL, This rough surface 210a will contribute to the strength of the joint between the lead frame 210 and the outer casing 232.
值得注意的是，製造者可選擇性地在A區域、B區域或 C區域上形成粗糙表面210a，當然，製造者亦可在A區域、B區域與C區域中的至少兩個區域上形成粗糙表面210a。It is worth noting that the manufacturer can selectively be in Zone A, Zone B or A rough surface 210a is formed on the C region, and of course, the manufacturer may also form the rough surface 210a on at least two of the A region, the B region, and the C region.
圖5為本發明第三實施例之發光二極體封裝之剖面示意圖，而圖6A至圖6D為第三實施例中外殼與導線架的立體示意圖。請參照圖5，本實施例之發光二極體封裝300與第二實施例之發光二極體封裝200’相似，惟二者主要差異之處在於：本實施例之發光二極體封裝300可進一步包括一第二透光部236，而外殼232更具有一第二凹陷232b以容納一電子元件250以及第二透光部236(如圖6A至圖6D所繪示)，第二透光部236配置於第二凹陷232b中並與外殼232連接，而第二透光部2326包覆電子元件250以及未被外殼232包覆之導線架210的部分區域。由圖5可清楚得知，第一透光部234與第二透光部236分別位於導線架210的兩對側。此外，第一凹陷232a的尺寸例如是大於第二凹陷232b的尺寸。值得注意的是，電子元件250例如是一發光二極體晶片、一靜電防護晶片、一控制晶片或是其他型態的晶片。5 is a schematic cross-sectional view of a light emitting diode package according to a third embodiment of the present invention, and FIGS. 6A to 6D are perspective views of the outer case and the lead frame of the third embodiment. Referring to FIG. 5, the LED package 300 of the present embodiment is similar to the LED package 200' of the second embodiment, but the main difference is that the LED package 300 of the embodiment can be The second housing 232b further includes a second recess 232b for receiving an electronic component 250 and a second transparent portion 236 (as shown in FIGS. 6A-6D). 236 is disposed in the second recess 232b and connected to the outer casing 232, and the second transparent portion 2326 covers the electronic component 250 and a partial region of the lead frame 210 not covered by the outer casing 232. As can be clearly seen from FIG. 5, the first light transmitting portion 234 and the second light transmitting portion 236 are respectively located on opposite sides of the lead frame 210. Further, the size of the first recess 232a is, for example, larger than the size of the second recess 232b. It should be noted that the electronic component 250 is, for example, a light emitting diode chip, a static electricity protection chip, a control wafer or other types of wafers.
綜上所述，本發明至少具有下列優點：1.由於本發明採用具有散射表面的導線架作為晶片承載器，因此，設計者可以在不大幅增加製造成本的前提下製造出發光效率較高的發光二極體封裝。In summary, the present invention has at least the following advantages: 1. Since the present invention employs a lead frame having a scattering surface as a wafer carrier, the designer can manufacture a luminous efficiency without significantly increasing the manufacturing cost. Light-emitting diode package.
2.由於本發明之外殼具有第一凹陷，且第一凹陷具有多段傾斜程度不同的側壁，因此，本發明之發光二極體封裝具有良好的發光效率。2. Since the outer casing of the present invention has a first recess and the first recess has a plurality of side walls having different degrees of inclination, the light emitting diode package of the present invention has good luminous efficiency.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
100‧‧‧發光二極體封裝100‧‧‧Light Diode Package
110‧‧‧導線架110‧‧‧ lead frame
110a‧‧‧鏡面表面110a‧‧ ‧Surface surface
120‧‧‧發光二極體晶片120‧‧‧Light Emitter Wafer
130‧‧‧封裝膠體130‧‧‧Package colloid
132‧‧‧外殼132‧‧‧Shell
132a‧‧‧凹陷132a‧‧‧ dent
134‧‧‧透光部134‧‧‧Transmission Department
E‧‧‧外部電極E‧‧‧External electrode
S‧‧‧側壁S‧‧‧ side wall
200、200’、300‧‧‧發光二極體封裝200, 200', 300‧‧‧Light Emitter Package
210‧‧‧導線架210‧‧‧ lead frame
210a‧‧‧粗糙表面210a‧‧‧Rough surface
220‧‧‧發光二極體晶片220‧‧‧Light Diode Wafer
230‧‧‧封裝膠體230‧‧‧Package colloid
232‧‧‧外殼232‧‧‧Shell
232a‧‧‧第一凹陷232a‧‧‧first depression
232b‧‧‧第二凹陷232b‧‧‧second depression
234‧‧‧第一透光部234‧‧‧First light transmission department
236‧‧‧第二透光部236‧‧‧Second light transmission department
240‧‧‧焊線240‧‧‧welding line
250‧‧‧電子元件250‧‧‧Electronic components
A、B、C‧‧‧區域A, B, C‧‧‧ areas
L‧‧‧引腳L‧‧‧ pin
IL‧‧‧內引腳IL‧‧‧ pin
OL‧‧‧外引腳OL‧‧‧ external pins
S1、S2‧‧‧側壁S1, S2‧‧‧ side wall
圖1為習知發光二極體封裝之剖面示意圖。1 is a schematic cross-sectional view of a conventional light emitting diode package.
圖2與圖3為本發明第一實施例之發光二極體封裝之剖面示意圖。2 and 3 are schematic cross-sectional views showing a light emitting diode package according to a first embodiment of the present invention.
圖4為本發明第二實施例之發光二極體封裝之剖面示意圖。4 is a cross-sectional view showing a light emitting diode package according to a second embodiment of the present invention.
圖5為本發明第三實施例之發光二極體封裝之剖面示意圖。FIG. 5 is a cross-sectional view showing a light emitting diode package according to a third embodiment of the present invention.
圖6A至圖6D為第三實施例中外殼與導線架的立體示意圖。6A to 6D are perspective views of the outer casing and the lead frame in the third embodiment.
200‧‧‧發光二極體封裝200‧‧‧Light Emitter Package
210‧‧‧導線架210‧‧‧ lead frame
210a‧‧‧粗糙表面210a‧‧‧Rough surface
220‧‧‧發光二極體晶片220‧‧‧Light Diode Wafer
230‧‧‧封裝膠體230‧‧‧Package colloid
232‧‧‧外殼232‧‧‧Shell
232a‧‧‧凹陷232a‧‧‧ dent
234‧‧‧透光部234‧‧‧Transmission Department
240‧‧‧焊線240‧‧‧welding line
A、B、C‧‧‧區域A, B, C‧‧‧ areas
L‧‧‧引腳L‧‧‧ pin
IL‧‧‧內引腳IL‧‧‧ pin
OL‧‧‧外引腳OL‧‧‧ external pins
Claims (7)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097115580A TWI381549B (en) | 2008-04-28 | 2008-04-28 | Light-emitting diode package |
| US12/164,114 US8030674B2 (en) | 2008-04-28 | 2008-06-30 | Light-emitting diode package with roughened surface portions of the lead-frame |
| DE102008032967A DE102008032967B4 (en) | 2008-04-28 | 2008-07-10 | Light emitting diode unit |
| US13/154,306 US8471285B2 (en) | 2008-04-28 | 2011-06-06 | Light-emitting diode package including a cavity with a plurality of side-walls with different inclinations |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097115580A TWI381549B (en) | 2008-04-28 | 2008-04-28 | Light-emitting diode package |
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| Publication Number | Publication Date |
|---|---|
| TW200945622A TW200945622A (en) | 2009-11-01 |
| TWI381549B true TWI381549B (en) | 2013-01-01 |
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| TWI394298B (en) * | 2010-01-29 | 2013-04-21 | Advanced Optoelectronic Tech | Package of semiconductor light emitting device |
| TW201128808A (en) | 2010-02-03 | 2011-08-16 | Advanced Optoelectronic Tech | Package of semiconductor light emitting device |
| TWI540769B (en) | 2013-05-27 | 2016-07-01 | 億光電子工業股份有限公司 | Loading structure and lighting deivce |
| TWI534441B (en) * | 2014-12-30 | 2016-05-21 | 震揚集成科技股份有限公司 | Testing method |
| JP6650723B2 (en) * | 2015-10-16 | 2020-02-19 | 新光電気工業株式会社 | Lead frame, method of manufacturing the same, and semiconductor device |
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| TW200522390A (en) * | 2004-05-20 | 2005-07-01 | Lighthouse Technology Co Ltd | Light emitting diode package |
| US20060097366A1 (en) * | 2003-07-19 | 2006-05-11 | Ns Electronics Bangkok (1993) Ltd. | Semiconductor package including leadframe roughened with chemical etchant to prevent separation between leadframe and molding compound |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060097366A1 (en) * | 2003-07-19 | 2006-05-11 | Ns Electronics Bangkok (1993) Ltd. | Semiconductor package including leadframe roughened with chemical etchant to prevent separation between leadframe and molding compound |
| TW200522390A (en) * | 2004-05-20 | 2005-07-01 | Lighthouse Technology Co Ltd | Light emitting diode package |
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