TWI379392B - Package structure and method for chip on film - Google Patents

Package structure and method for chip on film Download PDF

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Publication number
TWI379392B
TWI379392B TW97123461A TW97123461A TWI379392B TW I379392 B TWI379392 B TW I379392B TW 97123461 A TW97123461 A TW 97123461A TW 97123461 A TW97123461 A TW 97123461A TW I379392 B TWI379392 B TW I379392B
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Taiwan
Prior art keywords
layer
flip
chip
film
wire
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Application number
TW97123461A
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Chinese (zh)
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TW201001641A (en
Inventor
Chia Hung Hsu
William Wang
Chung Cheng Chou
Chin Yung Chen
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Raydium Semiconductor Corp
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Priority to TW97123461A priority Critical patent/TWI379392B/en
Publication of TW201001641A publication Critical patent/TW201001641A/en
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Publication of TWI379392B publication Critical patent/TWI379392B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

1379392 九、發明說明: 【發明所屬之技術領域】 覆晶薄 本發明係關於-種覆龍結構以及覆 ^法,並且特別地,本發日謂於—種可增加耐折/膜封裝 法 ,封裝結構以及完成誠晶薄卿裝、_之覆^膜封裝方 【先前技術】 由於現今產品不_小魏、冑速 特性發展’ IC的封裝技術也朝此一方向不斷演 ^H(Liquid Crystal Display, Ic 中’覆晶薄膜封裝製程可以提供上述魏並且可用於軟性^ 路板’適合使用於液晶顯示器之驅動Ic封裝。 覆晶封裝技術泛指將晶片翻轉後,以面朝下之 金屬導體與基板進行接合。當應用於軟性基板時,其晶片可 固定於,社,雜*料體與祕*板電性雜.,因此 為覆晶 >專膜封袋(Chip On Film, COF)。 請參閱圖―,圖一係繪示先前技術中覆晶薄膜封裝結構 1的侧視圖。如圖一所示,覆晶薄膜封裝結構i之基板1〇上 設置導,層12,並且導線層π上進一步設置絕緣層14。晶 片16藉由金屬凸塊18與導線層12電性連接。晶片%以及 金屬凸塊18之周圍填充絕緣材料19,用以固定晶片16以及 金屬凸塊18,並且對固定晶片16以及金屬凸塊18進一步絕 緣。 以覆晶薄膜封裝之驅動1C趨向高接腳數以及更精細的導 線寬度。然而’在導線寬度越來越窄的狀況下,軟性基板彎 6 1379392 =之導而降低甚至失去傳輪功能。 ;;ί:Γ低。上述情況將對驅動ic之良率以及可⑶ ϊί:a—方面,由於單位面積内的接腳數以及ί線ί 生的熱量將更不容易_,因此 為覆晶_封裝結構之研魅點。 U遞也成 【發明内容】 因此,本發明之一範疇在於 構,可增加其結構的耐折度,以解決上述問題Ί顿封裝結 性基Ξ據:本發明之覆晶薄膜封裳結構包含軟 基板:ί、ΐ 緣層以及彈性層。導線層係形成於軟性 線声上,、獅=且其包含複數條導線。絕緣層係形成於導 性層可ί衝ii::而受時,彈 高導_峨導熱性或 薄膣_ 1^ 本具體^财,彈性層可以形成於覆曰 線资隹°】;量較不易逸散之區域,例如晶片或是接腳及Ϊ 藉由彈性體之高導熱性’可幫助覆晶薄膜封 产lx明之另一範嚀在於提供—種覆晶膜 ^加覆轉膜封裝結構的耐折度’簡決先ί技術之ΓΙ 7 1379392 根據一具體實施例,本發明之覆晶薄膜封裝方法 列步驟:首先,製備軟性基板;接著,於軟性基板 二〔 形成導線層’其中導線層包含複數條導線;之後,於 上形成絕緣層;最後,於絕緣層上形成對應至少一遙 性層。 等綠之弹 根據本具體貫施例之覆晶薄膜封裝方法所完成舜曰 膜封裝結構,當軟性基板^:到外力而彎曲時,彈靜俺 ,因彎曲而產生_變’使導線不致因過度ς f =耐=體實施例所形成之彈性層可增加覆晶_^^^ 根據另一具體實施例,上述之覆晶薄腹 口性層可為高傳導性(高導熱性^^法=; 性層可以設置於覆晶薄膜封裝結構上敎量較 ^易逸散之區域,例如’日日日片或是接腳及導紗 :由彈性體之高導熱性’可幫助覆晶薄膜•:構=散 ,發明詳述及 附圖式付到進—步的瞭解 【實施方式】 所 覆晶ϊί:芯發,之1體實施例之 結構2係顺封裝晶=覆晶薄膜封裝 含敕性基板2。、“層22、‘,2= 於本具體實施例中,導綠 λ 表面上,其包含複數條^。請^,以 8 1379392 多ΐίί組成,並不受限於其層狀結構,於本呈體實 釋圖示之二;二Τ二層以 J形成於導線層22之上“二= 於本具體實施例中,彈性層26係形成於 上,並且其於絕緣層24上之位置、、f層24之 = 之部位。因此,#軟性基板=== =:寺,彈性層26可緩衝對應導線的彎曲形;=作 ㈣生層26可增加覆晶薄膜封裝結構2 二 不至於因過度的彎曲形變而斷裂。此外,彈^ „ 板印刷或是其他適合製程軸於絕_ 24之上s。可猎由網 於=體實施例中,晶片3之功能面朝 並且,晶片3之功能面藉由導電凸塊% * ^ ’ 接,^而使軟性基板2Q可透過導電凸塊如= 片3溝通。此外,於實務中,晶片3 乂、f層22與曰曰 充絕緣材料28,以固定“ 3與導電凸^凸塊3G周圍可填 絕緣功能。於實務中,晶片3可為液晶顯 提供 用以驅動液晶顯示||&板之液晶分子旋轉的^、。動晶片’ 請蒼閱圖三,圖三係繪示根據本 之覆晶薄騎裝結構2的示意圖。 另—具體實施例 例與上-具體實施例不同處,在於’本具體實施 封裝結構2之彈性層26可延伸覆個、貫知例之覆晶薄膜 藉此,當軟性基板2〇受到外力1 ^ί 2膜封裝結構2。 緩衝覆晶薄膜封裝結構2之各部分 =彈性層26可 封裝結構2之各部分不至於因 9 1379392 層26可增加覆晶薄膜封裝結構2的耐折度。 5月參閱圖四,圖四係繪示根據本發明之另一具體實施例 之覆晶薄膜封裝結構2的示意圖。如圖四所示,本具體實施 例與上述具體實施例不同處,在於本具體實施例之覆晶薄膜 封裝結構2之絕緣層24可具有孔洞240。於實務中,孔洞 之數量端看使用者或是設計者需求而定,並不受限於本 4月曰所列舉之具體貫施例。此外,於實務中,孔洞Mo可 選擇性地貫穿絕緣層24。 於本具體實施例中,當彈性層26形成於絕緣層24以及 孔洞240上時,彈性層26可被填充進入孔洞24〇。此外,彈 =層26於本具體實施例中係高導熱性(高導熱性或高導電性) =料士。當彈性層26被填充入孔洞24〇而接近或接觸導線層 22 %,由於其高導熱性可幫助導線層22散埶。更進一步 Ϊ =另—具體實施例中,彈性層26也可覆蓋晶片3以及覆 結構2之其餘部分’以增加覆晶薄膜封裝結構2 接網’彈性層26也可具有高導電性,當彈性層% ,巧導線層22並且彈性層26本身接地時,可進 晶溥膜封裝結構2之電性屏蔽。 乂 a強復 於每導熱性或高導電性)之彈性層26, 於貝務中可使用軟性金屬以同時逵至丨丨並古 線層22之彎曲形變之功能。勒及緩衝導 卵be卿)或是金來製成。]而5㈣生層26可利用銀 絕緣;ίΪΐ線薄形成彈赚 基板受力而彎曲時’彈性層可緩;導;=2= 10 線因過度形變而斷, 度。此外,彈性声^且加覆晶薄膜封裝結構之时折 薄膜封裝結導性’也可更進—步增強覆晶 再(錢妨以及電性屏蔽效應。 覆晶ΐϊ:ΐ法據具體實施例之 封裝方法可完成耐折議膜 列步Ϊ圖illς4ί具體實施例之覆晶薄膜封裝方法包含下 板之表面’製備軟性基板;於步驟S42,於軟性基 s _包含複數條導線,·於 緣層上谢膚$ +la道上&形成絕緣層;以及,於步驟S46,於絕 封i結構「广導線之位置形成彈性層,以^成覆晶薄膜 组成於實施例所形成之導線層可為多條導線 .進—牛對苴;a狀結構。絕緣層可保護整體電路架構並 中,增曰層 另一方面,於另一具體實施例 二ίΐί2包含將晶片封裝於軟性基板 敕性其h矣a 1接曰曰片與導線層之步驟。上述封裝晶片於 連接於實務中可進—步包含以導電凸塊電性 步驟。此外’於實務中晶片〜== 度。 以驅動液晶顯不器面板之液晶分子旋轉的角 之覆日、i_f ίΐ曲應力之位置。#本具體實施例所完成 曰、,裝、。構之軟性基板受力而彎曲時,彈性體可緩 衝導線層之對應位置的彎曲形變,使導線“至^=二 形又而斷裂’進而增加覆晶薄膜封裝結構的耐折度 請參閱圖六 圖 之覆晶薄膜封#…係繪不根據本發明之另一具體實施例 施例與:膜圖。如圖六所示,本具體實 膜封裝方林;於_本频實補之覆晶薄 及,於步驟^Ϊ ’孔洞可選擇性地貫穿絕緣層,·以 層。… ,將_層填充至孔洞中以接近或接觸導線 亦即於ίϊί以=3與步驟S44可於同一製程中完成, 方面,步驟S曰460^t 孔洞同時形成於導線層上。另一 同時形成彈性體於^層=^^同中—製程中完成,亦即, 明書所列舉之具體實施例。飞又°十者而求而疋,亚不限於本說 ^具體實施例中,·層可為高導敎性材料,因此, 以接近“導導 口:覆晶薄“結=分若== 覆晶溥膜封I结構整體的散熱效率。 也了進W曰加 於另—具體實施例中,彈性居Aw或古 覆日日4蘭裝結構之電性屏蔽亦可進—步被加強。 彈性高傳導性(高導電性或高導熱性)之 來ϋ 舉例而言’彈性層可利用銀膠或是金 12 1379592 綜上所述,本發明之覆晶薄膜封裝方法 心緣層上對應㈣裂之導線的位置,以層於 基板受力而彎曲時’彈性層可緩ίίϊϊ織ίί 構之耐折度。此外,彈性層若具有日結 增強覆晶薄膜封裝結構之散熱效果以及電性屏蔽效應。、步 …相較於先前技術,本發明之覆晶薄膜 缚膜封裝方法可以藉由彈性層緩衝導線受力^ 覆晶 :ΐϊίΐϊ膜封裝結構整體的耐折度’使其不因彎ΐ‘ί ^導線斷裂甚至影響其良率。此外,若彈性声H =1379392 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a structure and a coating method, and in particular, the present invention can increase the folding/film encapsulation method. The package structure and the completion of the company's packaging technology [previous technology] Because today's products are not _ Xiao Wei, the development of idle characteristics 'IC packaging technology is also constantly moving in this direction ^H (Liquid Crystal Display, Ic 'Flip-chip film packaging process can provide the above-mentioned Wei and can be used for flexible board' is suitable for driving Ic package of liquid crystal display. Flip-chip packaging technology refers to the metal conductor facing down after flipping the wafer. Bonding to the substrate. When applied to a flexible substrate, the wafer can be fixed to the ceramic, miscellaneous material and the secret plate, so it is a flip chip > Chip On Film (COF) Referring to the drawings, FIG. 1 is a side view showing a flip-chip package structure 1 of the prior art. As shown in FIG. 1, a substrate, a layer 12, and a wiring layer are disposed on a substrate 1 of a flip-chip package structure i. Further insulation on π 14. The wafer 16 is electrically connected to the wire layer 12 by metal bumps 18. The wafer % and the metal bumps 18 are filled with an insulating material 19 for fixing the wafer 16 and the metal bumps 18, and for fixing the wafer 16 and the metal. The bumps 18 are further insulated. The driving 1C of the flip chip package tends to a high number of pins and a finer wire width. However, in the case where the wire width is narrower, the flexible substrate bends 6 1379392 = Loss of the pass function. ;; ί: Γ low. The above situation will drive the yield of ic and can be (3) ϊί: a - aspect, because the number of pins per unit area and the heat generated by ί line ί will be even easier _ Therefore, it is a fascinating point of the flip chip _ package structure. U Dicheng is also a subject of the invention. Therefore, one aspect of the invention lies in the structure, which can increase the folding resistance of the structure to solve the above problems. According to the present invention, the flip-chip film sealing structure of the present invention comprises a soft substrate: ί, a rim layer and an elastic layer. The wire layer is formed on a soft line sound, and the lion = and it comprises a plurality of wires. The insulating layer is formed on The guiding layer can be ii ii:: When it is time, the high conductivity _ 峨 thermal conductivity or thin 膣 _ 1 ^ This specific ^ wealth, the elastic layer can be formed in the overlay line 隹 】 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;另一 By the high thermal conductivity of the elastomer, it can help the flip-chip film to seal the other. The other way is to provide the flip-chip film and the folding resistance of the film-transferred package structure. 1379392 According to a specific embodiment, the flip chip packaging method of the present invention comprises the steps of: firstly, preparing a flexible substrate; then, on the flexible substrate 2, forming a wiring layer, wherein the wiring layer comprises a plurality of wires; and then forming an insulating layer thereon Finally, at least one remote layer is formed on the insulating layer. According to the flip-chip packaging method of the specific embodiment, the enamel film encapsulation structure is completed. When the flexible substrate is bent to an external force, the squeak is static, and the crease is caused by the bending. Excessive ς f = resistance = elastic layer formed by the body embodiment can increase flip chip _ ^ ^ ^ According to another embodiment, the above-mentioned flip chip thin abdominal layer can be highly conductive (high thermal conductivity ^ ^ method =; The layer can be placed on the flip-chip film package structure where the amount of defects is relatively easy to escape, such as 'day and day film or pin and guide yarn: high thermal conductivity of the elastomer' can help flip chip •: Structure = Dispersion, Detailed Description of the Invention and Drawings for the Step-by-Step Understanding [Embodiment] The coated crystal ϊ: core hair, the structure of the first embodiment is 2 compliant package crystal = flip chip package containing敕 substrate 2, "layer 22, ', 2 = in the specific embodiment, on the green λ surface, it contains a plurality of ^ ^ Please ^, composed of 8 1379392 ΐ ίί, is not limited to its layer The structure is shown in the second embodiment of the present invention; the second layer and the second layer are formed on the wire layer 22 by J. "Two = in this embodiment The elastic layer 26 is formed on the upper portion and at the position on the insulating layer 24, and the portion of the f layer 24. Therefore, #软 substrate====: Temple, the elastic layer 26 can buffer the curved shape of the corresponding wire ; = (4) The green layer 26 can increase the flip-chip film encapsulation structure 2 and it will not be broken due to excessive bending deformation. In addition, the slab printing or other suitable process axis is above s 24 s. In the embodiment of the body, the function of the wafer 3 faces and the functional surface of the wafer 3 is connected by the conductive bumps %*^', so that the flexible substrate 2Q can communicate through the conductive bumps such as the =3. In practice, the wafer 3, the f layer 22 and the buffer insulating material 28 are used to fix the insulating function of the "3" and the conductive bumps 3G. In practice, the wafer 3 can be provided for liquid crystal display. Driving the liquid crystal display||& the liquid crystal molecules of the board rotates. The moving wafer' Please read Figure 3, and Figure 3 shows the schematic diagram of the flip-chip thin riding structure 2 according to the present. The difference between the above and the specific embodiments is that the elastic layer 26 of the package structure 2 can be extended. By way of example, when the flexible substrate 2 is subjected to an external force 1 ^ 2 2 film package structure 2, each part of the buffered flip chip package structure 2 = elastic layer 26 can be packaged structure 2 As for the 9 1379392 layer 26, the folding resistance of the flip chip package structure 2 can be increased. Referring to Figure 4, Figure 4 is a schematic view showing a flip chip package structure 2 according to another embodiment of the present invention. As shown in FIG. 4, the specific embodiment differs from the above embodiment in that the insulating layer 24 of the flip chip package structure 2 of the present embodiment may have a hole 240. In practice, the number of holes is viewed by the user or It is determined by the designer's needs and is not limited to the specific examples listed in this April. Further, in practice, the holes Mo may selectively penetrate the insulating layer 24. In this embodiment, when the elastic layer 26 is formed on the insulating layer 24 and the holes 240, the elastic layer 26 can be filled into the holes 24. In addition, the bomb = layer 26 is highly thermally conductive (high thermal conductivity or high electrical conductivity) in this embodiment = material. When the elastic layer 26 is filled into the holes 24 to approach or contact the wire layer 22%, the wire layer 22 can be dissipated due to its high thermal conductivity. Further, in another embodiment, the elastic layer 26 may also cover the wafer 3 and the rest of the covering structure 2 to increase the flip-chip film encapsulation structure. 2 The mesh layer 'elastic layer 26 may also have high conductivity, when elastic When the layer %, the wire layer 22 and the elastic layer 26 itself are grounded, the electrical shielding of the wafer package structure 2 can be performed. The elastic layer 26 is reinforced with each of the thermal conductivity or high conductivity, and a soft metal can be used in the peripheral to simultaneously smash the function of the curved deformation of the ruthenium layer 22 . And the buffer guides the egg, or gold. And the 5 (four) green layer 26 can be insulated with silver; the thin line is formed by the thin film. When the substrate is stressed and bent, the elastic layer can be slowed; the guide; = 2 = 10 lines are broken due to excessive deformation. In addition, the elastic sound ^ and the film-sealed structure of the folded film package can also be more advanced to enhance the flip-chip (the molecular and electrical shielding effect. The flip chip: the method according to the specific embodiment The packaging method can complete the folding-resistant film array. The flip-chip film packaging method of the specific embodiment includes the surface of the lower plate to prepare a flexible substrate; in step S42, the soft substrate s includes a plurality of wires, On the layer, the skin layer is formed on the surface of the film +; and, in step S46, an elastic layer is formed on the position of the wide-area wire in the structure of the insulating layer, and the layer of the wire formed in the embodiment is formed into a layer of the wire formed in the embodiment. For a plurality of wires. Into the cow-to-bee; a-like structure. The insulating layer can protect the overall circuit structure and enhance the germanium layer. On the other hand, in another embodiment, the package includes the chip packaged on the flexible substrate. H矣a 1 is a step of connecting the ruthenium and the wire layer. The packaged wafer can be further connected to the practice to include a conductive bump electrical step. In addition, in the practice, the wafer is ~== degrees. Liquid crystal molecules The position of the corner of the rotation, the position of the i_f ΐ ΐ 应力 。 。 # # # # # # # # # # # # # # 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本To make the wire "to ^^2 shape and break" and thereby increase the folding resistance of the flip chip package structure, please refer to the flip chip seal of Fig. 6 for drawing and not according to another embodiment of the present invention. : film diagram. As shown in Figure 6, the specific solid film encapsulation of the forest; in the _ this frequency is complemented by the laminating thin, in the step ^ Ϊ 'hole can selectively penetrate the insulating layer, · layer .... Filling the _ layer into the hole to approach or contact the wire is also completed in the same process as step S44, and the step S 曰 460^t hole is simultaneously formed on the wire layer. The body is completed in the process of ^ layer = ^ ^ in the same process, that is, the specific examples listed in the book. The fly is also ten, and the request is not limited to the specific embodiment, the layer can be Is a highly conductive material, therefore, to be close to the "guide port: flip-chip thin" knot = minute if = = The heat dissipation efficiency of the flip-chip enamel film I structure as a whole. Also added to the other specific embodiment, the electrical shielding of the elastic AW or the ancient day 4 blue structure can be further strengthened. Elastic high conductivity (high conductivity or high thermal conductivity) ϋ For example, 'elastic layer can use silver glue or gold 12 1379592. In summary, the flip chip coating method of the present invention corresponds to the core layer (4) The position of the cracked wire, when the layer is bent by the force of the substrate, the 'elastic layer can be loosened and woven. The elastic layer has the heat dissipation effect and electrical property of the solar junction-enhanced crystalline film package structure. Shielding effect, step... Compared with the prior art, the flip-chip film encapsulating method of the present invention can be covered by the elastic layer buffering wire: the overall folding resistance of the 封装ίΐϊ film packaging structure is not caused by the bending ΐ 'ί ^ wire breakage even affects its yield. In addition, if the elastic sound H =

Uli進—步增強覆晶薄膜封裝結構的散熱: 述本=======清輪 施!刺本發明之範蜂加以限制。相反實 的轉,乂===: 1379392 【圖式簡單說明】Uli step-enhanced heat dissipation of the flip-chip film package structure: Description =======清轮 Shi! The invention of the invention is limited. The opposite is true, 乂===: 1379392 [Simple description]

圖一係繪示先前技術中覆晶薄膜封裝結構的側視圖。 結構根據本發明之—具體實施例之覆晶薄膜封裝 圖二係續'示根據本發明另一 結構的示意圖。 具體實施例之覆晶薄膜封裝 圖四係繪示根據本發明之另 裝結構的不意圖。 一具體實施例之覆晶薄膜封 圖五係纟會示根據本發明之一 方法的步騾流程圖。 具體實施例之覆晶薄膜封裝 圖六係警示根據本發明之另 裝方法的步驟流程圖。 —具體實施例之覆晶薄膜封 【主要元件符號說明】 1:覆晶薄膜封裝結構 10 :基板 12 :導線層 14 :絕緣層 16 ·晶片 18 :金屬凸塊 19 .絕緣材料 2·覆晶薄膜封裝結構 20 :軟性基板 22:導線層 24 :絕緣層 26 :彈性層 28 :絕緣材料 14 1379392 200 :表面 3 :晶片 S40〜S46 :流程步驟 240 :孔洞 30 :導電凸塊 S440、S460 :流程步驟BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a side elevational view of a prior art flip chip package structure. Structure of a flip chip package in accordance with the present invention - Figure 2 is a schematic view showing another structure in accordance with the present invention. The flip chip package of the specific embodiment Fig. 4 is a schematic view showing an alternative structure according to the present invention. A flip-chip film seal of a specific embodiment will show a flow chart of a step in accordance with one of the methods of the present invention. The flip chip package of the specific embodiment is a flow chart showing the steps of the alternative method according to the present invention. - Flip-coated film package of a specific embodiment [Description of main components] 1: Flip-chip film package structure 10: Substrate 12: Wire layer 14: Insulation layer 16 • Wafer 18: Metal bumps 19. Insulation material 2·Cladding film Package structure 20: flexible substrate 22: wire layer 24: insulation layer 26: elastic layer 28: insulation material 14 1379392 200: surface 3: wafers S40 to S46: process step 240: hole 30: conductive bumps S440, S460: process steps

1515

Claims (1)

16、⑽,,〜 17 方法, 其中該 18、=範圍第17項所述之覆晶薄膜封裝方法,進一步包 於,,緣層上軸至少-孔洞;以及 將該高傳導性材料填充於該至少— 該導線層。 孔洞中以接近或接觸 19、 20、 如申請專利範圍第17項所述之覆晶薄膜封 傳‘性材料係銀膠(silver epoxy)。 如申請專利範圍第17項所述之覆晶薄膜封裝 性層接地。 、由’ "ti* «4? 共T §亥咼 其中該彈 1816. The method of claim 11, wherein the method of packaging a flip chip according to claim 17, further comprising: at least a hole in the upper layer of the edge layer; and filling the high conductivity material in the method At least - the layer of wire. The flip-chip is in close proximity to or in contact with 19, 20, and the flip-chip film as described in claim 17 of the patent application encapsulates the 'spark material' silver epoxy. The flip chip encapsulation layer described in claim 17 is grounded. By ' "ti* «4? Total T § 咼 咼 where the bomb 18
TW97123461A 2008-06-24 2008-06-24 Package structure and method for chip on film TWI379392B (en)

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Publication number Priority date Publication date Assignee Title
US8791008B2 (en) * 2012-03-21 2014-07-29 Stats Chippac, Ltd. Semiconductor device and method of forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief
JP6642552B2 (en) * 2017-11-08 2020-02-05 日亜化学工業株式会社 Light emitting device
CN108993835A (en) * 2018-07-16 2018-12-14 成都捷翼电子科技有限公司 A kind of novel segment difference fill method

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