TWI368222B - Method of determining binary signal of memory cell and apparatus thereof - Google Patents
Method of determining binary signal of memory cell and apparatus thereofInfo
- Publication number
- TWI368222B TWI368222B TW097107828A TW97107828A TWI368222B TW I368222 B TWI368222 B TW I368222B TW 097107828 A TW097107828 A TW 097107828A TW 97107828 A TW97107828 A TW 97107828A TW I368222 B TWI368222 B TW I368222B
- Authority
- TW
- Taiwan
- Prior art keywords
- memory cell
- binary signal
- determining binary
- determining
- signal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/563—Multilevel memory reading aspects
- G11C2211/5634—Reference cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070085005A KR101348364B1 (ko) | 2007-08-23 | 2007-08-23 | 메모리 셀의 이진 신호 판정 방법 및 장치 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200910351A TW200910351A (en) | 2009-03-01 |
| TWI368222B true TWI368222B (en) | 2012-07-11 |
Family
ID=40378316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW097107828A TWI368222B (en) | 2007-08-23 | 2008-03-06 | Method of determining binary signal of memory cell and apparatus thereof |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8145968B2 (zh) |
| KR (1) | KR101348364B1 (zh) |
| TW (1) | TWI368222B (zh) |
| WO (1) | WO2009025432A1 (zh) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9129434B2 (en) * | 2008-05-29 | 2015-09-08 | Robert R. Taylor | Method and system for 3D surface deformation fitting |
| KR101919902B1 (ko) | 2011-10-18 | 2018-11-20 | 삼성전자 주식회사 | 메모리 장치의 데이터 독출 방법 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5095452A (en) | 1988-05-30 | 1992-03-10 | Nippondenso Co., Ltd. | Device for accurately displaying physical measure by adjusting the outputs from pulse counters |
| US6839875B2 (en) | 1996-10-18 | 2005-01-04 | Micron Technology, Inc. | Method and apparatus for performing error correction on data read from a multistate memory |
| JP3165101B2 (ja) | 1998-03-05 | 2001-05-14 | 日本電気アイシーマイコンシステム株式会社 | 多値式半導体メモリ装置およびその不良救済方法 |
| KR100322542B1 (ko) | 1999-08-11 | 2002-03-18 | 윤종용 | 파이프 라인상의 고속동작을 구현하는 ｅｃｃ 회로를 구비하는동기식 반도체 메모리장치 및 이 동기식 반도체 메모리장치의 에러 체크 및 정정방법 |
| JP3447638B2 (ja) | 1999-12-24 | 2003-09-16 | 日本電気株式会社 | 半導体装置のテスト方法及びシステム並びに記録媒体 |
| DE10229802B3 (de) | 2002-07-03 | 2004-01-08 | Infineon Technologies Ag | Testschaltung und Verfahren zum Testen einer integrierten Speicherschaltung |
| WO2004040581A1 (ja) | 2002-10-15 | 2004-05-13 | Sony Corporation | メモリ装置、動きベクトルの検出装置および検出方法 |
| EP1473739A1 (en) | 2003-04-29 | 2004-11-03 | Dialog Semiconductor GmbH | Flash memory with pre-detection for data loss |
| JP4270994B2 (ja) | 2003-09-29 | 2009-06-03 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| US7139864B2 (en) | 2003-12-30 | 2006-11-21 | Sandisk Corporation | Non-volatile memory and method with block management system |
| US7274596B2 (en) | 2004-06-30 | 2007-09-25 | Micron Technology, Inc. | Reduction of adjacent floating gate data pattern sensitivity |
| US7613043B2 (en) * | 2006-05-15 | 2009-11-03 | Apple Inc. | Shifting reference values to account for voltage sag |
| US7894269B2 (en) * | 2006-07-20 | 2011-02-22 | Sandisk Corporation | Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells |
-
2007
- 2007-08-23 KR KR1020070085005A patent/KR101348364B1/ko active IP Right Grant
-
2008
- 2008-02-20 US US12/034,089 patent/US8145968B2/en active Active
- 2008-02-28 WO PCT/KR2008/001153 patent/WO2009025432A1/en active Application Filing
- 2008-03-06 TW TW097107828A patent/TWI368222B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR101348364B1 (ko) | 2014-01-07 |
| WO2009025432A1 (en) | 2009-02-26 |
| US8145968B2 (en) | 2012-03-27 |
| KR20090020326A (ko) | 2009-02-26 |
| US20090055700A1 (en) | 2009-02-26 |
| TW200910351A (en) | 2009-03-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |