TWI365391B - Circuit layout method and layout circuit - Google Patents

Circuit layout method and layout circuit

Info

Publication number
TWI365391B
TWI365391B TW097130790A TW97130790A TWI365391B TW I365391 B TWI365391 B TW I365391B TW 097130790 A TW097130790 A TW 097130790A TW 97130790 A TW97130790 A TW 97130790A TW I365391 B TWI365391 B TW I365391B
Authority
TW
Taiwan
Prior art keywords
circuit
layout
layout method
circuit layout
layout circuit
Prior art date
Application number
TW097130790A
Other languages
English (en)
Other versions
TW200943110A (en
Inventor
Tung Kai Tsai
Chih Ching Lin
Original Assignee
Mediatek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mediatek Inc filed Critical Mediatek Inc
Publication of TW200943110A publication Critical patent/TW200943110A/zh
Application granted granted Critical
Publication of TWI365391B publication Critical patent/TWI365391B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/06—Spare resources, e.g. for permanent fault suppression
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW097130790A 2008-04-01 2008-08-13 Circuit layout method and layout circuit TWI365391B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/060,298 US7949988B2 (en) 2008-04-01 2008-04-01 Layout circuit having a combined tie cell

Publications (2)

Publication Number Publication Date
TW200943110A TW200943110A (en) 2009-10-16
TWI365391B true TWI365391B (en) 2012-06-01

Family

ID=41119069

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097130790A TWI365391B (en) 2008-04-01 2008-08-13 Circuit layout method and layout circuit

Country Status (3)

Country Link
US (1) US7949988B2 (zh)
CN (1) CN101552269B (zh)
TW (1) TWI365391B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9846755B2 (en) 2015-04-16 2017-12-19 Taiwan Semiconductor Manufacturing Company Limited Method for cell placement in semiconductor layout and system thereof

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7546568B2 (en) * 2005-12-19 2009-06-09 Lsi Corporation Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage
IT1392913B1 (it) * 2008-12-30 2012-04-02 St Microelectronics Srl Metodo per implementare variazioni di funzionalita' di un layout di progetto di un dispositivo integrato, in particolare un sistema su singolo chip o system-on-chip mediante celle di riempimento programmabili tramite maschera
US8234612B2 (en) * 2010-08-25 2012-07-31 International Business Machines Corporation Cone-aware spare cell placement using hypergraph connectivity analysis
US8266566B2 (en) 2010-09-10 2012-09-11 International Business Machines Corporation Stability-dependent spare cell insertion
US8560997B1 (en) * 2012-07-25 2013-10-15 Taiwan Semiconductor Manufacturing Company Limited Conditional cell placement
US8826212B2 (en) * 2012-12-06 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed
JP6453732B2 (ja) 2015-09-11 2019-01-16 株式会社東芝 半導体集積回路
JP6407900B2 (ja) 2016-02-04 2018-10-17 株式会社東芝 半導体集積回路
US10430541B2 (en) * 2016-05-18 2019-10-01 Synopsys, Inc. Always-on tie cells for low power designs and method of manufacture thereof
US10127340B2 (en) 2016-09-30 2018-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell layout, semiconductor device having engineering change order (ECO) cells and method
KR102101537B1 (ko) * 2017-07-06 2020-04-17 매그나칩 반도체 유한회사 타이하이 및 타이로우 회로
JP2021101512A (ja) 2019-12-24 2021-07-08 キオクシア株式会社 半導体集積回路
US20230237239A1 (en) * 2022-01-25 2023-07-27 Cortina Access, Inc. Circuit unit having adjustable driving strength capability in chip and method thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5623420A (en) * 1994-11-16 1997-04-22 Sun Microsystems, Inc. Method and apparatus to distribute spare cells within a standard cell region of an integrated circuit
US6380593B1 (en) * 1998-12-30 2002-04-30 Texas Instruments Incorporated Automated well-tie and substrate contact insertion methodology
SG86407A1 (en) * 2000-06-13 2002-02-19 Texas Instr Singapore Pte Ltd Regenerative tie-high tie-low cell
US6814296B2 (en) * 2001-05-01 2004-11-09 Lattice Semiconductor Corp. Integrated circuit and associated design method with antenna error control using spare gates
US7191424B2 (en) * 2004-08-30 2007-03-13 Lsi Logic Corporation Special tie-high/low cells for single metal layer route changes
US7231625B2 (en) * 2004-09-28 2007-06-12 Lsi Corporation Method and apparatus for use of hidden decoupling capacitors in an integrated circuit design
JP2006222369A (ja) * 2005-02-14 2006-08-24 Oki Electric Ind Co Ltd 半導体集積回路、および、半導体集積回路の配置配線方法
US7221183B2 (en) * 2005-02-23 2007-05-22 Taiwan Semiconductor Manufacturing Company Tie-high and tie-low circuit
US7663851B2 (en) * 2005-05-25 2010-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Tie-off circuit with ESD protection features
US7546568B2 (en) * 2005-12-19 2009-06-09 Lsi Corporation Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9846755B2 (en) 2015-04-16 2017-12-19 Taiwan Semiconductor Manufacturing Company Limited Method for cell placement in semiconductor layout and system thereof
TWI662429B (zh) * 2015-04-16 2019-06-11 台灣積體電路製造股份有限公司 半導體佈局中單元配置的方法及其系統

Also Published As

Publication number Publication date
CN101552269B (zh) 2011-03-30
US20090249273A1 (en) 2009-10-01
US7949988B2 (en) 2011-05-24
TW200943110A (en) 2009-10-16
CN101552269A (zh) 2009-10-07

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