TWI362613B - System and method for validating a memory file that links speculative results of load operations to register values - Google Patents

System and method for validating a memory file that links speculative results of load operations to register values Download PDF

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Publication number
TWI362613B
TWI362613B TW094114201A TW94114201A TWI362613B TW I362613 B TWI362613 B TW I362613B TW 094114201 A TW094114201 A TW 094114201A TW 94114201 A TW94114201 A TW 94114201A TW I362613 B TWI362613 B TW I362613B
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Taiwan
Prior art keywords
job
load
speculative
address
storage
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TW094114201A
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English (en)
Chinese (zh)
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TW200606709A (en
Inventor
Benjamin T Sander
Krishnan V Ramani
Ramsey W Haddad
Mitchell Alsup
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Globalfoundries Us Inc
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Publication of TW200606709A publication Critical patent/TW200606709A/zh
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Publication of TWI362613B publication Critical patent/TWI362613B/zh

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
TW094114201A 2004-05-05 2005-05-03 System and method for validating a memory file that links speculative results of load operations to register values TWI362613B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/839,474 US7263600B2 (en) 2004-05-05 2004-05-05 System and method for validating a memory file that links speculative results of load operations to register values

Publications (2)

Publication Number Publication Date
TW200606709A TW200606709A (en) 2006-02-16
TWI362613B true TWI362613B (en) 2012-04-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW094114201A TWI362613B (en) 2004-05-05 2005-05-03 System and method for validating a memory file that links speculative results of load operations to register values

Country Status (7)

Country Link
US (1) US7263600B2 (https=)
JP (1) JP2007536626A (https=)
CN (1) CN100424635C (https=)
DE (1) DE112004002848B4 (https=)
GB (1) GB2429557B (https=)
TW (1) TWI362613B (https=)
WO (1) WO2005111794A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI652618B (zh) 2013-03-15 2019-03-01 英特爾股份有限公司 用以管理儲存在硬體結構中的元素的方法與設備

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7571304B2 (en) * 2005-03-18 2009-08-04 Sun Microsystems, Inc. Generation of multiple checkpoints in a processor that supports speculative execution
US7376817B2 (en) * 2005-08-10 2008-05-20 P.A. Semi, Inc. Partial load/store forward prediction
US20080010440A1 (en) * 2006-07-05 2008-01-10 International Business Machines Corporation Means for supporting and tracking a large number of in-flight stores in an out-of-order processor
US20080010441A1 (en) * 2006-07-05 2008-01-10 International Business Machines Corporation Means for supporting and tracking a large number of in-flight loads in an out-of-order processor
US7624253B2 (en) * 2006-10-25 2009-11-24 Arm Limited Determining register availability for register renaming
US20080162889A1 (en) * 2007-01-03 2008-07-03 International Business Machines Corporation Method and apparatus for implementing efficient data dependence tracking for multiprocessor architectures
US7689812B2 (en) * 2007-02-14 2010-03-30 International Business Machines Corporation Method and system for restoring register mapper states for an out-of-order microprocessor
US9069672B2 (en) * 2009-06-12 2015-06-30 Intel Corporation Extended fast memory access in a multiprocessor computer system
US8521992B2 (en) * 2009-12-22 2013-08-27 International Business Machines Corporation Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
US8468325B2 (en) 2009-12-22 2013-06-18 International Business Machines Corporation Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
US9135014B2 (en) * 2012-02-15 2015-09-15 Freescale Semiconductor, Inc Data processing system with latency tolerance execution
US9996348B2 (en) * 2012-06-14 2018-06-12 Apple Inc. Zero cycle load
US10467010B2 (en) * 2013-03-15 2019-11-05 Intel Corporation Method and apparatus for nearest potential store tagging
US10152327B2 (en) 2013-03-15 2018-12-11 Intel Corporation Apparatus for gating a load operation based on entries of a prediction table
US9471480B2 (en) 2013-12-02 2016-10-18 The Regents Of The University Of Michigan Data processing apparatus with memory rename table for mapping memory addresses to registers
GB2518022B (en) * 2014-01-17 2015-09-23 Imagination Tech Ltd Stack saved variable value prediction
US11068271B2 (en) 2014-07-28 2021-07-20 Apple Inc. Zero cycle move using free list counts
GB2532232A (en) * 2014-11-12 2016-05-18 Ibm Verifying a graph-based coherency verification tool
US9575897B2 (en) 2015-07-09 2017-02-21 Centipede Semi Ltd. Processor with efficient processing of recurring load instructions from nearby memory addresses
US20170010973A1 (en) * 2015-07-09 2017-01-12 Centipede Semi Ltd. Processor with efficient processing of load-store instruction pairs
CN107710153B (zh) * 2015-07-09 2022-03-01 森蒂彼得塞米有限公司 具有有效的存储器访问的处理器
US10185561B2 (en) * 2015-07-09 2019-01-22 Centipede Semi Ltd. Processor with efficient memory access
US10331357B2 (en) * 2016-08-19 2019-06-25 Advanced Micro Devices, Inc. Tracking stores and loads by bypassing load store units
US10908911B2 (en) 2017-08-18 2021-02-02 International Business Machines Corporation Predicting and storing a predicted target address in a plurality of selected locations
US10884747B2 (en) 2017-08-18 2021-01-05 International Business Machines Corporation Prediction of an affiliated register
US11150908B2 (en) 2017-08-18 2021-10-19 International Business Machines Corporation Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence
US10534609B2 (en) 2017-08-18 2020-01-14 International Business Machines Corporation Code-specific affiliated register prediction
US10719328B2 (en) 2017-08-18 2020-07-21 International Business Machines Corporation Determining and predicting derived values used in register-indirect branching
US10884745B2 (en) 2017-08-18 2021-01-05 International Business Machines Corporation Providing a predicted target address to multiple locations based on detecting an affiliated relationship
US10884746B2 (en) 2017-08-18 2021-01-05 International Business Machines Corporation Determining and predicting affiliated registers based on dynamic runtime control flow analysis
US11150904B2 (en) 2017-08-18 2021-10-19 International Business Machines Corporation Concurrent prediction of branch addresses and update of register contents
US10705973B2 (en) 2017-09-19 2020-07-07 International Business Machines Corporation Initializing a data structure for use in predicting table of contents pointer values
US10620955B2 (en) 2017-09-19 2020-04-14 International Business Machines Corporation Predicting a table of contents pointer value responsive to branching to a subroutine
US11061575B2 (en) 2017-09-19 2021-07-13 International Business Machines Corporation Read-only table of contents register
US10896030B2 (en) 2017-09-19 2021-01-19 International Business Machines Corporation Code generation relating to providing table of contents pointer values
US10725918B2 (en) 2017-09-19 2020-07-28 International Business Machines Corporation Table of contents cache entry having a pointer for a range of addresses
US10884929B2 (en) 2017-09-19 2021-01-05 International Business Machines Corporation Set table of contents (TOC) register instruction
US10713050B2 (en) 2017-09-19 2020-07-14 International Business Machines Corporation Replacing Table of Contents (TOC)-setting instructions in code with TOC predicting instructions
US10620961B2 (en) * 2018-03-30 2020-04-14 Intel Corporation Apparatus and method for speculative conditional move operation
US11334485B2 (en) * 2018-12-14 2022-05-17 Eta Scale Ab System and method for dynamic enforcement of store atomicity
US11061683B2 (en) * 2019-06-13 2021-07-13 Microsoft Technology Licensing, Llc Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor
US11200062B2 (en) 2019-08-26 2021-12-14 Apple Inc. History file for previous register mapping storage and last reference indication
US11416254B2 (en) 2019-12-05 2022-08-16 Apple Inc. Zero cycle load bypass in a decode group
US11392387B2 (en) 2020-11-04 2022-07-19 Microsoft Technology Licensing, Llc Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778219A (en) * 1990-12-14 1998-07-07 Hewlett-Packard Company Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations
US5428807A (en) * 1993-06-17 1995-06-27 Digital Equipment Corporation Method and apparatus for propagating exception conditions of a computer system
US5584009A (en) * 1993-10-18 1996-12-10 Cyrix Corporation System and method of retiring store data from a write buffer
US5452426A (en) * 1994-01-04 1995-09-19 Intel Corporation Coordinating speculative and committed state register source data and immediate source data in a processor
US5799179A (en) * 1995-01-24 1998-08-25 International Business Machines Corporation Handling of exceptions in speculative instructions
US6237082B1 (en) * 1995-01-25 2001-05-22 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received
US5751983A (en) * 1995-10-03 1998-05-12 Abramson; Jeffrey M. Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations
US5892936A (en) * 1995-10-30 1999-04-06 Advanced Micro Devices, Inc. Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register
US6108769A (en) * 1996-05-17 2000-08-22 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US5781752A (en) * 1996-12-26 1998-07-14 Wisconsin Alumni Research Foundation Table based data speculation circuit for parallel processing computer
US6021485A (en) * 1997-04-10 2000-02-01 International Business Machines Corporation Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching
US5845103A (en) * 1997-06-13 1998-12-01 Wisconsin Alumni Research Foundation Computer with dynamic instruction reuse
US6065103A (en) * 1997-12-16 2000-05-16 Advanced Micro Devices, Inc. Speculative store buffer
US6044430A (en) * 1997-12-17 2000-03-28 Advanced Micro Devices Inc. Real time interrupt handling for superscalar processors
US6041405A (en) * 1997-12-18 2000-03-21 Advanced Micro Devices, Inc. Instruction length prediction using an instruction length pattern detector
US6112296A (en) * 1997-12-18 2000-08-29 Advanced Micro Devices, Inc. Floating point stack manipulation using a register map and speculative top of stack values
US6175910B1 (en) * 1997-12-19 2001-01-16 International Business Machines Corportion Speculative instructions exection in VLIW processors
JPH11212788A (ja) * 1998-01-28 1999-08-06 Toshiba Corp プロセッサのデータ供給装置
US6202204B1 (en) * 1998-03-11 2001-03-13 Intel Corporation Comprehensive redundant load elimination for architectures supporting control and data speculation
US6108770A (en) * 1998-06-24 2000-08-22 Digital Equipment Corporation Method and apparatus for predicting memory dependence using store sets
US6463580B1 (en) * 1998-11-18 2002-10-08 Intel Corporation Parallel processing utilizing highly correlated data values
US6349382B1 (en) * 1999-03-05 2002-02-19 International Business Machines Corporation System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order
US6658554B1 (en) * 1999-03-09 2003-12-02 Wisconsin Alumni Res Found Electronic processor providing direct data transfer between linked data consuming instructions
US6266744B1 (en) * 1999-05-18 2001-07-24 Advanced Micro Devices, Inc. Store to load forwarding using a dependency link file
US6393536B1 (en) * 1999-05-18 2002-05-21 Advanced Micro Devices, Inc. Load/store unit employing last-in-buffer indication for rapid load-hit-store
US6662280B1 (en) * 1999-11-10 2003-12-09 Advanced Micro Devices, Inc. Store buffer which forwards data based on index and optional way match
US6438673B1 (en) * 1999-12-30 2002-08-20 Intel Corporation Correlated address prediction
US6643767B1 (en) * 2000-01-27 2003-11-04 Kabushiki Kaisha Toshiba Instruction scheduling system of a processor
US6675287B1 (en) * 2000-04-07 2004-01-06 Ip-First, Llc Method and apparatus for store forwarding using a response buffer data path in a write-allocate-configurable microprocessor
DE10121792C2 (de) * 2000-05-26 2003-09-25 Ibm Universelle Ladeadresse/Wertevorhersageschema
US6671780B1 (en) * 2000-05-31 2003-12-30 Intel Corporation Modified least recently allocated cache replacement method and apparatus that allows skipping a least recently allocated cache block
JP3497832B2 (ja) * 2001-03-28 2004-02-16 株式会社半導体理工学研究センター ロード・ストアキュー
US6883086B2 (en) * 2002-03-06 2005-04-19 Intel Corporation Repair of mis-predicted load values
US7028166B2 (en) * 2002-04-30 2006-04-11 Advanced Micro Devices, Inc. System and method for linking speculative results of load operations to register values

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI652618B (zh) 2013-03-15 2019-03-01 英特爾股份有限公司 用以管理儲存在硬體結構中的元素的方法與設備
US10289419B2 (en) 2013-03-15 2019-05-14 Intel Corporation Method and apparatus for sorting elements in hardware structures

Also Published As

Publication number Publication date
US7263600B2 (en) 2007-08-28
GB2429557B (en) 2007-09-05
CN1954290A (zh) 2007-04-25
WO2005111794A1 (en) 2005-11-24
GB0622878D0 (en) 2006-12-27
DE112004002848B4 (de) 2010-06-17
GB2429557A (en) 2007-02-28
JP2007536626A (ja) 2007-12-13
TW200606709A (en) 2006-02-16
CN100424635C (zh) 2008-10-08
US20050247774A1 (en) 2005-11-10
DE112004002848T5 (de) 2007-04-05

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