JP2007536626A - ロードオペレーションの投機的な結果をレジスタ値にリンクするメモリファイルを検証するためのシステムおよび方法 - Google Patents

ロードオペレーションの投機的な結果をレジスタ値にリンクするメモリファイルを検証するためのシステムおよび方法 Download PDF

Info

Publication number
JP2007536626A
JP2007536626A JP2007511351A JP2007511351A JP2007536626A JP 2007536626 A JP2007536626 A JP 2007536626A JP 2007511351 A JP2007511351 A JP 2007511351A JP 2007511351 A JP2007511351 A JP 2007511351A JP 2007536626 A JP2007536626 A JP 2007536626A
Authority
JP
Japan
Prior art keywords
load
speculative
tag
register
store
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007511351A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007536626A5 (https=
Inventor
ティー. サンダー ベンジャミン
ブイ. ラミニ クリシュナン
ダブリュ. ハダッド ラムジー
アルサップ ミッチェル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2007536626A publication Critical patent/JP2007536626A/ja
Publication of JP2007536626A5 publication Critical patent/JP2007536626A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824Operand accessing
    • G06F9/3826Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824Operand accessing
    • G06F9/383Operand prefetching
    • G06F9/3832Value prediction for operands; operand history buffers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824Operand accessing
    • G06F9/3834Maintaining memory consistency
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384Register renaming
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824Operand accessing
    • G06F9/383Operand prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
JP2007511351A 2004-05-05 2004-12-17 ロードオペレーションの投機的な結果をレジスタ値にリンクするメモリファイルを検証するためのシステムおよび方法 Pending JP2007536626A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/839,474 US7263600B2 (en) 2004-05-05 2004-05-05 System and method for validating a memory file that links speculative results of load operations to register values
PCT/US2004/042683 WO2005111794A1 (en) 2004-05-05 2004-12-17 System and method for validating a memory file that links speculative results of load operations to register values

Publications (2)

Publication Number Publication Date
JP2007536626A true JP2007536626A (ja) 2007-12-13
JP2007536626A5 JP2007536626A5 (https=) 2008-02-14

Family

ID=34959784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007511351A Pending JP2007536626A (ja) 2004-05-05 2004-12-17 ロードオペレーションの投機的な結果をレジスタ値にリンクするメモリファイルを検証するためのシステムおよび方法

Country Status (7)

Country Link
US (1) US7263600B2 (https=)
JP (1) JP2007536626A (https=)
CN (1) CN100424635C (https=)
DE (1) DE112004002848B4 (https=)
GB (1) GB2429557B (https=)
TW (1) TWI362613B (https=)
WO (1) WO2005111794A1 (https=)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013515306A (ja) * 2009-12-22 2013-05-02 インターナショナル・ビジネス・マシーンズ・コーポレーション アウトオブオーダー型マイクロプロセッサにおけるオペランド・ストア・比較ハザードの予測及び回避
JP2014002735A (ja) * 2012-06-14 2014-01-09 Apple Inc ゼロサイクルロード
KR20190033084A (ko) * 2016-08-19 2019-03-28 어드밴스드 마이크로 디바이시즈, 인코포레이티드 로드 스토어 유닛들을 바이패싱하여 스토어 및 로드 추적
US11068271B2 (en) 2014-07-28 2021-07-20 Apple Inc. Zero cycle move using free list counts
US11200062B2 (en) 2019-08-26 2021-12-14 Apple Inc. History file for previous register mapping storage and last reference indication
US11416254B2 (en) 2019-12-05 2022-08-16 Apple Inc. Zero cycle load bypass in a decode group

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7571304B2 (en) * 2005-03-18 2009-08-04 Sun Microsystems, Inc. Generation of multiple checkpoints in a processor that supports speculative execution
US7376817B2 (en) * 2005-08-10 2008-05-20 P.A. Semi, Inc. Partial load/store forward prediction
US20080010440A1 (en) * 2006-07-05 2008-01-10 International Business Machines Corporation Means for supporting and tracking a large number of in-flight stores in an out-of-order processor
US20080010441A1 (en) * 2006-07-05 2008-01-10 International Business Machines Corporation Means for supporting and tracking a large number of in-flight loads in an out-of-order processor
US7624253B2 (en) * 2006-10-25 2009-11-24 Arm Limited Determining register availability for register renaming
US20080162889A1 (en) * 2007-01-03 2008-07-03 International Business Machines Corporation Method and apparatus for implementing efficient data dependence tracking for multiprocessor architectures
US7689812B2 (en) * 2007-02-14 2010-03-30 International Business Machines Corporation Method and system for restoring register mapper states for an out-of-order microprocessor
US9069672B2 (en) * 2009-06-12 2015-06-30 Intel Corporation Extended fast memory access in a multiprocessor computer system
US8468325B2 (en) 2009-12-22 2013-06-18 International Business Machines Corporation Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
US9135014B2 (en) * 2012-02-15 2015-09-15 Freescale Semiconductor, Inc Data processing system with latency tolerance execution
US9436476B2 (en) 2013-03-15 2016-09-06 Soft Machines Inc. Method and apparatus for sorting elements in hardware structures
US10467010B2 (en) * 2013-03-15 2019-11-05 Intel Corporation Method and apparatus for nearest potential store tagging
US10152327B2 (en) 2013-03-15 2018-12-11 Intel Corporation Apparatus for gating a load operation based on entries of a prediction table
US9471480B2 (en) 2013-12-02 2016-10-18 The Regents Of The University Of Michigan Data processing apparatus with memory rename table for mapping memory addresses to registers
GB2518022B (en) * 2014-01-17 2015-09-23 Imagination Tech Ltd Stack saved variable value prediction
GB2532232A (en) * 2014-11-12 2016-05-18 Ibm Verifying a graph-based coherency verification tool
US9575897B2 (en) 2015-07-09 2017-02-21 Centipede Semi Ltd. Processor with efficient processing of recurring load instructions from nearby memory addresses
US20170010973A1 (en) * 2015-07-09 2017-01-12 Centipede Semi Ltd. Processor with efficient processing of load-store instruction pairs
CN107710153B (zh) * 2015-07-09 2022-03-01 森蒂彼得塞米有限公司 具有有效的存储器访问的处理器
US10185561B2 (en) * 2015-07-09 2019-01-22 Centipede Semi Ltd. Processor with efficient memory access
US10908911B2 (en) 2017-08-18 2021-02-02 International Business Machines Corporation Predicting and storing a predicted target address in a plurality of selected locations
US10884747B2 (en) 2017-08-18 2021-01-05 International Business Machines Corporation Prediction of an affiliated register
US11150908B2 (en) 2017-08-18 2021-10-19 International Business Machines Corporation Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence
US10534609B2 (en) 2017-08-18 2020-01-14 International Business Machines Corporation Code-specific affiliated register prediction
US10719328B2 (en) 2017-08-18 2020-07-21 International Business Machines Corporation Determining and predicting derived values used in register-indirect branching
US10884745B2 (en) 2017-08-18 2021-01-05 International Business Machines Corporation Providing a predicted target address to multiple locations based on detecting an affiliated relationship
US10884746B2 (en) 2017-08-18 2021-01-05 International Business Machines Corporation Determining and predicting affiliated registers based on dynamic runtime control flow analysis
US11150904B2 (en) 2017-08-18 2021-10-19 International Business Machines Corporation Concurrent prediction of branch addresses and update of register contents
US10705973B2 (en) 2017-09-19 2020-07-07 International Business Machines Corporation Initializing a data structure for use in predicting table of contents pointer values
US10620955B2 (en) 2017-09-19 2020-04-14 International Business Machines Corporation Predicting a table of contents pointer value responsive to branching to a subroutine
US11061575B2 (en) 2017-09-19 2021-07-13 International Business Machines Corporation Read-only table of contents register
US10896030B2 (en) 2017-09-19 2021-01-19 International Business Machines Corporation Code generation relating to providing table of contents pointer values
US10725918B2 (en) 2017-09-19 2020-07-28 International Business Machines Corporation Table of contents cache entry having a pointer for a range of addresses
US10884929B2 (en) 2017-09-19 2021-01-05 International Business Machines Corporation Set table of contents (TOC) register instruction
US10713050B2 (en) 2017-09-19 2020-07-14 International Business Machines Corporation Replacing Table of Contents (TOC)-setting instructions in code with TOC predicting instructions
US10620961B2 (en) * 2018-03-30 2020-04-14 Intel Corporation Apparatus and method for speculative conditional move operation
US11334485B2 (en) * 2018-12-14 2022-05-17 Eta Scale Ab System and method for dynamic enforcement of store atomicity
US11061683B2 (en) * 2019-06-13 2021-07-13 Microsoft Technology Licensing, Llc Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor
US11392387B2 (en) 2020-11-04 2022-07-19 Microsoft Technology Licensing, Llc Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6065103A (en) * 1997-12-16 2000-05-16 Advanced Micro Devices, Inc. Speculative store buffer
JP2002287959A (ja) * 2001-03-28 2002-10-04 Handotai Rikougaku Kenkyu Center:Kk ロード・ストアキュー
WO2003093982A1 (en) * 2002-04-30 2003-11-13 Advanced Micro Devices, Inc. System and method for linking speculative results of load operations to register values

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778219A (en) * 1990-12-14 1998-07-07 Hewlett-Packard Company Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations
US5428807A (en) * 1993-06-17 1995-06-27 Digital Equipment Corporation Method and apparatus for propagating exception conditions of a computer system
US5584009A (en) * 1993-10-18 1996-12-10 Cyrix Corporation System and method of retiring store data from a write buffer
US5452426A (en) * 1994-01-04 1995-09-19 Intel Corporation Coordinating speculative and committed state register source data and immediate source data in a processor
US5799179A (en) * 1995-01-24 1998-08-25 International Business Machines Corporation Handling of exceptions in speculative instructions
US6237082B1 (en) * 1995-01-25 2001-05-22 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received
US5751983A (en) * 1995-10-03 1998-05-12 Abramson; Jeffrey M. Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations
US5892936A (en) * 1995-10-30 1999-04-06 Advanced Micro Devices, Inc. Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register
US6108769A (en) * 1996-05-17 2000-08-22 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US5781752A (en) * 1996-12-26 1998-07-14 Wisconsin Alumni Research Foundation Table based data speculation circuit for parallel processing computer
US6021485A (en) * 1997-04-10 2000-02-01 International Business Machines Corporation Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching
US5845103A (en) * 1997-06-13 1998-12-01 Wisconsin Alumni Research Foundation Computer with dynamic instruction reuse
US6044430A (en) * 1997-12-17 2000-03-28 Advanced Micro Devices Inc. Real time interrupt handling for superscalar processors
US6041405A (en) * 1997-12-18 2000-03-21 Advanced Micro Devices, Inc. Instruction length prediction using an instruction length pattern detector
US6112296A (en) * 1997-12-18 2000-08-29 Advanced Micro Devices, Inc. Floating point stack manipulation using a register map and speculative top of stack values
US6175910B1 (en) * 1997-12-19 2001-01-16 International Business Machines Corportion Speculative instructions exection in VLIW processors
JPH11212788A (ja) * 1998-01-28 1999-08-06 Toshiba Corp プロセッサのデータ供給装置
US6202204B1 (en) * 1998-03-11 2001-03-13 Intel Corporation Comprehensive redundant load elimination for architectures supporting control and data speculation
US6108770A (en) * 1998-06-24 2000-08-22 Digital Equipment Corporation Method and apparatus for predicting memory dependence using store sets
US6463580B1 (en) * 1998-11-18 2002-10-08 Intel Corporation Parallel processing utilizing highly correlated data values
US6349382B1 (en) * 1999-03-05 2002-02-19 International Business Machines Corporation System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order
US6658554B1 (en) * 1999-03-09 2003-12-02 Wisconsin Alumni Res Found Electronic processor providing direct data transfer between linked data consuming instructions
US6266744B1 (en) * 1999-05-18 2001-07-24 Advanced Micro Devices, Inc. Store to load forwarding using a dependency link file
US6393536B1 (en) * 1999-05-18 2002-05-21 Advanced Micro Devices, Inc. Load/store unit employing last-in-buffer indication for rapid load-hit-store
US6662280B1 (en) * 1999-11-10 2003-12-09 Advanced Micro Devices, Inc. Store buffer which forwards data based on index and optional way match
US6438673B1 (en) * 1999-12-30 2002-08-20 Intel Corporation Correlated address prediction
US6643767B1 (en) * 2000-01-27 2003-11-04 Kabushiki Kaisha Toshiba Instruction scheduling system of a processor
US6675287B1 (en) * 2000-04-07 2004-01-06 Ip-First, Llc Method and apparatus for store forwarding using a response buffer data path in a write-allocate-configurable microprocessor
DE10121792C2 (de) * 2000-05-26 2003-09-25 Ibm Universelle Ladeadresse/Wertevorhersageschema
US6671780B1 (en) * 2000-05-31 2003-12-30 Intel Corporation Modified least recently allocated cache replacement method and apparatus that allows skipping a least recently allocated cache block
US6883086B2 (en) * 2002-03-06 2005-04-19 Intel Corporation Repair of mis-predicted load values

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6065103A (en) * 1997-12-16 2000-05-16 Advanced Micro Devices, Inc. Speculative store buffer
JP2002287959A (ja) * 2001-03-28 2002-10-04 Handotai Rikougaku Kenkyu Center:Kk ロード・ストアキュー
WO2003093982A1 (en) * 2002-04-30 2003-11-13 Advanced Micro Devices, Inc. System and method for linking speculative results of load operations to register values
US20040177236A1 (en) * 2002-04-30 2004-09-09 Pickett James K. System and method for linking speculative results of load operations to register values
JP2005532613A (ja) * 2002-04-30 2005-10-27 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ロード操作の推測結果をレジスタ値にリンクするためのシステムおよび方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013515306A (ja) * 2009-12-22 2013-05-02 インターナショナル・ビジネス・マシーンズ・コーポレーション アウトオブオーダー型マイクロプロセッサにおけるオペランド・ストア・比較ハザードの予測及び回避
JP2015228237A (ja) * 2009-12-22 2015-12-17 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation アウトオブオーダー型マイクロプロセッサにおけるオペランド・ストア比較ハザードの予測及び回避
US9430235B2 (en) 2009-12-22 2016-08-30 International Business Machines Corporation Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
JP2014002735A (ja) * 2012-06-14 2014-01-09 Apple Inc ゼロサイクルロード
US9996348B2 (en) 2012-06-14 2018-06-12 Apple Inc. Zero cycle load
US11068271B2 (en) 2014-07-28 2021-07-20 Apple Inc. Zero cycle move using free list counts
KR20190033084A (ko) * 2016-08-19 2019-03-28 어드밴스드 마이크로 디바이시즈, 인코포레이티드 로드 스토어 유닛들을 바이패싱하여 스토어 및 로드 추적
JP2019525355A (ja) * 2016-08-19 2019-09-05 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated ロードストアユニットをバイパスすることによるストア及びロードの追跡
JP7084379B2 (ja) 2016-08-19 2022-06-14 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ロードストアユニットをバイパスすることによるストア及びロードの追跡
KR102524565B1 (ko) 2016-08-19 2023-04-21 어드밴스드 마이크로 디바이시즈, 인코포레이티드 로드 스토어 유닛들을 바이패싱하여 스토어 및 로드 추적
US11200062B2 (en) 2019-08-26 2021-12-14 Apple Inc. History file for previous register mapping storage and last reference indication
US11416254B2 (en) 2019-12-05 2022-08-16 Apple Inc. Zero cycle load bypass in a decode group

Also Published As

Publication number Publication date
TWI362613B (en) 2012-04-21
US7263600B2 (en) 2007-08-28
GB2429557B (en) 2007-09-05
CN1954290A (zh) 2007-04-25
WO2005111794A1 (en) 2005-11-24
GB0622878D0 (en) 2006-12-27
DE112004002848B4 (de) 2010-06-17
GB2429557A (en) 2007-02-28
TW200606709A (en) 2006-02-16
CN100424635C (zh) 2008-10-08
US20050247774A1 (en) 2005-11-10
DE112004002848T5 (de) 2007-04-05

Similar Documents

Publication Publication Date Title
CN100424635C (zh) 验证将加载作业的推测结果连结到缓存器值的存储档案的系统及方法
JP4538462B2 (ja) 二重用途レジスタを識別しているアドレス指定パターンに基づいたデータ投機
US7415597B2 (en) Processor with dependence mechanism to predict whether a load is dependent on older store
JP4105684B2 (ja) ロード操作の推測結果をレジスタ値にリンクするためのシステムおよび方法
US6950925B1 (en) Scheduler for use in a microprocessor that supports data-speculative execution
JP3866261B2 (ja) ロード/ストア操作をバイパスするために投機的ソースオペランドを使用するシステムおよび方法
WO2005041024A2 (en) System and method for handling exceptional instructions in a trace cache based processor
KR101093784B1 (ko) 리플레이 메커니즘을 구비한 로드 저장 유닛
JP4624988B2 (ja) データ推測マイクロプロセッサにおいて実行中のオペレーションのインスタンスがオペレーションのリプレイの割込みを防ぐためのシステム及び方法
US7222226B1 (en) System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation
US7043626B1 (en) Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming
US7937569B1 (en) System and method for scheduling operations using speculative data operands
JP4745960B2 (ja) マイクロプロセッサにおいてデータ推測オペレーションを識別する推測ポインタ
US7197630B1 (en) Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation
KR20070019750A (ko) 로드 동작의 투기적인 결과들을 레지스터 값들에 연결하는메모리 파일을 유효화하기 위한 시스템 및 그 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071214

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071214

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20100421

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20100902

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101215

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20110629