GB2429557B - System and method for validating a memory file that links speculative results of load operations to register values - Google Patents

System and method for validating a memory file that links speculative results of load operations to register values

Info

Publication number
GB2429557B
GB2429557B GB0622878A GB0622878A GB2429557B GB 2429557 B GB2429557 B GB 2429557B GB 0622878 A GB0622878 A GB 0622878A GB 0622878 A GB0622878 A GB 0622878A GB 2429557 B GB2429557 B GB 2429557B
Authority
GB
United Kingdom
Prior art keywords
validating
links
register values
memory file
load operations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0622878A
Other languages
English (en)
Other versions
GB0622878D0 (en
GB2429557A (en
Inventor
Benjamin T Sander
Krishnan V Ramani
Ramsey W Haddad
Mitchell Alsup
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0622878D0 publication Critical patent/GB0622878D0/en
Publication of GB2429557A publication Critical patent/GB2429557A/en
Application granted granted Critical
Publication of GB2429557B publication Critical patent/GB2429557B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
GB0622878A 2004-05-05 2004-12-17 System and method for validating a memory file that links speculative results of load operations to register values Expired - Fee Related GB2429557B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/839,474 US7263600B2 (en) 2004-05-05 2004-05-05 System and method for validating a memory file that links speculative results of load operations to register values
PCT/US2004/042683 WO2005111794A1 (en) 2004-05-05 2004-12-17 System and method for validating a memory file that links speculative results of load operations to register values

Publications (3)

Publication Number Publication Date
GB0622878D0 GB0622878D0 (en) 2006-12-27
GB2429557A GB2429557A (en) 2007-02-28
GB2429557B true GB2429557B (en) 2007-09-05

Family

ID=34959784

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0622878A Expired - Fee Related GB2429557B (en) 2004-05-05 2004-12-17 System and method for validating a memory file that links speculative results of load operations to register values

Country Status (7)

Country Link
US (1) US7263600B2 (https=)
JP (1) JP2007536626A (https=)
CN (1) CN100424635C (https=)
DE (1) DE112004002848B4 (https=)
GB (1) GB2429557B (https=)
TW (1) TWI362613B (https=)
WO (1) WO2005111794A1 (https=)

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US8468325B2 (en) 2009-12-22 2013-06-18 International Business Machines Corporation Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
US9135014B2 (en) * 2012-02-15 2015-09-15 Freescale Semiconductor, Inc Data processing system with latency tolerance execution
US9996348B2 (en) * 2012-06-14 2018-06-12 Apple Inc. Zero cycle load
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US10467010B2 (en) * 2013-03-15 2019-11-05 Intel Corporation Method and apparatus for nearest potential store tagging
US10152327B2 (en) 2013-03-15 2018-12-11 Intel Corporation Apparatus for gating a load operation based on entries of a prediction table
US9471480B2 (en) 2013-12-02 2016-10-18 The Regents Of The University Of Michigan Data processing apparatus with memory rename table for mapping memory addresses to registers
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US20170010973A1 (en) * 2015-07-09 2017-01-12 Centipede Semi Ltd. Processor with efficient processing of load-store instruction pairs
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US10908911B2 (en) 2017-08-18 2021-02-02 International Business Machines Corporation Predicting and storing a predicted target address in a plurality of selected locations
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US10705973B2 (en) 2017-09-19 2020-07-07 International Business Machines Corporation Initializing a data structure for use in predicting table of contents pointer values
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US11061575B2 (en) 2017-09-19 2021-07-13 International Business Machines Corporation Read-only table of contents register
US10896030B2 (en) 2017-09-19 2021-01-19 International Business Machines Corporation Code generation relating to providing table of contents pointer values
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US10884929B2 (en) 2017-09-19 2021-01-05 International Business Machines Corporation Set table of contents (TOC) register instruction
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Also Published As

Publication number Publication date
TWI362613B (en) 2012-04-21
US7263600B2 (en) 2007-08-28
CN1954290A (zh) 2007-04-25
WO2005111794A1 (en) 2005-11-24
GB0622878D0 (en) 2006-12-27
DE112004002848B4 (de) 2010-06-17
GB2429557A (en) 2007-02-28
JP2007536626A (ja) 2007-12-13
TW200606709A (en) 2006-02-16
CN100424635C (zh) 2008-10-08
US20050247774A1 (en) 2005-11-10
DE112004002848T5 (de) 2007-04-05

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PCNP Patent ceased through non-payment of renewal fee

Effective date: 20111217