1362096 • a 九、發明說明： « •【發明所屬之技術領域】 : 本發明係有關於一種半導體裴置之製法，尤指一種呈 細間距電性連接結構之封裝基板製法。 八 【先前技術】 隨著電子產業的蓮勃發展，電子產品之外型趨向輕薄 方：ί功能上並逐漸邁入高性能、高功能、高速度化的 •先進ΐί、=覆晶式⑺iP邮）半導體封裝技術為一種 令化技術，在現行覆以半導體封裝技術 :接片上設有電極塾，並於該電極㈣^ 有相對應之電性接觸塾 .遠=凸塊，俾提供該半導體晶片透過該些烊接凸 連接該封裝基板。 Α由於越來越多的產品設計趨向於小型化、高速度、多 功能，因此，覆晶技術的應用範圍將不斷擴大，成爲 標準的晶片封裝技術’相較於打線接合（Wire Bond)技 t’覆晶技術之特徵在於半導體晶片與封裝基板間的電性 件=塊而非一般之金線，而該種覆晶技術之 i點在於其可“封裝密度以降低封裝元件尺寸，同時， 該種覆晶技術不需使用長度較長之金線，故可提高電 能。 請參閱第1A至ID圖，係為習知於基板之電性接觸墊 上電鑛形成導電凸柱及焊接材料之製法；如第1A圖所 不’係於一表面形成有複數電性接觸塾1〇1之基板本體 Π0782 5 1362096 10上形成有防焊層u， 程形成有複數對應之開孔1=層乂”以曝光顯影製 ⑻，而該開孔 ^ At , „0 电炫接觸墊101上，因顯 (7= 而有顯影之殘渔產生，稱之為膠浩 命Γ易旦/二該料110a於細小孔徑時愈容易產生，且 =接觸塾101、防烊们1表面及其開孔i二 厚… 设於亥W層12上形成有阻層13,且該阻 中形成有開口 130’以露出形成於該電性接觸塾101 之導電4 12’如第ic圖所示，接著藉由該導電層κ =電鍍製程以於該電性接觸塾m上形成金屬凸柱Η 、接^料15，凊麥閱第1D圖，之後移除該阻層及 -斤覆愿之導電層12 ’以露出該金屬凸柱i 4及焊接材料1362096 • a IX. Description of the invention: «• Technical field to which the invention pertains: The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method for fabricating a package substrate having a fine pitch electrical connection structure. Eight [previous technology] With the development of the electronics industry, the appearance of electronic products tends to be thin and light: ί functions and gradually enters high performance, high functionality, high speed. • Advanced 、ί, = flip-chip (7) iP Semiconductor packaging technology is a kind of technology. In the current semiconductor packaging technology: the electrode is provided on the tab, and the electrode (4) has a corresponding electrical contact. The far=bump is provided. The package substrate is connected through the splicing bumps. Α As more and more product designs tend to be smaller, faster, and more versatile, the application of flip chip technology will continue to expand, becoming the standard chip packaging technology' compared to wire bonding technology. 'The flip chip technology is characterized by the electrical component between the semiconductor wafer and the package substrate = block instead of the general gold wire, and the point of the flip chip technology is that it can "package density to reduce the package component size, and at the same time, The flip chip technology does not need to use a long length of gold wire, so it can improve the electric energy. Please refer to the 1A to ID diagram, which is a method for forming a conductive stud and a solder material by using the electric contact on the electrical contact pad of the substrate; As shown in FIG. 1A, a substrate body Π0782 5 1362096 10 having a plurality of electrical contacts 塾1〇1 formed on a surface thereof is formed with a solder resist layer u, and a plurality of corresponding openings 1=layers are formed. Exposure development system (8), and the opening ^ At, „0 electro-shock contact pad 101, due to display (7 = there is development of the residual fishing, called glue Haoming Yidan / two of the material 110a in small The easier the aperture is, and the contact 塾101, prevention The surface of the first surface 1 and the opening thereof are two thick. The resist layer 13 is formed on the layer 12 of the sea, and an opening 130' is formed in the resist to expose the conductive layer 12 12' formed in the electrical contact layer 101. As shown in the ic diagram, the conductive layer κ = electroplating process is followed to form a metal stud 、 and a material 15 on the electrical contact 塾m, and the buckwheat is read in the 1D image, and then the resist layer is removed and - Receptive conductive layer 12' to expose the metal stud i 4 and welding material
It)。 .上述製法t，受限於對位精度，該阻層13之開口 130 籲=大於該防焊層η之開孔11〇，使該金屬凸柱14於該開 I 130及開孔110之間形成頸縮之肩部141(如第1C圖所 2)’當該電性接觸墊101與金屬凸柱14持續縮小，且該 'θ接材料15僅結合於該金屬凸柱14上，使該金屬凸柱 4之肩部141容易因後續熱循環製程中因熱應力導致應 =中，致使該金屬凸柱14於肩部2 41處產生龜裂，因 而知％電性連接，且該金屬凸柱14之肩部141亦佔用了 部分空間。 再者，因以曝光顯影之圖案化製程於該防焊層丨丨中 110782 6 形成有開孔110，該開不丨】】n产A ,It). The method t is limited by the alignment accuracy, and the opening 130 of the resist layer 13 is greater than the opening 11 of the solder resist layer η, so that the metal stud 14 is between the opening I 130 and the opening 110. Forming a necked shoulder 141 (as in FIG. 1C) 2 when the electrical contact pad 101 and the metal stud 14 continue to shrink, and the 'θ connection material 15 is only bonded to the metal stud 14 The shoulder portion 141 of the metal stud 4 is likely to be cracked due to thermal stress in the subsequent thermal cycle process, causing the metal stud 14 to crack at the shoulder portion 21, thus knowing that the electrical connection is made and the metal bump is formed. The shoulder 141 of the post 14 also occupies a portion of the space. Furthermore, since the opening 110 is formed in the solder resist layer by the patterning process of exposure and development, the opening 110 is formed.
10底°卩外露之電性接觸墊1 o J 有膠潰110a’使該開孔11〇底部開口過小，導致 1 g Η與該電性接觸塾⑻之接觸面積縮小 至可能造成該金屬凸柱14盥杂 爸 連接不良，或該金屬凸柱二，觸整101之間的電性 2. ώ ^ 柱U與电性接觸墊101表面接著 強度降低，進而影響電性連接丧者 1Π1 βθ 0 牧<口口貝，且當該電性接觸墊 1 〇 1之間的間距持續縮減時， 蝕1Λ1 忑金屬凸柱14與電性接觸 墊101之間的結合面積更小 *, , Λ ^ 便該金屬凸柱14與電性接 之間的結合性降低，容易因後續熱循環製程中因 雛應為致該電性接觸墊1〇1與金屬凸柱“ 離，進而影響電性連接功能。 座生脫 因此，鑒於上述之問韻， 覆晶封裝基板上之全屬避免習知技術於細間距 差，導致電性連接不良的情況，每 ° ° ^ 題。 只已成目月'J亟欲解決的課 丨【發明内容】 繁於上述習知技術之缺 一種刼壯茸杧制+ 失本务明之主要目的係提供 題。衣能減少電性接觸墊結合性不佳之問 本發明之主要目的係提供—種封裝基板製 細間距之電性接觸墊。 b扠供 為達上述目的及J:他日4 製法，係包括.提#其本發明揭露一種封裝基板 數電性接= 本體，於其至少一表面具有複10 bottom 卩 exposed electrical contact pad 1 o J has a glue 110a' so that the bottom opening of the opening 11 过 is too small, resulting in a contact area of 1 g Η and the electrical contact 塾 (8) is reduced to possibly cause the metal stud 14 爸 爸 dad poorly connected, or the metal studs two, the electrical properties between the tangent 101. ώ ^ The strength of the surface of the column U and the electrical contact pad 101 is reduced, which affects the electrical connection of the mourners 1Π1 βθ 0 <mouth, and when the spacing between the electrical contact pads 1 〇1 is continuously reduced, the bonding area between the etched metal ribs 14 and the electrical contact pads 101 is smaller*, Λ ^ The bond between the metal studs 14 and the electrical connection is reduced, and the electrical contact pads 1〇1 and the metal studs are easily separated due to the subsequent thermal cycling process, thereby affecting the electrical connection function. Therefore, in view of the above-mentioned rhyme, the flip-chip package substrate is all about avoiding the conventional technique in the fine pitch difference, resulting in poor electrical connection, per ° ° ^. Only the moon has been 'J亟The lesson to be solved [invention] The lack of a kind of traditional technology The main purpose of the invention is to provide a problem. The main purpose of the present invention is to provide an electrical contact pad with a fine pitch of the package substrate. And J: the method of the fourth day, including the invention. The invention discloses a package substrate electrical connection = body, having at least one surface thereof
电性接觸H該電性接料上形成有凸I 110782 7 1362096 ♦ . •“生接觸墊上印刷形成有防焊層，該防焊層係低於 該，柱高於該防焊層，且該防焊層係未覆蓋該 、 ^曝絲f彡製餘物焊層巾形成有複數開孔，以 出該電性接觸塾之表面及凸柱，該開孔尺寸係大於 ❹柱尺七於該防焊層、開孔之孔壁、電性接觸塾及凸 主上二有第二導電層;於該第二導電層上形成有第三阻 三阻層中形成有複數第三開口區，以對應露出 該開孔中之第二導電a， _ Λ Hr - 且該苐二開口區大於該開孔；於 •該開孔及弟三開口區中電鑛形成有焊接材料，以完全包覆 該凸柱’並電性連接該凸柱及電性接觸塾；以及移除該第 .=層及其所覆蓋之第二導電層’以露出該防焊層及焊接 材料0 依上述之封裝基板製法，該基板本體上形成電性接觸 及凸柱之製法，係包括：於該基板本體上形成有第一導 電層；於該第一導電層上形成有第一阻層，且該第一阻声 #中形成有第一開口區’以露出部份之第一導電層；於該^ 一開口 £中之弟-導電層上電鑛形成該電性接觸塾；於該 卜阻層及電性接觸塾上形成有第二阻層，且該第二阻層 Μ成有第二開口區’以露出部份之電性接觸塾，·於該第 二開口區中之電性接觸塾上電鑛形成該凸柱；以及移除該 第二阻層、第一阻層及該第一阻層所覆蓋之第一導電層。 又依上述之製法，凸柱係為銅（Cu)、錄（Ni)、金Electrical contact H is formed on the electrical material with a convexity I 110782 7 1362096 ♦. "The raw contact pad is printed with a solder resist layer, the solder resist layer is lower than the pillar, and the pillar is higher than the solder resist layer, and the The solder resist layer is not covered, and the plurality of openings are formed to expose the surface of the electrical contact crucible and the protrusion, the size of the opening is larger than the ruler The solder resist layer, the opening hole wall, the electrical contact 塾 and the convex main layer have a second conductive layer; the third conductive layer is formed with a third resistive layer formed with a plurality of third open regions, Correspondingly exposing the second conductive a, _ Λ Hr - in the opening, and the second opening area is larger than the opening; in the opening and the third opening area, the electric ore is formed with a welding material to completely cover the protruding column 'and electrically connecting the stud and the electrical contact 塾; and removing the first layer and the second conductive layer covered by the second layer to expose the solder resist layer and the solder material 0. According to the above package substrate manufacturing method, Forming an electrical contact and a bump on the substrate body, comprising: forming a first conductive layer on the substrate body Forming a first resist layer on the first conductive layer, and forming a first open region 'in the first sound blocking layer to expose a portion of the first conductive layer; The layer is electrically formed to form the electrical contact enthalpy; a second resist layer is formed on the resist layer and the electrical contact ,, and the second resistive layer is formed with the second open region ′ to expose the electrical portion Contacting the crucible, forming the stud with the electrical contact in the second open region; and removing the second resist layer, the first resist layer and the first conductive layer covered by the first resist layer According to the above method, the pillars are copper (Cu), recorded (Ni), gold.
Uu)、錫（Sn)、錯⑽、銀（Ag)所組成群組之其中一者； 該焊接材料係為錫㈤、錯⑽、銀㈤、銅㈣、辞㈤ 110782 8 1362096 及叙（Bi)所組成群組之其中一者。 依上所述’該開孔係對應露出各該凸柱及 ， 所覆蓋之電性接觸塾的部分或全部表面。 本發明復提供-種封裝基板製法，係包括：提供—其 板本體’於其至少一表面具有複數電性接 : 塾上形成有凸柱，·於該基板本體及電性接觸二 形成有防焊層’該防焊層係低於該&柱，使該凸柱高= 防焊層，且該防蟬層係未覆罢 、^ 矿復皿a凸柱，以曝光顯影製程於 二、J形成有複數開孔’以對應露出該電性接觸塾之 表=及凸柱’該開孔尺寸係大於該凸柱尺寸；以及於該開 孔中之電性接觸墊之表面及凸柱上形成金屬，黏著層。 依上述之封裝基板製法，該基板本體上形成電性接觸 墊及凸柱之製法，係包括：於該基板本體上形成有第一導 電層；於該第一導電層上形成有第一阻層，且該第一阻層 中形成有第一開口區，以露出部份之第一導電層；於該^ :開口區中之第-導電層上電鐘形成該電性接觸塾；於該 第:阻層及電性接觸墊上形成有第二阻層，且該第二阻層 中形成有第二開口區，以露出部份之電性接觸墊,·於該第 =開口區中之電性接觸墊上電鍍形成該凸柱；以及移除該 第一阻層、第一阻層及該第一阻層所覆蓋之第一導電層。 依上述之製法，該凸柱24係為銅（Cu) '鎳（Ni)、金 (Au)錫（Sn)、錯（Pb)、銀（Ag)所組成群組之其中一者； 該金屬黏著層係為金、鎳、鈀、銀、錫、鎳/鈀、鉻/鈦、 鎳/金、鈀/金及鎳/鈀/金所組成群組之其中一者。 110782 9 1362096 费依上所述，該開孔係對應露出各該凸柱及未為該凸柱 所覆盘之電性接觸墊的部分或全部表面。 病+因此，本發明之封裝基板製法，係於該基板本體上連 a包鍍電性接觸墊及凸柱’使該凸柱底部完全接置於該電 I·,接觸墊上，以提高結合之穩固性，並於該電性接觸墊上 :成細間距之Μ’以提高佈設密度，且使覆蓋該基板本 版之防焊層之開孔尺寸大於該凸柱尺寸，以露出該電性接 觸墊之上表面及其上之凸柱，使該焊接材料完全包覆該凸 才俾以長1尚結合之穩固性，進而避免產生電性連接不良 的情況。 义 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。One of the groups consisting of Uu), tin (Sn), wrong (10), and silver (Ag); the solder material is tin (five), wrong (10), silver (five), copper (four), and (f) 110782 8 1362096 and One of the groups formed. According to the above, the opening corresponds to exposing part or all of the surface of each of the studs and the covered electrical contact. The invention provides a method for manufacturing a package substrate, comprising: providing a plate body having a plurality of electrical connections on at least one surface thereof: a protrusion is formed on the substrate, and the substrate body and the electrical contact are formed The soldering layer 'the solder resist layer is lower than the & column, so that the stud is high = solder resist layer, and the anti-corrosion layer is uncovered, and the anti-corrosion layer a pillar is exposed to the development process. J is formed with a plurality of openings 'to correspondingly expose the surface of the electrical contact = = and the column 'the opening size is greater than the size of the column; and the surface of the electrical contact pad and the column on the opening Form metal, adhesive layer. According to the above method for manufacturing a package substrate, the method for forming an electrical contact pad and a bump on the substrate body comprises: forming a first conductive layer on the substrate body; forming a first resist layer on the first conductive layer And forming a first opening region in the first resist layer to expose a portion of the first conductive layer; forming an electrical contact 电 on the first conductive layer in the opening region; a second resist layer is formed on the resist layer and the electrical contact pad, and a second open region is formed in the second resist layer to expose a portion of the electrical contact pad, and the electrical property in the first open region Forming the stud on the contact pad; and removing the first resist layer, the first resist layer and the first conductive layer covered by the first resist layer. According to the above method, the stud 24 is one of a group consisting of copper (Cu) 'nickel (Ni), gold (Au) tin (Sn), erbium (Pb), and silver (Ag); The adhesive layer is one of a group consisting of gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold, and nickel/palladium/gold. 110782 9 1362096 In accordance with the above description, the opening corresponds to a portion or all of the surface of each of the studs and the electrical contact pads that are not covered by the studs. Disease + Therefore, the method for manufacturing a package substrate of the present invention is to connect a package of electroplating contact pads and studs on the substrate body to completely connect the bottom of the stud to the electric I, contact pads to improve bonding. Stabilization, and on the electrical contact pad: a fine pitch Μ' to increase the layout density, and the size of the opening of the solder resist layer covering the front plate of the substrate is larger than the size of the stud to expose the electrical contact pad The upper surface and the protrusions thereon enable the solder material to completely cover the protrusion, and the stability of the combination is long, thereby avoiding the occurrence of electrical connection failure. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure.
請參閱第2Α至2Κ圖，係詳細說明本發明封裴基板製 法之剖面示意圖。 τ 如第2Α圖所示，提供一基板本體2〇,於該基板本體 20上形成有第一導電層21a，該第一導電層2ia主要係作 爲後續電鍍金屬材料所需之電流傳導路徑，其可由金屬 合金或沉積數層金屬層所構成，如選自銅、錫、鎳、鉻、 鈦、銅-路合金或錫-錯合金等所構成之群組之其中一者所 組成，係以濺鍍、蒸鍍、無電電鍍及化學沈積之一者刑成. 或可使用例如聚乙炔、聚笨胺或有機硫聚合物等導電言八 子材料’而以旋轉塗佈（Spin coating)、喷黑印刷 110782 10 1362096 (ink-jet printlng)或㈣（—Μ •該第一導電層21a。 仏成 :阻二第2β圖所示，於該第一導電層21a上形成有第-θ a該第―阻層22a係為—例如乾膜或液態光阻等 ,2阻層（Ph〇t〇resi st)，其係利用印刷、旋塗或貼合等方 ::別形成於該第一導電層21a上，再藉由曝光、 方式於該第一阻居ώ 、寺 2?〇抱^曰22a中圖案化以形成第一開口 22〇a，俾以露出部份之第一導電層21日。 匕 如第2C圖所示，於該第一開口區22〇a中之第一導電 θ 21a上電鍍形成有電性接觸墊23。 上形：ί Γ二圖广示’於該第一阻層22a及電性接觸塾23 開口^ 22Gb— Μ咖，且該第二阻層挪中形成有第二 =H2Gb，以露出部份之電性接 區鳩尺寸係小於第一開口區220a尺寸。 開口 如第2E圖所示，於該第二開口區鳩中之 ，⑻2)3上金電(ΓΓ成有凸柱24 ;該凸柱24係為銅(Cu)、鋅 如第2F圖所示，移除該第二阻層挪、第一阻 及該第-阻層22a所覆蓋之第一導電層Η 曰' 板本體^ 乂路出該基 反本體20 t性接觸塾㈡及其上之凸柱& 性接觸墊23及凸# 94 > & + ± 接者，該電 合性。 凸柱24之外露表面進行粗化，藉以增加結 如第2G圖所示，於該基板本體2〇及電性接觸塾23 】】0782 11 1362096 上之凸柱24設有印刷網版30，以於該基板本體2〇及電 •性接觸墊23上以印刷形成有防焊層25，該防焊層25係 -低於該凸柱24,且該防焊層25係未覆蓋該凸柱24，使^ '凸柱24高於該防焊層25提供適當高度，以利於後續與^ 片接合及封裝製程之進行。 如弟2H 2H-1、2H-2及2H-3圖所示，於該防焊層 25中曝光顯影形成有複數開孔25〇，以對應露出該凸柱 24及未為該凸柱24所覆蓋之電性接觸墊23的部份表 •面，如第2H圖所示；或於該電性接觸塾23的部份表面及 凸柱24上形成有金屬黏著層26a，如第2H-i圖所示；或 ，開孔250亦可對應露出該凸柱24及未為該凸柱24所覆 蓋之電性接觸墊23的全部表面’如第2H_2圖所示；或於 該包！'生接觸塾23的全部表面及凸柱24上形成有金屬黏著 層26a ’如第2H-3圖所示；其中該金屬黏著層26a係為 金、錄、免、銀、錫、錄/把、鉻/欽、錄/金、|ε/金及錦 # /纪/金所組成群組之其中一者；之後，以該第2H圖所示 之結構作說明。 如第21圖所示，於該防焊層25、開孔250之孔壁、 電陡接觸塾23及凸柱24上形成有第二導電層21b;接著 於該第二導電層21b上形成有第三阻層Me，且該第三阻 層版中形成有複數第三開口區220c，以對應露出各該 開孔250中之第二導電層21b ’且該第三開口區220c大 於該開孔250。 如第21圖所示’於該防焊層25之開孔250及第三開 12 110782 1362096 口區220c中電鍍形成有焊接材料26b，以完全包覆該凸 枉24,亚電性連接該凸柱24及電性接觸墊23;該焊接材 科 26b 係為錫（Sn)、鉛（Pb)、銀（Ag)、銅（Cu)、鋅 及鉍（B i )所組成群組之其中一者。 , 如第2K圖所示，移除該第三阻層22c及其所覆蓋之 第二導電層21b，以露出該防焊層25及焊接材料2此；該 凸=24係高於該防焊層25,可減少該焊接材料2讣的使 用里，並使該凸柱24深入該焊接材料26b中，而可提高 ♦該焊接材料26b與凸柱24之結合性，以及提供適當的高 度，以利於後續與晶片接合及封裝製程之進行。 本發明之封裝基板製法，係於該基板本體上連續電鍍 •形成該電性接觸墊及凸柱’使該凸柱底部完全接置於該電 性接觸墊上，俾以提高結合之穩固性，並於該電性接觸塾 上也成細間距之凸柱，以提高佈設密度，且使覆蓋於該基 板本體之防蟬層之開孔尺寸大於該凸柱尺寸，以露出該凸 籲柱及未為該凸柱所覆蓋之電性接觸墊的部分或全部表 面由於》亥凸柱業已連續電鐘成形於該電性接觸塾上，即 使防焊層顯影產生膠渣，亦不致影響電性接觸塾及凸柱的 心丨並於後續製私使該焊接材料完全包覆該凸柱，俾 以提高結合之穩固性’進而避免產生電性連接不良的情 =，且該凸柱高於該防焊層，能提供適當高度，以利於後 、·’灵與晶片接合及封裝製程之進行。 >上迷貫施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 110782 13 月：發明之精神及範疇下，對上述實施例進行修 x *此發明之彳_保護範®，應如後狀ΐ請專利範 • 圍所列。 【圖式簡單説明】 第1Α至1D圖係為習知半導體封裝基板增層製法之流 程不意圖， 第2Α至2Κ圖係為本發明之封裝基板製法之剖面示意 圖； 第2Η-1圖係接續第2Η圖之實施例； 第2Η-2圖係為第2Η圖之另一實施例；以及 第2Η-3圖係接續第2Η-2圖之實施例。 【主要元件符號說明】 10、20 基板本體 101 、 23 電性接觸墊 11、25 防焊層 110 、 250 開孔 110a 膠渣 12 導電層 13 阻層 130 開口 14 金屬凸柱 141 肩部 15 、 26b 焊接材料 21a 第一導電層 14 110782 1362096 21b 22a 220a 22b 220b 22c 220c 24 • 26a 30 第二導電層 第一阻層 第一開口區 第二阻層 第二開口區 第三阻層 第三開口區 凸柱 金屬黏著層 印刷網版Referring to Figures 2 to 2, a cross-sectional view showing the method of sealing the substrate of the present invention will be described in detail. As shown in FIG. 2, a substrate body 2 is provided, and a first conductive layer 21a is formed on the substrate body 20, and the first conductive layer 2ia is mainly used as a current conduction path required for subsequent plating of a metal material. It may be composed of a metal alloy or a plurality of deposited metal layers, such as one selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-alloy or tin-alloy, with a splash One of plating, vapor deposition, electroless plating, and chemical deposition may be used. Alternatively, spin coating or black printing may be used using a conductive material such as polyacetylene, polystyrene or organic sulfur polymer. 110782 10 1362096 (ink-jet printlng) or (d) (-) the first conductive layer 21a. The second conductive layer 21a is formed with a first -θ a - The resist layer 22a is, for example, a dry film or a liquid photoresist, or a resist layer, which is formed by printing, spin coating or lamination, etc.: is formed on the first conductive layer 21a. Then, by the exposure, the pattern is patterned in the first barrier 、, the temple 2 〇 曰 曰 22a to form the first Opening 22〇a, 俾 to expose a portion of the first conductive layer 21. As shown in FIG. 2C, an electrical contact pad is formed on the first conductive θ 21a in the first open region 22〇a. 23. The upper shape: ί Γ 2 shows that the first resist layer 22a and the electrical contact 塾 23 opening ^ 22Gb - Μ , , 且 , , , , , , , , , , The size of the electrical contact region is smaller than the size of the first opening region 220a. The opening is as shown in FIG. 2E, and in the second opening region, (8) 2) 3 is gold-plated (clamped into a stud 24; The stud 24 is made of copper (Cu) and zinc, as shown in FIG. 2F, and the second resist layer, the first resist, and the first conductive layer covered by the first resist layer 22a are removed. The enthalpy out of the base counter body 20 t contact 塾 (2) and the above-mentioned studs & contact pads 23 and convex # 94 > & ± + contacts, the electrical compatibility. Roughening, in order to increase the junction, as shown in FIG. 2G, the substrate 24 and the electrical contact 23 are provided with a printing screen 30 for the substrate body 2 Electrical connection A solder resist layer 25 is formed on the pad 23 by printing, and the solder resist layer 25 is lower than the stud 24, and the solder resist layer 25 does not cover the stud 24 so that the bump 24 is higher than the anti-solder The solder layer 25 is provided with a suitable height to facilitate the subsequent bonding and packaging process. As shown in the drawings 2H 2H-1, 2H-2 and 2H-3, the solder resist layer 25 is exposed and developed to form a plurality of layers. Opening a hole 25 〇 to correspond to a portion of the surface of the stud 24 and the electrical contact pad 23 not covered by the stud 24, as shown in FIG. 2H; or the electrical contact 塾23 A metal adhesion layer 26a is formed on a portion of the surface and the post 24, as shown in FIG. 2H-i; or the opening 250 may correspondingly expose the protrusion 24 and the electrical contact not covered by the protrusion 24. The entire surface of the pad 23 is as shown in the 2H_2 diagram; or in the package! A metal adhesive layer 26a' is formed on the entire surface of the green contact bump 23 and on the stud 24 as shown in FIG. 2H-3; wherein the metal adhesive layer 26a is gold, recorded, free, silver, tin, recorded/handed One of the groups consisting of chrome/champ, record/gold, |ε/金和锦# / 纪/金; after that, the structure shown in Fig. 2H is used for explanation. As shown in FIG. 21, a second conductive layer 21b is formed on the solder resist layer 25, the hole wall of the opening 250, the electrical steep contact 塾 23 and the stud 24; and then formed on the second conductive layer 21b. a third resistive layer Me, and a plurality of third open regions 220c are formed in the third resistive layer to correspondingly expose the second conductive layer 21b' in each of the openings 250 and the third open region 220c is larger than the opening 250. As shown in FIG. 21, a solder material 26b is plated in the opening 250 of the solder resist layer 25 and the third opening 12 110782 1362096 port region 220c to completely cover the tenon 24, electrically connecting the bump a pillar 24 and an electrical contact pad 23; the solder material 26b is one of a group consisting of tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc and bismuth (B i ) By. As shown in FIG. 2K, the third resist layer 22c and the second conductive layer 21b covered thereon are removed to expose the solder resist layer 25 and the solder material 2; the convex=24 system is higher than the solder resist The layer 25 can reduce the use of the solder material 2 , and make the stud 24 penetrate into the solder material 26b, thereby improving the bonding of the solder material 26b and the stud 24, and providing an appropriate height to Conducive to subsequent wafer bonding and packaging process. The method for manufacturing a package substrate according to the present invention is to continuously electroplat the main body of the substrate, form the electrical contact pad and the pillars to completely connect the bottom of the pillar to the electrical contact pad, so as to improve the stability of the bond, and a fine pitch pillar is also formed on the electrical contact raft to increase the layout density, and the opening of the tamper-proof layer covering the substrate body is larger than the pillar size to expose the convex column and the Part or all of the surface of the electrical contact pad covered by the stud is formed on the electrical contact pad by the continuous electric bell. Even if the solder resist develops to produce glue, it does not affect the electrical contact. The core of the stud and the subsequent manufacturing of the solder material completely cover the stud, so as to improve the stability of the bond', thereby avoiding the occurrence of electrical connection failure, and the stud is higher than the solder resist layer , can provide the appropriate height, in order to facilitate the post, 'spirit and wafer bonding and packaging process. The above examples are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Anyone who is familiar with this skill can apply for the above embodiment under the spirit and scope of the invention. 110 * The invention _ Protection Fan® should be listed as follows. BRIEF DESCRIPTION OF THE DRAWINGS The first to the first drawings are not intended to be the flow of the conventional semiconductor package substrate build-up method, and the second to second drawings are schematic cross-sectional views of the package substrate manufacturing method of the present invention; The embodiment of Fig. 2; Fig. 2-2 is another embodiment of Fig. 2; and Fig. 2-3 is an embodiment of Fig. 2-2. [Main component symbol description] 10, 20 substrate body 101, 23 electrical contact pads 11, 25 solder resist layer 110, 250 opening 110a slag 12 conductive layer 13 resist layer 130 opening 14 metal stud 141 shoulder 15 , 26b Soldering material 21a first conductive layer 14 110782 1362096 21b 22a 220a 22b 220b 22c 220c 24 • 26a 30 second conductive layer first resistive layer first open region second resistive layer second open region third resistive layer third open region convex Column metal adhesive layer printing screen