0708004 26304twf.doc/n 九、發明說明： 【發明所屬之技術領域】 是有：：月:於一種線路結構及其製造方法’且特別 疋有關於—種在線路板上轉路結構及其製造方法。 【先前技術】0708004 26304twf.doc/n IX. Description of the invention: [Technical field to which the invention pertains] Yes: Month: In a circuit structure and its manufacturing method' and particularly relevant to the type of circuit structure on the circuit board and its manufacture method. [Prior Art]
在目刖線路板的製程中，當線路板的線路已大致完成 L通常會再製造-層增層鱗，以使祕板上的多個= 塾π排列整齊。這樣可贿這純墊的分佈位置能符合— ，線路板的佈線規格，並且可使晶片、被動元件、主動元 件等外部電子元件容該餘祕板上，*目前上述增層 線路的製造方法與習知線路板製程所採用的增層法 (build-upprocess)大致相同。In the process of witnessing the circuit board, when the circuit board circuit has been substantially completed, L will usually be re-manufactured-layer-enhanced scales so that multiple = 塾π on the secret board are arranged neatly. In this way, the distribution position of the pure pad can conform to the wiring specification of the circuit board, and the external electronic components such as the chip, the passive component, and the active component can be accommodated on the secret board, and the current manufacturing method of the above-mentioned build-up line is The build-up process used in the conventional circuit board process is roughly the same.
圖1A至圖1E是習知一種增層線路的製造方 示意圖。請參關丨A，習知增層線關製造縣包括^ 步驟。首先，提供-線路基板110，其中線路基板11〇包 括二鋼線路層112、114以及一位於銅線路層112與114 之間的介電層116。線路基板11〇内的線路結構基本上已 完成，且此時的線路基板110尚未被防焊層覆蓋，即線路 基板110算是線路板的半成品。 請參閱圖1B，接著，加熱壓合一樹脂層12〇於線路 基板11〇上，其中樹脂層120覆蓋銅線路層112。樹脂層 120通常是膠片（prepreg)，而樹脂層ι2〇在加熱之後^ < S ) 5 1357294. 0708004 26304twf.doc/n 請參閱目1C，之後，進行雷射鑽孔製程，以在樹脂 1二20上喊-開口 m，其中開口 Ηι會局部暴露出銅線 θ 112 ’且開口 Ή1的縱橫比（深度與寬度之比）通常介 ^ο·4至2>4m請參關1D ’接著，先後進行無電電 又法以及有電電鍍法，以在樹脂層12G上形成—銅金屬層 厪3(1以及4電盲孔結構B卜導電盲孔結構151會從銅金 a 130延伸至開〇 H1内，且導電盲孔結構B1會經由開 口 H1連接至銅線路層I!〗。 值付一提的是，在進行雷射鑽孔製程之後，開口 H1 ^底P S殘留些膠〉查，而這些膠潰會造成銅金屬層130 二銅線路層112之間料紐翻不㈣情形。因此，在 ，成銅金屬層130《前，通常會進行去膠渣製程 es^ear) ’以去除這些位於開口 Ηι底部的膠渣。 旦月 > 閱圖1D與圖iE，接著，對銅金屬層⑽進行微 刻製程，以形成一銅線路層13〇,。之後，形成一覆 =·5、·路層130’的防焊層14〇，其中防焊層14〇局部暴露 二，路層13G ’而被防焊層14()所暴露的部分銅線路層 可以作為連接晶#、被動元件、线元件或其他外部 子兀件的接墊。至此，一種線路板100已製造完成。 。由，可知，習知增層線路的製造方法包括雷射鑽孔製 =、去膠凌製程以及微影與蝕刻製程。為了避免良率降低， 田進行雷射鑽孔製程以及微影與侧製程時，皆需要進行 對位耘序。這會使得雷射鑽孔製程以及微影與蝕刻製程需 要花費相當多的時間來進行。 1357294. 0708004 26304twf.doc/n 此外，雷射鑽孔製程所需要的雷射光源設備，其價格 相當昂貴’而微影與侧製程所採用的綠與_藥液也 是很昂責。其次’樹脂層12〇通常是膠#，而膠#的價格 亦是相當高昂。因此’習知增層線路的製造方法i有製造 時間費時以及製造成本過高的缺點。 【發明内容】 本發明是提供-種製造線路板上的線路 法，以降低製造成本。 時間 本發明疋提供-種線路板上的線路結構， 以縮短製造 本發明提出-種製造線路板 包括以下步驟。料，提供—線路板3中m去括其 少一介電層於防焊層上，其中介電層=^ =介電層上。導電圖案層延伸;二== 層經由開口連接至接墊。 円且V電圖案 絕緣材㈣包括印刷一 墨：發二:Π，上述絕緣材料包括熱固型油 高分子介電層熱固型絕緣膜、感光型絕緣膜或 在本1明之-實施例t，上述形成導電圖案層的方法 0708004 26304twtdoc/n 包括印刷—導電H導電膏於介電層上及烘烤導電膠或 導電膏。 ，本發明之一實施例中，上述導電膠包括銅膠、銀 膠二%I膠、奈米銀或導電高分子材料，而導電膏包括鋼膏、 銀育石反月奈米銀或導電向分子材料。 在本發明之一實施例中，上述形成導電圖案層的方法 包括噴，法、滾輪塗佈法、無電讀法、有電電鑛法、藏 鍍法、蒸鍍法、化學氣相沉積或物理氣相沉積。 在本發明之一實施例中，上述接墊的數量為多個而 導電圖案層連接至少一個接墊。 在本發明之一實施例中，更包括形成一保護層於介電 層上，其中保護層配置於導電圖案層上。 在本發明之一實施例中，上述保護層完全覆蓋導電圖 案層或局部暴露導電圖案層。 在本發明之一實施例中，上述介電層的材質與防焊層 的材質可相同或不相同。 本發明提出一種線路板上的線路結構，其適於電性連 接一線路板。線路板包括至少—接墊與一暴露接墊的防焊 層’而線路板上的線路結構包括一介電層以及一導電圖案 層。介電層配置於防焊層上，且介電層具有至少一暴露接 墊的開口。導電圖案層配置於介電層上，並延伸至開口内。 導電圖案層經由開口連接至接墊。 在本發明之一實施例中，上述開口的縱橫比介於0 02 至0.1之間。 1357294 0708004 26304twf.doc/n 在本發明之一實施例中，上述介電層的厚度介於ι〇 微米至30微米之間。 在本發明之一實施例中，上述導電圖案層的厚度介於 10微米至50微米之間。 ' 本發明因採用印刷方式而形成介電層於防焊層上，因 此本發明能在不經由加熱壓合樹脂層、雷射鑽孔製程以及 去膠渣製程的前提下，直接形成介電層於線路板的防焊層 上。相較於習知技術而言，本發明能降低製造成本以及縮 短製造時間。 ' 為讓本發明之特徵和優點能更明顯易懂，下文特舉較 佳實施例’並配合所附圖式，作詳細說明如下。 【實施方式】 【第一實施例】 圖2疋本發明第一實施例之線路板上的線路結構之剖 面不意圖。請參閱圖2,本實施例之線路板上的線路結構 300能電性連接一線路板2〇〇,其中線路板2〇〇為已製造完 成的成απ，而線路板200包括多個接塾210與一防焊芦 220 〇 ”曰 圖2所示的線路板200雖然包括二個接墊21〇，但是 在其他未有圖式揭露的實施例中，線路板200可以包括一 個接墊210或二個以上的接墊21〇。此外，圖2所示的防 焊層220之類型雖然為防焊層定義（Solder Mask Define, SMD)，但是在其他未繪示實施例中，防焊層220之類型 1357294 0708004 26304twf.doc/n 也可以是非防焊層定義（N〇n S〇lder Mask Defm NSMD)。 線路板上的線略結構300包括一介電層310以及一導 電圖案層32〇。介電層mo配置於防焊層上且介電 ^ 310具有多個暴露接墊210的開口 H2。雖然圖2所示的 ”電層310具有一個開口 H2，但是根據線路板2㈨所包括 的接塾210之數置’介電層31〇亦可以具有一個開口 或是二個以上的開口 H2。 此外’ 電層310可由印刷一絕緣材料而形成，而該 、名緣材料包括熱固型油墨、樹脂、顯影型油墨、孰固型絕 緣膜、感姑絕_或高分子介電層，其帽㈣;絕緣材 料的方法可包括鋼板印刷、網板印刷或其他適#的印刷方 法。當然，介電層310的製作方法亦可以包括喷塗、顯影、 滚輪塗佈、無電電鍍、麟、蒸鍍、化學氣相沉積或物理 氣相沉積。 導電圖案層320配置於介電層310上，而且導電圖案 層320延伸至這些開口 H2内，並且經由這些開口 H2連接 至這些接墊210。導電圖案層320的較佳厚度可以在1〇微 米至50微米之間，而導電圖案層320可由印刷一導電膠或 一導電膏而形成，而導電膠與導電膏的差異在於二者的雷 諾數（Reynolds number)不同。 詳細而吕’導電备的雷諾數比導電膏大，即導電膠比 導電膏易於流動。上述的導電膠可以是鋼膠、銀朦、碳膠 或是其他低電阻係數的金屬膠，而導電膏可以是銅膏、銀 0708004 263〇4twf.doc/n 霄、碳膏或是其他低電阻係數的金屬膏。此外，導 導電膏也可以包括奈米銀、導電高分子材料或是 成方法所製成的非金屬材料。印刷導電膠或導電膏的方法 可包括鋼板印刷、網板印刷或其他適當的印刷方法。 、從上述内容得知，導電圖案層320與介電層310皆可 、用印刷的方式而形成。因此，相較於習知技術而言（請 參考圖1E)，導電圖案層32〇以及介電層31〇在結構上^ 圖1E所示的銅線路層13〇,以及樹脂層12〇有所不同。詳 細而έ，導電圖案層32〇在開口 H2處的表面較為平坦（如 圖2所示）。其次’習知技術的開口 H1之側壁（Sidewall) 争乂為陡峭，介電層310的開口 H2之側壁反而較為平緩。 因此，介電層310的開口 H2具有較小的縱橫比，其值可 介於0.02至0.1之間。 線路板上的線路結構3〇〇更可以包括一保護層33〇， 其中保護層330配置於導電圖案層320上，而保護層330 的厚度介於10微米至30微米之間。保護層330可以完全 覆蓋導電圖案層320,以保護導電圖案層320,進而避免導 電圖案層320受到損傷。此外，保護層330的材質可以與 介電層310或防焊層220相同。 另外’在本實施例中，導電圖案層320可以作為一種 跳線（jumper)，例如導電圖案層320可以連接至少一個 接塾210,或是連接其中一個接墊210與另一個接墊21〇。 再者’端視不同的電路設計之需求，導電圖案層320也可 以連接三個接墊21〇。當然，導電圖案層320更可以連接 1357294 . 0708004 26304twf.doc/n 四個或四個以上之接墊210，而且這些接墊21〇不會因為 與導電圖案層320連接而發生短路。此外’線路板2〇〇的 相對二表面上也可以分別配置二個線路板上的線路結構 300。 以上僅介紹線路板上的線路結構的構造，接下來 將配合圖3A至圖3D，對線路板上的線路結構3〇〇之製造 方法進行詳細的說明。1A to 1E are schematic views showing a manufacturing method of a conventional build-up line. Please refer to A, and the knowledge-added line to the manufacturing county includes ^ steps. First, a circuit substrate 110 is provided, wherein the circuit substrate 11 includes two steel circuit layers 112, 114 and a dielectric layer 116 between the copper circuit layers 112 and 114. The circuit structure in the circuit substrate 11 is substantially completed, and the circuit substrate 110 at this time is not covered by the solder resist layer, that is, the circuit substrate 110 is regarded as a semi-finished product of the circuit board. Referring to Fig. 1B, a resin layer 12 is then heat-bonded to the wiring substrate 11, wherein the resin layer 120 covers the copper wiring layer 112. The resin layer 120 is usually a film (prepreg), and the resin layer ι2〇 is heated. <S) 5 1357294. 0708004 26304twf.doc/n Please refer to item 1C, after which a laser drilling process is performed to the resin 1 On the 20th, the shouting-opening m, in which the opening Ηι will partially expose the copper wire θ 112 ' and the aspect ratio of the opening Ή 1 (the ratio of the depth to the width) is usually referred to as ^ο·4 to 2> 4m, please refer to 1D 'Next, The electroless plating method and the electroplating method are successively performed to form a copper metal layer 厪3 on the resin layer 12G (1 and 4 electric blind hole structure B. The conductive blind hole structure 151 extends from the copper gold a 130 to the opening In H1, and the conductive blind hole structure B1 is connected to the copper circuit layer I! via the opening H1. It is worth mentioning that after performing the laser drilling process, the opening H1 ^ bottom PS remains some glue> These glues can cause the copper metal layer 130 to be turned over between the two copper circuit layers 112. Therefore, in the copper metal layer 130, "the desmear process is usually performed es^ear" to remove these a slag located at the bottom of the opening Ηι. Dan > Referring to Figure 1D and Figure iE, the copper metal layer (10) is then micro-etched to form a copper circuit layer 13?. Thereafter, a solder resist layer 14A of the overlying layer 5' is formed, wherein the solder resist layer 14 is partially exposed, and the portion of the copper layer of the via layer 13G' is exposed by the solder resist layer 14 It can be used as a pad for connecting crystal #, passive components, wire components or other external components. So far, a circuit board 100 has been manufactured. . It can be seen that the manufacturing method of the conventional build-up line includes laser drilling system, de-gelling process, and lithography and etching process. In order to avoid the yield reduction, the field needs to perform the alignment sequence when performing laser drilling process and lithography and side process. This can take a considerable amount of time to perform the laser drilling process as well as the lithography and etching processes. 1357294. 0708004 26304twf.doc/n In addition, the laser source equipment required for laser drilling processes is quite expensive, and the green and _ liquid used in lithography and side processes is also very high. Secondly, the resin layer 12 is usually a glue #, and the price of the glue # is also quite high. Therefore, the manufacturing method i of the conventional build-up wiring has the disadvantages of time-consuming manufacturing time and excessive manufacturing cost. SUMMARY OF THE INVENTION The present invention provides a wiring method for manufacturing a circuit board to reduce manufacturing costs. Time The present invention provides a circuit structure on a circuit board to shorten manufacturing. The present invention provides a circuit board comprising the following steps. Material, provided - in the circuit board 3 m to include a dielectric layer on the solder mask, wherein the dielectric layer = ^ = dielectric layer. The conductive pattern layer extends; two == the layer is connected to the pad via the opening. And the V-electric pattern insulating material (4) comprises printing one ink: hair two: Π, the above insulating material comprises a thermosetting oil polymer dielectric layer thermosetting insulating film, a photosensitive insulating film or in the present invention - an embodiment t The above method for forming a conductive pattern layer is 0800004 26304twtdoc/n, which comprises printing a conductive-conductive H conductive paste on the dielectric layer and baking the conductive paste or the conductive paste. In one embodiment of the present invention, the conductive paste comprises copper glue, silver glue II% I gel, nano silver or conductive polymer material, and the conductive paste comprises steel paste, silver yishite anti-moon nano silver or conductive direction. Molecular material. In an embodiment of the invention, the method for forming the conductive pattern layer comprises a spray method, a roller coating method, a non-electric reading method, an electro-electric ore method, a Tibetan plating method, an evaporation method, a chemical vapor deposition method or a physical gas. Phase deposition. In an embodiment of the invention, the number of the pads is plural and the conductive pattern layer is connected to at least one pad. In an embodiment of the invention, the method further includes forming a protective layer on the dielectric layer, wherein the protective layer is disposed on the conductive pattern layer. In one embodiment of the invention, the protective layer completely covers the conductive pattern layer or the partially exposed conductive pattern layer. In an embodiment of the invention, the material of the dielectric layer and the material of the solder resist layer may be the same or different. The present invention provides a wiring structure on a circuit board that is adapted to be electrically connected to a circuit board. The circuit board includes at least a pad and a solder resist layer of the exposed pad, and the wiring structure on the circuit board includes a dielectric layer and a conductive pattern layer. The dielectric layer is disposed on the solder resist layer, and the dielectric layer has at least one opening that exposes the pad. The conductive pattern layer is disposed on the dielectric layer and extends into the opening. The conductive pattern layer is connected to the pad via the opening. In an embodiment of the invention, the opening has an aspect ratio between 0 02 and 0.1. 1357294 0708004 26304twf.doc/n In one embodiment of the invention, the dielectric layer has a thickness between ι and 10 microns. In an embodiment of the invention, the conductive pattern layer has a thickness of between 10 microns and 50 microns. The present invention forms a dielectric layer on the solder resist layer by using a printing method. Therefore, the present invention can directly form a dielectric layer without heating the resin layer, the laser drilling process, and the desmear process. On the solder mask of the board. The present invention can reduce manufacturing costs and shorten manufacturing time compared to conventional techniques. To make the features and advantages of the present invention more comprehensible, the following detailed description of the preferred embodiments and the accompanying drawings are set forth below. [Embodiment] [First Embodiment] Fig. 2 is a cross-sectional view showing a line structure of a circuit board according to a first embodiment of the present invention. Referring to FIG. 2, the circuit structure 300 on the circuit board of the embodiment can be electrically connected to a circuit board 2, wherein the circuit board 2 is manufactured to be απ, and the circuit board 200 includes a plurality of interfaces. 210 and a solder resist 220. The circuit board 200 shown in FIG. 2 includes two pads 21, but in other embodiments not disclosed, the circuit board 200 may include a pad 210 or Two or more pads 21 〇. In addition, the type of the solder resist 220 shown in FIG. 2 is a Solder Mask Define (SMD), but in other embodiments not shown, the solder resist 220 The type 1357294 0708004 26304twf.doc/n may also be a non-solder mask definition (N〇n S〇lder Mask Defm NSMD). The line structure 300 on the board includes a dielectric layer 310 and a conductive pattern layer 32〇. The dielectric layer mo is disposed on the solder resist layer and the dielectric 310 has a plurality of openings H2 exposing the pads 210. Although the "electric layer 310" shown in FIG. 2 has an opening H2, the connections according to the circuit board 2 (9) are included. The number of 塾210 can be set to 'dielectric layer 31 〇 can also have one opening or two The opening H2. In addition, the electric layer 310 may be formed by printing an insulating material including a thermosetting ink, a resin, a developing ink, a sturdy insulating film, a smear or a polymer dielectric layer, and a cap thereof. (d); The method of insulating material may include steel plate printing, screen printing or other printing methods. Of course, the dielectric layer 310 can also be fabricated by spraying, developing, roller coating, electroless plating, lining, evaporation, chemical vapor deposition or physical vapor deposition. The conductive pattern layer 320 is disposed on the dielectric layer 310, and the conductive pattern layer 320 extends into the openings H2 and is connected to the pads 210 via the openings H2. The preferred thickness of the conductive pattern layer 320 may be between 1 μm and 50 μm, and the conductive pattern layer 320 may be formed by printing a conductive paste or a conductive paste, and the difference between the conductive paste and the conductive paste is the Reynolds number of the two. (Reynolds number) is different. In detail, the Reynolds number of the conductive device is larger than that of the conductive paste, that is, the conductive paste is easier to flow than the conductive paste. The conductive paste may be steel glue, silver enamel, carbon glue or other low-resistance metal glue, and the conductive paste may be copper paste, silver 0708004 263 〇 4 twf. doc/n 霄, carbon paste or other low resistance. Coefficient of metal paste. Further, the conductive paste may also include nano silver, a conductive polymer material or a non-metal material produced by a method. The method of printing a conductive paste or a conductive paste may include steel plate printing, screen printing, or other suitable printing method. It can be seen from the above that the conductive pattern layer 320 and the dielectric layer 310 can be formed by printing. Therefore, compared with the prior art (please refer to FIG. 1E), the conductive pattern layer 32 and the dielectric layer 31 are structurally formed on the copper wiring layer 13A shown in FIG. 1E, and the resin layer 12 is formed. different. Detailed and detailed, the surface of the conductive pattern layer 32 at the opening H2 is relatively flat (as shown in Fig. 2). Secondly, the side wall of the opening H1 of the prior art is steep, and the side wall of the opening H2 of the dielectric layer 310 is rather gentle. Therefore, the opening H2 of the dielectric layer 310 has a small aspect ratio and may have a value between 0.02 and 0.1. The wiring structure 3 on the circuit board may further include a protective layer 33, wherein the protective layer 330 is disposed on the conductive pattern layer 320, and the protective layer 330 has a thickness of between 10 micrometers and 30 micrometers. The protective layer 330 may completely cover the conductive pattern layer 320 to protect the conductive pattern layer 320, thereby preventing the conductive pattern layer 320 from being damaged. In addition, the material of the protective layer 330 may be the same as that of the dielectric layer 310 or the solder resist layer 220. In the present embodiment, the conductive pattern layer 320 can be used as a jumper. For example, the conductive pattern layer 320 can be connected to at least one of the interfaces 210, or one of the pads 210 can be connected to the other of the pads 210. Furthermore, the conductive pattern layer 320 can also be connected to the three pads 21〇 depending on the requirements of different circuit designs. Of course, the conductive pattern layer 320 can be connected to the 1357294. 0708004 26304twf.doc/n four or more pads 210, and the pads 21 are not short-circuited by the connection with the conductive pattern layer 320. Further, the line structures 300 on the two boards may be separately disposed on the opposite surfaces of the circuit board 2''. The above describes only the structure of the line structure on the circuit board. Next, the manufacturing method of the line structure 3A on the circuit board will be described in detail in conjunction with Figs. 3A to 3D.
制止圖3A至圖3D是圖2中線路板上的線路結構3〇〇之 製造方法的流㈣意圖。請參關从，本實關之線路板 上的線路結構之製造方法包括下列步驟1先，提供 ，^板200 ’其中線路板2〇〇包括多個接墊以及一暴 露這些接墊210的防焊層22〇。 晴參閱圖3B ’接著’形成介電層310於防焊層220 上’其中介電層310具有多個暴露這些接塾21()的開口 ^形成介電層31G的方法可以是印糖_油墨、樹脂、 同刀f’丨電層或其他絕緣材料於防焊層22〇上。當介電層 法/由I刷熱固型油墨而形成時，形成介電層310的方 # ^以轉烤該絕緣材料。如此，絕緣材料得以而 形成介電層31〇。 人參閱圖扣，接著，形成至少—導電圖案層320於 i可=上。在本實施例中，形成導電圖案層320的方 ΪΙ導電膠或導電膏於介電層31G上。當導電圖 ^印刷導電膠或導電膏而形成時，形成導電圖 導導是烘烤料1膠或料電I如此， 料導電貧得以固化而形成導電圖案層320。 12 1357294 0708004 26304twf.doc/n 導電圖案層320除了可以由印刷導電朦或印刷導電膏 而形成之外，本實施例還具有其他形成導電圖案層32〇的 方法，例如喷塗法（spray coating)、滾輪塗佈法、無電電 鑛法、有電電鐘法、藏鍍法（sputter)、蒸鑛法、化學氣 相沉積（Chemical Vapor Deposition, CVD)或物理氣相沉 積（Physical Vapor Deposition, PVD )。 當導電圖案層320是由上述方法所形成時，包括以下 步驟。首先，形成一全面性覆蓋介電層310、防焊層220 以及這些接墊210的導電膜層。之後，再進行微影與餘刻 製程，以移除部份導電膜層’進而形成導電圖案層32〇。 在導電圖案層320形成之後’基本上，一種線路板上的線 路結構300已製造完成。 請參閱圖3D，之後’可以形成一保護層330於介電 層310上，其中保護層330可以全面性覆蓋導電圖案層 320’而保護層330的形成方法與材質可以與介電層31〇 或防焊層220相同。 【第二實施例】 圖4是本發明第二實施例之線路板上的線路結構之剖 面示意圖。請參閱圖4，本實施例之線路板上的線路結構 400適於電性連接一線路板200’，其中線路板2〇〇,包括至 少一接墊210’以及一防焊層220’，而線路板上的線路結構 400包括一介電層410、一導電圖案層420以及一保護層 430。須事先說明的是，雖然圖4僅繪示一個接墊21〇,， 但在本實施例中，線路板200,亦可以包括多個接塾21〇,， 故圖4中的接墊210,之數量並非限定本發明。 < S ) 13 1357294 · 0708004 26304twf.doc/n 線路板上的線路結構4〇〇的形成方法、材質以及結 皆與第一實施例相似，故不再重複介紹，惟線路板上的線 路，構働與第一實施例的差異之處在於保護層43〇局部 覆蓋導電®案420。也就是說，倾層43()局部暴露 圖案420。 ^ 詳細而言，導電圖案420被保護層43〇所暴露的部分 (圖4中虛線所圍繞的部分）可作為連接晶片、被動元件、 • 絲兀件或其他外部電子元件的接墊，也就是說，導電圖 案420能連接上述外部電子元件。 综上所述，本發明之線路板上的線路結構，其介電層 是藉由印刷絕緣材料於線路板的防焊層上而形成。因此: ' 本發明能在不經由加熱壓合樹脂層、雷射鑽孔製程以及去 膠渣製程的前提下，直接形成介電層於線路=防= 上。相較於習知技術而言，本發明的製造線路板上的線路 結構之方法能大幅降低製造成本以及有效縮短製造時間。 纟次’藉由印刷導電膠或印刷導電#，本發明能在介 擊騎上直娜成導觸錢，錢經由郷熟刻製程。 因此’本發明的製造線路板上的線路結構之方法可不必採 ^光阻與_藥液。這樣可崎低線路板上的線路結構在 以造過程所產生的污染物，以符合環保的需求。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何熟f本發明所屬領域之具有通常知識 者，在不脫離本發明之精神和範圍内，當可作些許之更動 與潤御，因此本發明之保護範圍當視後附之 所界定者為進。 丁《寻~孝巳 1357294 . 0708004 26304twf.doc/n 【圖式簡單說明】 造方法的流程 圖1A至圖1E是習知一種增層線路的徵 示意圖。 圖2是本發明第一實施例之線路板上的 面示意圖。 〜構之剖 圖3A至圖3D是圖2中線路板上的線路結構3〇〇 製造方法的流程示意圖。 之Fig. 3A to Fig. 3D are diagrams showing the flow (four) of the manufacturing method of the line structure 3A on the circuit board of Fig. 2. Please refer to the manufacturing method of the circuit structure on the circuit board of the present invention, including the following step 1, first, providing, the board 200' wherein the circuit board 2 includes a plurality of pads and an anti-exception of the pads 210 The solder layer 22 is. Referring to FIG. 3B, 'subsequently, a dielectric layer 310 is formed on the solder resist layer 220. The dielectric layer 310 has a plurality of openings exposing the interfaces 21 (). The method of forming the dielectric layer 31G may be a printing ink. , resin, the same knife f' 丨 electric layer or other insulating material on the solder mask 22 〇. When the dielectric layer method is formed by I brushing the thermosetting ink, the square of the dielectric layer 310 is formed to turn the insulating material. Thus, the insulating material is formed to form the dielectric layer 31. Referring to the figure, then at least the conductive pattern layer 320 is formed on i can be =. In the present embodiment, a conductive paste or a conductive paste of the conductive pattern layer 320 is formed on the dielectric layer 31G. When the conductive pattern is formed by printing a conductive paste or a conductive paste, the conductive pattern is formed to be the baking material 1 or the material I, and the conductive poor is cured to form the conductive pattern layer 320. 12 1357294 0708004 26304twf.doc/n The conductive pattern layer 320 can be formed by printing a conductive paste or a printed conductive paste, and the present embodiment has other methods of forming the conductive pattern layer 32, such as spray coating. , roller coating method, electroless ore method, electric clock method, sputtering method, steaming method, chemical vapor deposition (CVD) or physical vapor deposition (PVD) . When the conductive pattern layer 320 is formed by the above method, the following steps are included. First, a comprehensive covering dielectric layer 310, a solder resist layer 220, and a conductive film layer of these pads 210 are formed. Thereafter, a lithography and a remnant process is performed to remove a portion of the conductive film layer' to form a conductive pattern layer 32. After the formation of the conductive pattern layer 320 'substantially, the wiring structure 300 on one of the wiring boards has been completed. Referring to FIG. 3D, a protective layer 330 may be formed on the dielectric layer 310. The protective layer 330 may cover the conductive pattern layer 320 ′ in a comprehensive manner. The forming method and material of the protective layer 330 may be formed on the dielectric layer 31 or The solder resist layer 220 is the same. [Second Embodiment] Fig. 4 is a cross-sectional view showing the structure of a line on a circuit board according to a second embodiment of the present invention. Referring to FIG. 4, the circuit structure 400 on the circuit board of the present embodiment is adapted to be electrically connected to a circuit board 200', wherein the circuit board 2 includes at least one pad 210' and a solder resist layer 220'. The wiring structure 400 on the circuit board includes a dielectric layer 410, a conductive pattern layer 420, and a protective layer 430. It should be noted that although FIG. 4 only shows one pad 21〇, in the embodiment, the circuit board 200 may also include a plurality of interfaces 21〇, so the pads 210 in FIG. 4, The number is not intended to limit the invention. <S) 13 1357294 · 0708004 26304twf.doc/n The formation method, material and junction of the circuit structure 4〇〇 on the circuit board are similar to those of the first embodiment, so the description will not be repeated, but the circuit on the circuit board, The configuration differs from the first embodiment in that the protective layer 43 is partially covered by the conductive pattern 420. That is, the pour layer 43() partially exposes the pattern 420. ^ In detail, the portion of the conductive pattern 420 exposed by the protective layer 43A (the portion surrounded by the broken line in FIG. 4) can be used as a pad for connecting a wafer, a passive component, a wire component or other external electronic component, that is, It is said that the conductive pattern 420 can connect the above external electronic components. In summary, the wiring structure of the circuit board of the present invention has a dielectric layer formed by printing an insulating material on the solder resist layer of the circuit board. Therefore: 'The present invention can directly form a dielectric layer on the line = anti-proof without pre-pressing the resin layer, the laser drilling process, and the desmear process. Compared with the prior art, the method of manufacturing a wiring structure on a circuit board of the present invention can greatly reduce the manufacturing cost and effectively shorten the manufacturing time. By the time of printing conductive paste or printing conductive #, the present invention can be used to guide the ride on the direct ride to the money, and the money is processed through the process. Therefore, the method of manufacturing the wiring structure of the wiring board of the present invention does not require the use of photoresist and liquid medicine. This can reduce the line structure on the circuit board in the process of production of pollutants to meet environmental requirements. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and the invention may be practiced otherwise without departing from the spirit and scope of the invention. The scope of protection of the present invention is determined by the appended claims. Ding "seeking ~ filial piety 1357294 . 0708004 26304twf.doc / n [Simple diagram of the process] Flow chart of the method of manufacture Figure 1A to Figure 1E is a schematic diagram of a conventional layer-added circuit. Fig. 2 is a schematic view showing the surface of the circuit board of the first embodiment of the present invention. Section 3A to Fig. 3D is a flow chart showing the manufacturing method of the line structure 3〇〇 on the circuit board of Fig. 2. It
圖4是本發明第二實施例之線路板上的線路結構之 面示意圖。 【主要元件符號說明】 100、200、200’ ：線路板 110 .線路基板 112、114、130’ ：鋼線路層 116、310、410 :介電層 120 :樹脂層 130 :銅金屬層 140、220、220，：防焊層 210、210’ ：接墊 300、400 :線路板上的線路結構 320、420 :導電圖案層 330、430 :保護層 B1 :導電盲孔結構 HI、H2 :開口Fig. 4 is a schematic view showing the structure of a line on a circuit board according to a second embodiment of the present invention. [Description of main component symbols] 100, 200, 200': circuit board 110. circuit substrate 112, 114, 130': steel wiring layer 116, 310, 410: dielectric layer 120: resin layer 130: copper metal layer 140, 220 , 220,: solder resist layer 210, 210': pads 300, 400: circuit structure 320, 420 on the circuit board: conductive pattern layer 330, 430: protective layer B1: conductive blind hole structure HI, H2: opening
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