TW200938043A - Wire structure on circuit board and method for fabricating the same - Google Patents

Wire structure on circuit board and method for fabricating the same Download PDF

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TW200938043A
TW200938043A TW97106991A TW97106991A TW200938043A TW 200938043 A TW200938043 A TW 200938043A TW 97106991 A TW97106991 A TW 97106991A TW 97106991 A TW97106991 A TW 97106991A TW 200938043 A TW200938043 A TW 200938043A
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Taiwan
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layer
circuit board
conductive pattern
manufacturing
conductive
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TW97106991A
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Chinese (zh)
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TWI357294B (en
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Chen-Chuan Chang
Shang-Lin Sung
Tseng-Hsien Lin
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Unimicron Technology Corp
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Abstract

A wire structure on circuit board suitable for connecting to a circuit board is provided. The circuit board includes at least a pad, and a solder mask exposing the pad. The wire structure on circuit board includes a dielectric layer and a conductive pattern layer. The dielectric layer is disposed on the solder mask, and the dielectric layer has at least a hole exposing the pad. The conductive pattern layer is disposed on the dielectric layer and stretched in the hole. The conductive pattern layer is connected to the pad through the hole. Besides, a method for fabricating the wire structure on circuit board is provided, too.

Description

200938043200938043

Itw^doc/n 九、發明說明: 【發明所屬之技術領域】 β本發明是有關於一種線路結構及其製造方法,且特別 是有關於一種在線路板上的線路結構及其製造方法。 【先前技術】 在目前線路板的製程中,當線路板的線路已大致完成 ❻ 時,通常會再製造一層增層線路,以使線路板上的多二接 墊月t*排列整齊。這樣可以使這些接塾的分佈位置能符合一 些線路板的佈線規格,並且可使晶片、被動元件、主動元 件等外。卩電子元件谷易組裝在線路板上,而目前上述增層 線路的製造方法與習知線路板製程所採用的增層法 (build-up process)大致相同。 一圖1A至圖1E是習知一種增層線路的製造方法的流程 示意圖。請參閱圖1A,習知增層線路的製造方法包括以下 步驟。首先,提供一線路基板11〇,其中線路基板u〇包 括二銅線路層112、114以及一位於銅線路層112與114 之間的介電層116。線路基板11〇内的線路結構基本上已 完成,且此時的線路基板110尚未被防焊層覆蓋,即線路 基板110算是線路板的半成品。 請參閱圖1B ’接著’加熱壓合一樹脂層12〇於線路 基板110上’其中樹脂層12〇覆蓋銅線路層η]。樹脂層 120通常是膠片(Prepreg) ’而樹脂層12G在加熱之後會 固化。 twf.doc/n 200938043 請參閱圖1C,之後,進行雷射鑽孔製程,以在樹脂 層120上形成一開口 H1 ’其中開口 H1會局部暴露出銅線 路層112 ’且開口 H1的縱横比(深度與寬度之比)通常介 於0.4至2.4之間。請參閱圖m,接著,先後進行無電電 鍍法以及有電電鍍法,以在樹脂層12〇上形成一銅金屬層 130以及一導電盲孔結構B1。導電盲孔結構B1會從銅金It is a technical field of the invention. The present invention relates to a circuit structure and a method of manufacturing the same, and more particularly to a circuit structure on a circuit board and a method of fabricating the same. [Prior Art] In the current circuit board process, when the circuit board circuit has been substantially completed, a layer of additional layer is usually fabricated to make the multiple pads of the circuit board lined up neatly. This allows the locations of these interfaces to conform to the wiring specifications of some boards and allows wafers, passive components, active components, and the like. The 卩 electronic component 谷易 is assembled on the circuit board, and the current method of manufacturing the above-mentioned build-up line is substantially the same as the build-up process used in the conventional circuit board process. 1A to 1E are schematic flow charts showing a conventional method of manufacturing a build-up line. Referring to FIG. 1A, a conventional method for manufacturing a build-up line includes the following steps. First, a wiring substrate 11 is provided, wherein the wiring substrate u includes a copper wiring layer 112, 114 and a dielectric layer 116 between the copper wiring layers 112 and 114. The circuit structure in the circuit substrate 11 is substantially completed, and the circuit substrate 110 at this time is not covered by the solder resist layer, that is, the circuit substrate 110 is regarded as a semi-finished product of the circuit board. Referring to Fig. 1B', then 'heating and pressing a resin layer 12 on the wiring substrate 110' where the resin layer 12 is covered with the copper wiring layer η]. The resin layer 120 is usually a film (Prepreg)' and the resin layer 12G is cured after heating. Twf.doc/n 200938043 Please refer to FIG. 1C, after which a laser drilling process is performed to form an opening H1 on the resin layer 120, wherein the opening H1 partially exposes the copper wiring layer 112' and the aspect ratio of the opening H1 ( The ratio of depth to width is usually between 0.4 and 2.4. Referring to Figure m, electroless plating and electroplating are sequentially performed to form a copper metal layer 130 and a conductive blind via structure B1 on the resin layer 12A. Conductive blind hole structure B1 will be from copper gold

屬層130延伸至開n H1内’且導電盲孔結構B1會經由開 口 H1連接至銅線路層ι12。 值付一提的是,在進行雷射鑽孔製程之後,開口 的底部會殘留-些膠潰,而這些膠逢會造成銅金屬層13〇 與銅線路層112之間發生電性接觸不良的情形。因此,在 开^成銅金屬層13G之前,通常會進行去膠渣製程 (desmear),以去除這些位於開口 m底部的膠潰。 晴參關1D與圖m,接著,對銅金屬 製程’以形成一銅線路層13〇,。之後,形 的防焊層140,其中防焊層140局部暴露 130,可“為連接層動:所^ 電子元心㈣動件、主動元件或其他外部 由塾。至此,一種線路板刚已製造完成。 程、去膠料驗枝扯雷射鑽孔製 當進行雷了^率降低, 相序當孔製程一刻= 6 200938043The genus layer 130 extends into the opening n H1 and the conductive blind via structure B1 is connected to the copper wiring layer ι12 via the opening H1. It is worth mentioning that after the laser drilling process, there will be some glue collapse at the bottom of the opening, and these glues will cause electrical contact between the copper metal layer 13〇 and the copper circuit layer 112. situation. Therefore, before the copper metal layer 13G is opened, a desmear process is usually performed to remove the glue at the bottom of the opening m. The ginseng is 1D and the figure m, and then, the copper metal process is formed to form a copper circuit layer 13 〇. Thereafter, the shape of the solder resist layer 140, wherein the solder resist layer 140 is partially exposed 130, can be "moving for the connection layer: the electron element (four) moving parts, active components or other external elements. Thus, a circuit board has just been manufactured. Finished. Cheng, go to the rubber material inspection and tear laser drilling system when the mine is reduced, the rate is reduced, the phase sequence is the hole process moment = 6 200938043

Jtwfdoc/n 此外,雷射鑽孔製程所需要的雷射光源設備,其價格 相當昂貴’而微影與蝕刻製程所採用的光阻與蝕刻藥液也 是很昂貴。其次,樹脂層120通常是膠片,而膠片的價格 亦是相當高昂。因此,習知增層線路的製造方法具有製造 時間費時以及製造成本過高的缺點。 【發明内容】 ❹ 本發明是提供一種製造線路板上的線路結構之方 法,以降低製造成本。Jtwfdoc/n In addition, the laser source equipment required for laser drilling processes is quite expensive, and the photoresist and etching solutions used in lithography and etching processes are also expensive. Second, the resin layer 120 is usually film, and the price of the film is also quite high. Therefore, the manufacturing method of the conventional build-up wiring has the disadvantages of time-consuming manufacturing time and excessive manufacturing cost. SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a wiring structure on a wiring board to reduce manufacturing costs.

本發明是提供一種線路板上的線路結構,以縮短製造 時間。 V 本發明提出一種製造線路板上的線路結構之方法,其 包括以下步驟。首先,提供一線路板,其中線路板包括〆 防焊層與至少一接墊,而防焊層暴露接墊。接著,形成奚 ·’ 71電層於防焊層上,其中介電層具有至少一暴露接费 ❺ 的開口。接著,形成至少一導電圖案層其中導電圖案層 配置於介電層上。導電圖案層延伸至開口内,且導電^案 層經由開口連接至接墊。 在本發明之一實施例中,上述形成介電層包括印刷_ 絕緣材料於防焊層上及烘烤該絕緣材料。 在本發明之一實施例中,上述絕緣材料包括熱固型油 ,、樹脂、顯影型油墨、熱固型絕緣膜、感光型絕緣膜威 高分子介電層。 在本發明之一實施例中,上述形成導電圖案層的方法 7 200938043 ------- ttwf.doc/n 3括印刷—導電膠或—導電膏於介電層上及烘烤導電勝或 V電膏。 在本發明之一實施例中,上述導電膠包括銅膠、銀 膠、碳膠山、奈米銀或導電高分子材料,而導電膏包括銅膏、 銀《石反用、奈米銀或導電1¾分子材料。 在本發明之一實施例中,上述形成導電圖案層的方法 包括嘴,法、滚輪塗佈法、無電電鍍法、有電電鑛法、錢 ❹ 鍍法、蒸鍍法、化學氣相沉積或物理氣相沉積。 在本發明之—實施例中,上述接墊的數量為多個,而 導電圖案層連接至少一個接墊。 在本發明之一實施例中,更包括形成一保護層於介電 層上,其中保護層配置於導電圖案層上。 在本發明之一實施例中,上述保護層完全覆蓋導電圖 案層或局部暴露導電圖案層。 在本發明之-實施例中,上述介電層的材質與防 的材質可相同或不相同。 #曰 ❿ 本發明提出-種線路板上的線路結構,其適於電性連 接-線路板。線路板包括至少—料與一暴露接塾的 層’而線路板上的線路結構包括—介電層以及—導電 電層2於防焊層上,且介電層具有至少-暴露接 塾的4 口導電圖案層配置於介電層上,並延伸至開口内。 導電圖案層經由開口連接至接塾。 至上本,明之_實施例中’上述開口的縱橫比介於_ 200938043 ^fdoc/n 在本發明之一實施例中 微米至30微米之間。 上述介電層的厚度介於10 導電圖案層的厚度介於 在本發明之一實施例中,上述 10微米至50微米之間。 本發明因採用印刷方式而形成介電層於防焊層上,因 此本發明能在不經由加熱壓合樹脂層、雷射 去雜製程的前提下,直接形成介電層於線路SUMMARY OF THE INVENTION The present invention is to provide a wiring structure on a circuit board to shorten manufacturing time. V The present invention proposes a method of manufacturing a wiring structure on a wiring board, which comprises the following steps. First, a wiring board is provided, wherein the wiring board includes a solder resist layer and at least one pad, and the solder resist layer exposes the pads. Next, an electrical layer of 奚·' 71 is formed on the solder resist layer, wherein the dielectric layer has at least one opening that exposes the charge. Next, at least one conductive pattern layer is formed, wherein the conductive pattern layer is disposed on the dielectric layer. The conductive pattern layer extends into the opening and the conductive layer is connected to the pad via the opening. In an embodiment of the invention, the forming the dielectric layer comprises printing an insulating material on the solder resist layer and baking the insulating material. In an embodiment of the invention, the insulating material comprises a thermosetting oil, a resin, a developing ink, a thermosetting insulating film, and a photosensitive insulating film. In an embodiment of the present invention, the method 7 for forming a conductive pattern layer is included in a printing-conductive paste or a conductive paste on a dielectric layer and baking conductively. Or V cream. In an embodiment of the invention, the conductive paste comprises copper glue, silver glue, carbon glue mountain, nano silver or conductive polymer material, and the conductive paste comprises copper paste, silver "stone reverse, nano silver or conductive" 13⁄4 molecular material. In an embodiment of the invention, the method for forming the conductive pattern layer comprises a nozzle, a method, a roller coating method, an electroless plating method, an electroforming method, a gold plating method, an evaporation method, a chemical vapor deposition method or a physical method. Vapor deposition. In an embodiment of the invention, the number of the pads is plural, and the conductive pattern layer is connected to at least one of the pads. In an embodiment of the invention, the method further includes forming a protective layer on the dielectric layer, wherein the protective layer is disposed on the conductive pattern layer. In one embodiment of the invention, the protective layer completely covers the conductive pattern layer or the partially exposed conductive pattern layer. In the embodiment of the present invention, the material of the dielectric layer may be the same or different from the material of the prevention. #曰 ❿ The present invention proposes a circuit structure on a circuit board that is suitable for electrical connection-circuit boards. The circuit board includes at least a layer of exposed material and a wiring structure on the circuit board including a dielectric layer and a conductive electrical layer 2 on the solder resist layer, and the dielectric layer has at least - exposed contacts 4 The conductive pattern layer is disposed on the dielectric layer and extends into the opening. The conductive pattern layer is connected to the interface via the opening. In the above, the aspect ratio of the above opening in the embodiment is between _200938043 and fdoc/n in one embodiment of the invention between micrometers and 30 micrometers. The thickness of the dielectric layer described above is 10 and the thickness of the conductive pattern layer is between 10 microns and 50 microns in one embodiment of the invention. The present invention forms a dielectric layer on the solder resist layer by using a printing method. Therefore, the present invention can directly form a dielectric layer on the line without heating the resin layer and the laser removing process.

上。相較於f知麟言’本發明崎低製造成本以及縮 為讓本發明之特徵和優點能更明顯易懂,下文特舉較 佳實施例,並配合所附圖式,作詳細說明如下。 【實施方式】 【第一實施例】 圖2疋本發明第一實施例之線路板上的線路結構之剖 面不意圖。請參閱圖2,本實施例之線路板上的線路結構 300能電性連接一線路板2〇〇,其中線路板2〇〇為已製造完 成的成品,而線路板2〇〇包括多個接墊21〇與一防焊層 220。 圖2所示的線路板200雖然包括二個接墊21〇,但是 在其他未有圖式揭露的實施例中,線路板2〇〇可以包括一 個接墊210或二個以上的接墊21〇。此外,圖2所示的防 焊層220之類型雖然為防焊層定義(s〇lder Mask Defme, SMD) ’但是在其他未繪示實施例中,防焊層22〇之類型 9 200938043 itwf.doc/non. The features and advantages of the present invention are more apparent and understood from the following description of the present invention. [Embodiment] [First Embodiment] Fig. 2 is a cross-sectional view showing a line structure of a circuit board according to a first embodiment of the present invention. Referring to FIG. 2, the circuit structure 300 on the circuit board of the embodiment can be electrically connected to a circuit board 2, wherein the circuit board 2 is a finished product, and the circuit board 2 includes multiple connections. The pad 21 is bonded to a solder resist layer 220. Although the circuit board 200 shown in FIG. 2 includes two pads 21, in other embodiments not shown in the drawings, the circuit board 2 can include a pad 210 or more than two pads 21〇. . In addition, the type of the solder resist layer 220 shown in FIG. 2 is a solder mask layer definition (SMD), but in other embodiments not shown, the solder resist layer 22 is of the type 9 200938043 itwf. Doc/n

Mask Define, 也可以是非防焊層定義(No〜s〇lder NSMD)。 線路板上的線路結構3〇〇包括—介電層⑽以及一導 電圖案層32G。介電層31G 置於防焊層22 且 層310具有多個暴露接㈣〇的開口 H2。雖然圖2所示^ 介電層31〇具有二個開口 Η2,但是根據線路板細所包括Mask Define, can also be a non-solderproof layer definition (No~s〇lder NSMD). The wiring structure 3 on the wiring board includes a dielectric layer (10) and a conductive pattern layer 32G. The dielectric layer 31G is placed on the solder resist layer 22 and the layer 310 has a plurality of openings H2 exposing the (four) turns. Although the dielectric layer 31〇 shown in FIG. 2 has two openings Η2, it is included according to the wiring board.

,接塾21〇之數量’介電層310亦可以具有一個開口 Η2 或是二個以上的開口 Η2。 此外,介電層310可由印刷一絕緣材料而形成,而該 絕緣材料包括熱固型油墨、樹脂、顯影型油墨、献固型絕 緣膜、感光型絕緣膜或高分子介電層,其中該^絕緣材 枓的方法可包括鋼板印刷、峨印刷或其他適當的印刷方 法。當然’介電層310的製作方法亦可以包括喷塗、顯影、 滾輪塗佈、無電驗、雜、驗、化學氣相沉積或物理 氣相沉積。 導電圖案層320配置於介電層310上,而且導電圖案 層320延伸至這些開口 Η2内’並且經由這些開口 連接 至這些接墊210。導電圖案層320的較佳厚度可以在1〇微 米至50微米之間,而導電圖案層32〇可由印刷—導電膠或 一導電膏而形成,而導電膠與導電膏的差異在於二者 諾數(Reynolds number)不同。 詳細而言,導電膠的雷諾數比導電膏大,即導電膠比 導電膏易於流動。上述的導電膠可以是銅膠、銀膠、碳膠 或是其他低電阻係數的金屬膠,而導電膏可以是铜客厌^ 200938043 ^twf.doc/n Ϊ電電阻係數的金屬膏。此外,導電膠與 奈米銀、導電高分子材料或是由化學合 成方去所成的非金屬㈣。印刷導電膠或導電膏的方法 可包括鋼板印刷、網板印刷或其他適當的印刷方法。’ 、從上述内容得知,導電圖案層320與介電層31〇皆可 以用印刷的方式㈣成。因此,相較於習知技術而 參考圖1E),導電圖案層32〇以及介電層31〇在結^上盘 圖1E所示的銅線路層13〇,以及樹脂層12〇有所不同。詳 細而言’一導電圖案層320在開口 m處的表面較為平坦(如 圖2所示)。其次,習知技術的開口 H1之侧壁(sidewall) 較為陡峨’介電層31〇的開口 H2之側壁反而較為平缓。 因此,介電層310的開口 H2具有較小的縱橫比,其值可 介於0.02至〇·1之間。 zThe number of the dielectric layers 310 may also have an opening Η2 or more than two openings Η2. In addition, the dielectric layer 310 may be formed by printing an insulating material including a thermosetting ink, a resin, a developing ink, a solid insulating film, a photosensitive insulating film or a polymer dielectric layer, wherein The method of insulating material 可 may include steel plate printing, enamel printing or other suitable printing methods. Of course, the method of fabricating the dielectric layer 310 may also include spraying, developing, roller coating, electroless inspection, miscellaneous inspection, chemical vapor deposition, or physical vapor deposition. The conductive pattern layer 320 is disposed on the dielectric layer 310, and the conductive pattern layer 320 extends into the openings ’2 and is connected to the pads 210 via the openings. The preferred thickness of the conductive pattern layer 320 may be between 1 μm and 50 μm, and the conductive pattern layer 32 may be formed by a printed-conductive paste or a conductive paste, and the difference between the conductive paste and the conductive paste is the difference between the two. (Reynolds number) is different. In detail, the Reynolds number of the conductive paste is larger than that of the conductive paste, that is, the conductive paste is easier to flow than the conductive paste. The conductive paste may be copper glue, silver glue, carbon glue or other low-resistance metal glue, and the conductive paste may be a metal paste with a resistivity of copper. In addition, the conductive paste is made of nano silver, a conductive polymer material or a non-metal formed by chemical synthesis (4). The method of printing a conductive paste or a conductive paste may include steel plate printing, screen printing, or other suitable printing method. From the above, it is known that the conductive pattern layer 320 and the dielectric layer 31 can be formed by printing (four). Therefore, referring to Fig. 1E), the conductive pattern layer 32 and the dielectric layer 31 are different in the copper wiring layer 13A shown in Fig. 1E, and the resin layer 12A. More specifically, the surface of a conductive pattern layer 320 at the opening m is relatively flat (as shown in Fig. 2). Secondly, the side wall of the opening H1 of the prior art is relatively steep. The side wall of the opening H2 of the dielectric layer 31 is relatively flat. Therefore, the opening H2 of the dielectric layer 310 has a small aspect ratio and may have a value between 0.02 and 〇·1. z

線路板上的線路結構300更可以包括一保護層33〇, 其中保濩層330配置於導電圖案層;320上,而保護層330 的厚度介於10微米至30微米之間·。保護層330可以完全 覆蓋導電圖案層320,以保護導電圖案層320,進而避免導 電圖案層320受到損傷。此外,保護層330的材質可以與 介電層310或防焊層220相同。 另外’在本實施例中,導電圖案層320可以作為一種 跳線(jumper),例如導電圖案層320可以連接至少一個 接墊210 ’或是連接其中一個接墊210與另一個接墊21(^ 再者’端視不同的電路設計之需求,導電圖案層320也可 以連接三個接墊210。當然,導電圖案層320更可以連接 11 200938043 ttwf.doc/n =J四個以上之接墊21〇 ’ 與導電圖案層320遠接而双a, 个曰LJ為 相掛•主連接發生短路。此外,線路板2〇〇的 300 分別配置二個線路板上的線路結構 將介紹線路板上的線路結構的構造,接下來 圖3Α至圖3D ’對線路板上的線路結構300之製造 方法進行詳細的說明。 衣以The wiring structure 300 on the circuit board may further include a protective layer 33, wherein the protective layer 330 is disposed on the conductive pattern layer 320, and the protective layer 330 has a thickness between 10 micrometers and 30 micrometers. The protective layer 330 may completely cover the conductive pattern layer 320 to protect the conductive pattern layer 320, thereby preventing the conductive pattern layer 320 from being damaged. In addition, the material of the protective layer 330 may be the same as that of the dielectric layer 310 or the solder resist layer 220. In addition, in this embodiment, the conductive pattern layer 320 can serve as a jumper. For example, the conductive pattern layer 320 can be connected to at least one pad 210 ′ or connect one of the pads 210 to another pad 21 (^ Furthermore, the conductive pattern layer 320 can also be connected to the three pads 210. Of course, the conductive pattern layer 320 can be connected to more than four pads 21 of 200938043 ttwf.doc/n=J. 〇' is remote from the conductive pattern layer 320 and double a, one 曰LJ is connected and the main connection is short-circuited. In addition, the wiring structure of the circuit board 2 配置 300 is configured on two circuit boards. The structure of the line structure, and then FIG. 3A to FIG. 3D', the manufacturing method of the line structure 300 on the circuit board will be described in detail.

制、土太、土 &圖2中線路板上的線路結構300之 ::線路二?〇:思圖、。請參閱圖3A,本實施例之線路板 線路板2(^,ϋ之製造方法包括下列步驟。首先,提供 —此驗’ /、中線路板細包括多個接整21G以及一暴 路追些接墊210的防焊層22〇。 u 閱® 3B ’接著,形成介電層310於防焊層22〇System, earth, soil & line structure 300 on the circuit board in Figure 2 :: Line 2: 思: thinking,. Referring to FIG. 3A, the circuit board circuit board 2 of the present embodiment (^, the manufacturing method of the cymbal includes the following steps. First, provide - this test ' /, the middle circuit board includes a plurality of 21G and a violent road to catch some The solder resist layer 22 of the pad 210. u Read® 3B 'Next, a dielectric layer 310 is formed on the solder resist layer 22〇

’ 了中介電層31G具有多個暴露這些接墊21()的開口 形成介電層31G的方法可以是印祕_油墨、樹脂、 馬为電層或其他絕緣材料於防焊層22〇上。當介電層 310疋由印刷熱固型油墨而形成時,形成介電層則的方 法更可以是烘烤魏緣㈣。如此,絕緣㈣得以固化而 形成介電層310。 =參閱圖3C ’接著,形成至少一導電圖案層32〇於 ”電層310上。在本實施例中,形成導電圖案層32〇的方 導電膠或導電膏於介電層310上。當導電圖 ^層320疋由印刷導電膠或導電膏而形成時,形成導電圖 案層32〇的方法可以是烘烤該導電膠或該導電膏。如此, 導電膠或導電膏得以固化而形成導電圖案層32〇。 12 200938043 4twf.doc/n 導電圖案層320除了可以由印刷導電膠或印刷導電膏 而形成之外,本實施例還具有其他形成導電圖案層320的 方法,例如喷塗法(spray coating )、滾輪塗佈法、無電電 鑛法、有電電鑛法、藏鍍法(sputter)、蒸鏡法、化學氣 相沉積(Chemical Vapor Deposition, CVD)或物理氣相沉 積(Physical Vapor Deposition,PVD )。 當導電圖案層320是由上述方法所形成時,包括以下 ^ 步驟。首先,形成一全面性覆蓋介電層310、防焊層220 以及這些接墊210的導電膜層。之後,再進行微影與蝕刻 製程’以移除部份導電膜層,進而形成導電圖案層32〇。 在導電圖案層320形成之後’基本上,一種線路板上的線 路結構300已製造完成。 請參閱圖3D,之後’可以形成一保護層330於介電 層310上,其中保護層330可以全面性覆蓋導電圖案層 320,而保護層330的形成方法與材質可以與介電層31〇 或防焊層220相同。 Φ 【第二實施例】 圖4疋本發明第二實施例之線路板上的線路結構之剖 面示意圖。請參閱圖4,本實施例之線路板上的線路結構 400適於電性連接一線路板200,,其中線路板2〇〇,包括至 少一接墊210’以及一防焊層220,,而線路板上的線路結構 400包括一介電層410、一導電圖案層42〇以及一保護層 430。須事先說明的是,雖然圖4僅繪示一個接墊21〇,: 但在本實施例中,線路板200,亦可以包括多個接墊 故圖4中的接㈣〇’之數量並雜定本^個接塾210 13 200938043 ltwf.doc/n 線路板上的線路結構400的形成方法、材質以及結構 皆與第-實施例相似,故不再重複介紹,惟線路板上 路^構400與第一實施例的差異之處在於保護層43〇局部 覆蓋導電圖案420。也就是說,保護層43〇局部暴露 圖案420。 詳細而言,導電圖案420被保護層430所暴露的部分 (圖4中虛線所圍繞的部分)可作為連接晶片、被動元件、 ❿ 主動元件或其他外部電子元件的接墊,也就是說,導電圖 案420能連接上述外部電子元件。 綜上所述,本發明之線路板上的線路結構,其介電層 疋藉由印刷絕緣材料於線路板的防焊層上而形成。因此, 本發明能在不經由加熱壓合樹脂層、雷射鐵孔製程以及去 膠/查製私的剷提下,直接形成介電層於線路板的防焊層 上。相較於習知技術而言,本發明的製造線路板上的線路 結構之方法能大幅降低製造成本以及有效縮短製造時間。 — 其次,藉由印刷導電膠或印刷導電膏,本發明能在介 電層上直接形成導電圖案層,無須經由微影與蚀刻製程。 因此,本發明的製造線路板上的線路結構之方法可不必採 用光阻與蝕刻藥液。這樣可以降低線路板上的線路結構在 製造過程所產生的污染物’以符合環保的需求。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習本發明所屬領域之具有通常知識 者’在不脫離本發明之精神和範圍内,當可作些許之更動 與潤飾’因此本發明之保護範圍當視後附之申請專利範圍 所界定者為準。 200938043 ttwf.doc/n 【圖式簡單說明】 示意至圖1E0知—種增層線路的製造方法的流程 圖2是本發明第一實施例之 面示意圖。 '、路板上的線路結構之剖 ❹ 圖3A至圖3D是圖2中線践^ 製造方法騎赫意圖。、板上的線路結構3〇〇之 =是本發明第二實施例之線路板上的線· 面系意圖 〖構之剖 【主要元件符號說明】 100、200、200’ :線路板 110 :線路基板 112、114、130’ :銅線路層 116、310、410 :介電層 120 ·樹脂層 ® 130:銅金屬層 140、220、220’ :防焊層 210、210’ :接墊 300、400 :線路板上的線路結構 320、420 :導電圖案層 ° 330、430 :保護層 B1 :導電盲孔結構 HI、H2 :開口 15The dielectric layer 31G has a plurality of openings exposing the pads 21 to form a dielectric layer 31G. The method may be a stamper ink, a resin, a horse electrical layer or other insulating material on the solder resist layer 22A. When the dielectric layer 310 is formed by printing a thermosetting ink, the method of forming the dielectric layer may be a baking edge (4). Thus, the insulation (4) is cured to form the dielectric layer 310. Referring to FIG. 3C', then at least one conductive pattern layer 32 is formed on the "electric layer 310. In this embodiment, a conductive paste or conductive paste of the conductive pattern layer 32" is formed on the dielectric layer 310. When conducting When the layer 320 is formed by printing a conductive paste or a conductive paste, the method of forming the conductive pattern layer 32 may be baking the conductive paste or the conductive paste. Thus, the conductive paste or the conductive paste is cured to form a conductive pattern layer. 32〇. 12 200938043 4twf.doc/n The conductive pattern layer 320 can be formed by printing a conductive paste or a printed conductive paste. This embodiment also has other methods of forming the conductive pattern layer 320, such as spray coating. ), roller coating method, electroless ore method, electro-pneumatic method, sputter, steam mirror, chemical vapor deposition (CVD) or physical vapor deposition (Physical Vapor Deposition, PVD) When the conductive pattern layer 320 is formed by the above method, the following steps are included. First, a comprehensive covering dielectric layer 310, a solder resist layer 220, and a conductive film layer of the pads 210 are formed. Then, a lithography and etching process is performed to remove a portion of the conductive film layer to form a conductive pattern layer 32. After the conductive pattern layer 320 is formed, 'substantially, a wiring structure 300 on a circuit board has been manufactured. Referring to FIG. 3D, a protective layer 330 may be formed on the dielectric layer 310, wherein the protective layer 330 may cover the conductive pattern layer 320 in a comprehensive manner, and the forming method and material of the protective layer 330 may be combined with the dielectric layer 31. The second embodiment is a cross-sectional view of the circuit structure on the circuit board of the second embodiment of the present invention. Referring to FIG. 4, the circuit structure 400 on the circuit board of the present embodiment is suitable. Electrically connected to a circuit board 200, wherein the circuit board 2 includes at least one pad 210' and a solder resist layer 220, and the circuit structure 400 on the circuit board includes a dielectric layer 410 and a conductive pattern layer. 42〇 and a protective layer 430. It should be noted that although FIG. 4 only shows one pad 21〇, in the embodiment, the circuit board 200 may also include a plurality of pads, so that in FIG. 4 Connect (four) 〇 'the number and miscellaneous this ^塾 210 13 200938043 ltwf.doc / n The formation method, material and structure of the circuit structure 400 on the circuit board are similar to the first embodiment, so the description will not be repeated, but the circuit board 400 and the first embodiment The difference is that the protective layer 43 〇 partially covers the conductive pattern 420. That is, the protective layer 43 〇 partially exposes the pattern 420. In detail, the conductive pattern 420 is surrounded by the portion exposed by the protective layer 430 (the dotted line in FIG. 4 The portion can be used as a pad for connecting the wafer, the passive component, the active component or other external electronic component, that is, the conductive pattern 420 can be connected to the external electronic component. In summary, the wiring structure of the circuit board of the present invention has a dielectric layer formed by printing an insulating material on the solder resist layer of the circuit board. Therefore, the present invention can directly form a dielectric layer on the solder resist layer of the wiring board without passing through the heat-pressing resin layer, the laser iron hole process, and the stripping/inspection. Compared with the prior art, the method of manufacturing a wiring structure on a circuit board of the present invention can greatly reduce the manufacturing cost and effectively shorten the manufacturing time. — Secondly, by printing a conductive paste or a printed conductive paste, the present invention can form a conductive pattern layer directly on the dielectric layer without passing through a lithography and etching process. Therefore, the method of manufacturing the wiring structure of the wiring board of the present invention does not require the use of photoresist and etching solution. This can reduce the contaminants produced by the wiring structure on the board during the manufacturing process to meet environmental requirements. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art to which the invention pertains will be able to make a few changes without departing from the spirit and scope of the invention. And the scope of the invention is therefore defined by the scope of the appended claims. 200938043 ttwf.doc/n [Simplified Schematic Description] Fig. 1E0 shows a flow of a method for manufacturing a build-up line. Fig. 2 is a schematic view showing a first embodiment of the present invention. ', section of the circuit structure on the road board ❹ Figure 3A to Figure 3D is the schematic of the manufacturing method of the line in Figure 2. The circuit structure on the board is the line/face system on the circuit board according to the second embodiment of the present invention. [The main component symbol description] 100, 200, 200': circuit board 110: line Substrate 112, 114, 130': copper wiring layer 116, 310, 410: dielectric layer 120 · resin layer ® 130: copper metal layer 140, 220, 220': solder resist layer 210, 210': pads 300, 400 : Line structure 320, 420 on the circuit board: conductive pattern layer ° 330, 430: protective layer B1: conductive blind hole structure HI, H2: opening 15

Claims (1)

twf.doc/n 200938043 十、申請專利範固: ^ -種製造線路板上的線路結構之方法,包括: 線路板,其中該線路板包括—防焊 接塾’該防焊層暴露該接墊; 至少焊層上’其中該介電層具有 ^ 暴露該接墊的開口;以及 介電案層’其中該導電圖案層配置於該 層層延伸至該開口内’且該導電圖案 由該開口連接至該接墊。 跟社接*申叫專利範圍第1項所述之製造線路板上的線 該防焊::法’其中形成該介電層包括印刷-絕緣材料於 路社申⑽利範圍第2項所述之製造線路板上的線 緣方法,其巾形成齡電層的方法更包括烘烤該絕 路妹i㈤申料利範圍第2項所述之製造線路板上的線 之方法,其中該絕緣材料包括熱固贺油墨、樹脂、 芦墨、熱目型絕緣膜、感光型絕緣嫉或高分子介電 5.如申請專利範圍第i項所述之製造線路板上的線 、、、。構之方法,其中形成該導電圖案 法包括印 導電膠或一導電膏於該介電層上。 社6·如申請專利範圍第5項所述之製造線路板上的線 、、吉構之方法,其中形成該導電圖案層的方法更包括烘烤 16 ^twf.d〇c/n 200938043 該導電膠或該導電膏。 紗L ΐ申請專魏圍第5摘述之製造線路板上的線 其中該導電膠包括鋼膠、銀膠、碳膠、奈 i ii南分子材料’而該導電膏包括銅膏、銀膏、碳 月、不米銀或導電高分子材料。 ❹ m 路於L t巾請專郷圍第1摘述之驗線路板上的線 ,,、吞认法,其中形成該導電圖案層的方法包括喷塗 ί法無電電鍍法、有電電錄法、濺鑛法:蒸 化予乳相沉積或物理氣相沉積。 路結二之::請=範圍第1項所述之製造線路板上的線 声遠;1 ,,、中該接墊的數量為多個,而該導電圖案 層運接至少—個接墊。 絲it如+請專纖圍第1賴叙製造祕板上的線 ’更包括形成—倾層於該介制上,其中 这保=層配置於該導電圖案層上。 線路結 1構如申請專魏圍第1G項所述之製造線路板上的 &之方法’其中該保護層完全覆蓋該導電圖案層。 線路結構如申請專娜圍第10柄述之製造線路板上的 之方法’其中該保護層局部暴露該導電圖案層。 路結構之如申請專利範圍第1項所述之製造線路板上的線 同。 方法’其中該介電層的材質與該防焊層的材質相 路結構·如申請專利範圍第1項所述之製造線路板上的線 °之方法’其中該介電層的材質與該防焊層的材質不 17 kwf.doc/n 200938043 相同。 I5. -種線路板上的線路結 板’該線路板包括至少-接Μ 生連接一線路 該線路板上的線路結構包ί塾與—暴露該接墊的防谭層, 一介電層,配置於該防焊層 暴露該接墊的開口;以及 %丨電層具有至少- ❹ 一導電圖案層’配置於該介電層上,並延伸至 内’而導電圖案層經由該開口連接至該接墊。”汗口 社槿16ιΓ請專利細第15項所述之線路板上的線路 、、,。構’其中該開口的縱橫比介於0 02至01之間。路 結構利範圍第15項所述之線路板上的線路 /、 5λ;ι電層的厚度介於10微米至30微米 结構專利範圍第15項所述之線路板上的L 八中該Μ電層是由印刷一絕緣材料而形成。 -構'It!,專利範圍第18項所述之線路板上的線路 敍;緣材料包括熱固型油墨、樹脂、顯影型喃 ‘型絕緣膜、感光型絕緣膜或高分子介電層。< 結二範圍第15項所述之線路板上的綠路 形成/、 圖案層是由印刷—導電膠或—導電膏而 結構二 ==膠2°=述:r的線路 電高分子材料。 銅膠、銀膠、碳膠、奈米銀或導 22 •申請專利範圍第20項所述之線路板上的線略 18 4twf.doc/n 200938043 、口構/、中該導電膏包括銅膏、銀膏、碳膏、奈米銀或裝 電高分子材料。 ^ 23·如申請專利範圍第15項所述之線路板上的線路 =構,其中該導電圖案層的厚度介於1〇微米至5〇微米之 24·如申請專利範圍第ls項所述之線路板上的線路 '° ,其中該介電層的材質與該防焊層的材質相同。 Ο ❹ 25·如申請專職㈣15項所狀線路板上的線路 、'σ '、中該介電層的材質與該防焊層的材質不相同。 姓播I如中請專利範圍第15項所述之線路板上的線路 個::該接墊的數量為多個,而該導電圖案層連接至 妹播2\如巾請專利範圍第15項所述之線路板上的線路 ^上1更包括—保護層,其中該保護層配置於該導電圖案 社播2,8甘^請專利範圍第27項所述之線路板上的線路 ’、該保濩層完全覆蓋該導電圖案層。 於槿巾請專利範㈣27項所述之線路板上的線路 ° '、中該保護層局部暴露該導電圖案層。 19Twf.doc/n 200938043 X. Application for patents: ^ - A method of manufacturing a circuit structure on a circuit board, comprising: a circuit board, wherein the circuit board includes - an anti-welding layer - the solder resist layer exposes the pad; At least on the solder layer 'where the dielectric layer has an opening exposing the pad; and a dielectric layer 'where the conductive pattern layer is disposed in the layer extending into the opening' and the conductive pattern is connected to the opening The pad. The contact with the community is called the wire on the manufacturing circuit board described in the first paragraph of the patent scope. The soldering prevention method: the method of forming the dielectric layer including the printing-insulating material is described in the second item of the road social application (10). The method for manufacturing the wire edge on the circuit board, the method for forming the ageing layer of the towel further comprises the method of baking the wire on the manufacturing circuit board according to item 2 of the claim 5, wherein the insulating material comprises A thermosetting ink, a resin, a reed ink, a thermal-mesh insulating film, a photosensitive insulating crucible or a polymer dielectric. 5. A wire, a wire on a manufacturing wiring board as described in claim i. The method of forming the conductive pattern comprises printing a conductive paste or a conductive paste on the dielectric layer. 6. The method of manufacturing a wire on a circuit board according to claim 5, wherein the method of forming the conductive pattern layer further comprises baking 16 ^ twf.d〇c/n 200938043 Glue or the conductive paste. Yarn L ΐ Apply for the line on the manufacturing circuit board of the Wei Wei 5th section, wherein the conductive adhesive includes steel glue, silver glue, carbon glue, nai ii south molecular material' and the conductive paste includes copper paste, silver paste, Carbon moon, not silver or conductive polymer materials. ❹ m Road in L t towel, please refer to the line on the circuit board of the first review, the method of swallowing, wherein the method of forming the conductive pattern layer includes spraying, electroless plating, and electro-acoustic recording. Splashing method: steaming to emulsion phase deposition or physical vapor deposition. Road junction two:: Please = the line on the manufacturing circuit board mentioned in item 1 is far away; 1 , , , the number of the pads is multiple, and the conductive pattern layer is transported at least one pad . The silk it is like a + the special fiber around the first line of the manufacturing line on the secret board ‘and includes the formation-dip layer on the medium, wherein the layer is disposed on the conductive pattern layer. The circuit junction 1 is constructed as a method of applying & on the manufacturing circuit board described in Section 1G of the Wei Wei, wherein the protective layer completely covers the conductive pattern layer. The wiring structure is as applied to the method of manufacturing the wiring board described in the 10th handle of the stipulations, wherein the protective layer partially exposes the conductive pattern layer. The structure of the road is the same as that of the manufacturing circuit board described in the first application of the patent scope. The method of the material of the dielectric layer and the material of the solder resist layer, and the method for manufacturing the line on the circuit board according to the first aspect of the patent application, wherein the material of the dielectric layer and the prevention The material of the solder layer is not the same as 17 kwf.doc/n 200938043. I5. - A circuit board on a circuit board. The circuit board includes at least a connection to a circuit. The circuit structure on the circuit board includes an anti-tank layer, a dielectric layer, which exposes the pad. Disposed on the solder mask to expose the opening of the pad; and the % germanium layer has at least - a conductive pattern layer disposed on the dielectric layer and extending into the inner portion through which the conductive pattern layer is connected Pads. "Khankou Society 槿16 Γ Γ 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利The wiring on the circuit board /, 5λ; the thickness of the electrical layer is between 10 micrometers and 30 micrometers. The structural layer of the circuit described in the fifteenth item of the patent range is formed by printing an insulating material. - Structure 'It!, the line on the circuit board mentioned in the 18th patent; the edge material includes thermosetting ink, resin, developing type ' insulating film, photosensitive insulating film or polymer dielectric layer < The green path on the circuit board described in item 15 of the second paragraph is formed, and the pattern layer is printed-conductive rubber or conductive paste and the structure is two == glue 2 ° = said: r line electric polymer Materials: Copper, silver, carbon, nano silver or guide 22 • The line on the circuit board described in item 20 of the patent application is slightly 18 4twf.doc/n 200938043, the mouth structure /, the conductive paste includes Copper paste, silver paste, carbon paste, nano silver or charged polymer materials. ^ 23·If you apply for the scope of the 15th item The circuit on the circuit board is configured as follows: wherein the thickness of the conductive pattern layer is between 1 〇 micrometer and 5 〇 micrometers. 24 线路 线路 如 如 如 如 如 如 如 如 如 如 如 , , , , , , , The material of the electric layer is the same as that of the solder resist layer. Ο ❹ 25·If you apply for full-time (4) 15 lines, the line on the circuit board, 'σ', the material of the dielectric layer is different from the material of the solder resist layer. The last name I broadcasts the line on the circuit board as described in item 15 of the patent scope:: the number of the pads is plural, and the conductive pattern layer is connected to the sister broadcast 2\ The circuit 1 on the circuit board of the present invention further includes a protective layer, wherein the protective layer is disposed on the circuit board of the conductive pattern 2, 8 and the circuit board described in item 27 of the patent scope, The protective layer completely covers the conductive pattern layer. The circuit of the circuit board described in Item 27 of the patent specification (4) is used to partially expose the conductive pattern layer.
TW97106991A 2008-02-29 2008-02-29 Wire structure on circuit board and method for fab TWI357294B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI412308B (en) * 2009-11-06 2013-10-11 Via Tech Inc Circuit substrate and fabricating process thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI412308B (en) * 2009-11-06 2013-10-11 Via Tech Inc Circuit substrate and fabricating process thereof

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