TWI355090B - Semiconductor device and method of producing the s - Google Patents

Description

1355090 IX. Description of the invention: [Technical field to which the invention pertains] Method. The present invention is directed to a semiconductor device that operates at high speed and high power and its manufacture. [Prior Art] The prior art is a high-speed transistor that is used in micro-power and a large-scale electric power a-body used for power conversion, and is led by a silicon-electric product. , is applied in various fields. As a semiconductor element constituting a high-speed transistor and a large power transistor, a thyristor 'GTG, IGBT, MGSFET, or the like. These components must be used for high-speed power FF_, _ to the power; ^: for the purpose of speed, and the use of a semiconductor substrate formed on the plane. In the case of a semiconductor substrate in which the substrate phase is used to form such a device, a two-layer structure is used as shown in FIG. As a structure for manufacturing a component, agro-n-type semiconductor dream layer 13〇2 (or, on a layer of a high-altitude material having a semiconductor), a low-concentration semiconductor semiconductor layer is stacked on the ^ On the platter 'using ion implantation technology, hetero-f diffusion technology, and technology, to form three to four layers of impurity concentration or conductivity-conducting semi-conducting layer' to form a desired semiconductor element. In the semiconductor element thus formed, = current flows from the back side of the substrate to the surface side (or flows in the opposite direction), and the substrate is formed to have a thickness of 2 〇 to 1 mm thick. = The substrate in which the component is inserted in series has a large resistance. For this reason, the back surface grinding technique of the substrate having a high impurity concentration as a supporting substrate is finally used, and the substrate is ground to 2 〇 〜 2 〇〇 The thickness of the component substrate is reduced to reach a minus = string After the purpose of the coupling resistance, the metal electrode is placed on the back surface to complete the semiconductor element 1355090. After the back grinding, the thickness of the semiconductor secret is about 30. The re-live will cause problems such as mechanical strength reduction and component destruction. It is hoped that the problem of component destruction will not occur and that the semi-conducting is formed after the crayback process without using the above-mentioned back grinding method. The temperature around c is such that the crystal growth of the insect crystals is carried out and the thin layer is formed at a temperature of 8 (the temperature of the rc is connected to the metal substrate).

^ However, due to the use of coffee. The high temperature above c will produce the metal original = scattered ^I, = the H!iLroJ when the pre-layered layer of the upper layer is pre-layered: it is extremely difficult to control 'only one layer or two layers can be obtained: + conductor The layer, at the time, causes the problem that semiconductor fabrication cannot be simplified. In addition, regarding the semiconductor device used in the conventional semiconductor device, the interface of the shixi gate insulating film interface is known as a vertical semiconductor device, and it is extremely difficult to form the n-type and p-type bipolar elements. The semiconductor material to be formed into an inverter or the like is formed by mounting an individual semiconductor element on a wiring board. Back to the semiconductor component process, in order to form the semiconductor component, it is necessary to carry out the impurity implantation and expansion process, and most of these wealth must be processed in the vicinity of lOGGt, so the impurity distribution in the component The system is extremely difficult, and the yield will decrease, which will cause the price of components to rise. From the viewpoint of the manufacturing technique, since only the (100) plane can be used, the diffusion constant of electrons and holes is small, and the speed at which the current of the element is turned on or off cannot be improved. Moreover, since the element is formed on the substrate, the heat of the element is hard to dissipate to the outside of the element, and the temperature of the element rises, so that the problem arises: the electron and the hole 6 1355090 are extremely increased. Uncontrollable and complex temperature compensation circuits must be designed. Further, conventionally, it has been difficult to form a large number of vertical semiconductor elements on a single conductor substrate, and thus semiconductors formed using such semiconductor elements have been increased in size. In the case where the above-described semiconductor device cannot be densified and the size of the semiconductor device is increased, the problem of connecting the wiring of the adjacent semiconductor element to a long distance is caused. Therefore, the parasitic capacitance and inductance (Inductance) of the wiring are increased, and the speed cannot be increased. The problem of the semi- & body device®, [Description of the Invention] The invention of the invention is to solve the above problems, and it is possible to introduce a thin semiconductor layer which is not available in the prior art, and to reduce the series resistance of the substrate. The element operation speed g is high speed, and the substrate 'pre-controlled impurity concentration distribution before the element is manufactured can be easily obtained and the manufacturing cost of the semiconductor element is reduced. Further, an object of the present invention is to form an element capable of high-conduction or blocking of a current by using a (110) plane capable of obtaining a high electron diffusion constant and a hole diffusion constant. Here, the (110) plane orientation indicates a plane equivalent to the (110) plane in crystallography, that is, a planar square position such as a (010) plane or a (001) plane. Further, in the semiconductor device formed using the plurality of semiconductor elements, the semiconductor element is formed on a single semiconductor substrate, the wiring distance between the connection elements is reduced, and the parasitic capacitance and inductance of the wiring are reduced. The semiconductor device is driven at a high speed. In order to solve the problems according to the present invention, the present invention is a semiconductor substrate having a semiconductor layer formed on a substrate of a metal substrate, the metal substrate comprising: a metal substrate made of a first metal; and a diffusion preventing layer Preventing the metal constituting the metal substrate from diffusing into the semiconductor layer; the connecting metal layer is composed of a second gold rider for connecting the metal substrate to the 7 1355090 2 bulk layer, and the solution conductor is made of (i 〇) One of the plane orientation and the plane orientation equivalent to the orientation of the (Π〇) plane = and the semi-transistor semiconductor component of the semiconductor miscellaneous (four) conductivity age is characterized by: (110) plane orientation and The ceremonial crystals of the plane orientation equivalent to f are formed by combining bipolar electric MOSFETs and IGBTs individually or in a large number. Further, in the case of the vertical semiconductor element of the present day and the month, a plurality of the different vertical semiconductor elements are densely disposed on a single substrate at the element isolation region. The semiconductor element system is based on the fact that the axis is on the metal substrate, and the thickness of the semiconductor layer above is the following. Further, the method for forming the present substrate and the semiconductor material is a process of forming a porous donor on a type of semiconductor substrate, and forming a porous enamel on the porous substrate; The wafer layer of the wafer layer: g paste 2: the metal substrate and the semiconductor substrate having the cryptocene layer are separated from each other. Further, the semiconductor element and the semiconductor substrate of the present invention contain a 'different polarity. Most of the vertical semi-conducting separations; the paste-component electrical properties do not form the semiconductor layer on the metal substrate, because the layer ϊ == two causes problems, __ components ' and make the conventional The semiconductor m 8 1355090 is as small as 20//m or less, and the series resistance of the vertical semiconductor element can be reduced. 2 is a graph showing the substrate thickness versus the bipolar transistor occlusion frequency, showing that the layers of the collector, the substrate concentration, and the thickness of the collector are 'n type 1 x lO cm, 0.7 _; 0. 5//m; dependence on the substrate in contact with the collector layer when n-type lxl〇2Qcnf3 is set. In order to reduce the series resistance of the device, the resistance of the substrate must be as low as possible. The impurity concentration of the substrate must be such that the substrate resistivity is sufficiently low, about 1 ηηΩαη, at about i xltfoiT3 at t, or a higher concentration. The offset frequency starts to deteriorate from a thickness of the substrate exceeding 2 〇 ym, and the conventional substrate is thickened to a maximum of about half.

According to the present invention, it is possible to drive a workpiece at a high speed by guiding a substrate of 20 "m or less. The same effect can be obtained by using the p-type substrate of the opposite conductivity type even if the n-type substrate has an impurity concentration of about 1×10 2 Gcra-3 or higher. Further, according to the present invention, the semiconductor layer forming the semiconductor layer utilizes crystals having a plane orientation parallel to the surface of the substrate surface, whereby the diffusion of electrons or holes is often increased, and the conduction can be performed at a south speed. Or interrupt the current. Further, by providing an element isolation region penetrating through the semiconductor layer, a plurality of vertical semiconductor elements are formed on a single substrate, and wiring is formed on both surfaces of the semiconductor, thereby concentrating the semiconductor element, thereby utilizing the Since the formed semiconductor device is miniaturized, the parasitic capacitance and inductance of the tree and the wiring household can be reduced, and thus the problem of delay in operation of the element or generation of a surge voltage can be alleviated, and these problems have occurred in the past. Further, according to the semiconductor substrate of the present invention, since wiring can be formed on both surfaces of the vertical semiconductor layer, conventionally, the inverter of the vertical semiconductor element cannot be realized except for the method of mounting the individual element on the wiring board. ECL (emitter-coupled logic) is formed on a single-substrate, and can be easily realized, and various integrated circuits using a vertical semiconductor can be realized. * The (110) plane orientation referred to in the present invention is a general term for crystallographically equivalent to (110) plane, plane orientation, for example, (011) plane, (101) plane, and the like. Further, even if it is not completely complete with the (110) plane H, A can be related to the purpose of the present invention 9 1355090, for example, (511) plane, (311) plane, (221) plane, (231) plane, (351) face, (320) face, (2) heart 2: (110) face orientation may be similar.发明Inventive semiconductor substrate by using appropriate and semi-conducting materials, and forming a genus substrate on a metal substrate to improve the thermal conductivity of the substrate, thereby removing the elemental component of the genus, and the semiconductor substrate according to the present invention. As described above, since the % of the material is controlled, the distribution of the impurity concentration in the adjacent semiconductor phase can be made to minimize the size of the "body" layer in the polarity, and the substrate can be fabricated by a simple process. Extremely thin or short-length, high-performance components. The semi-conducting step-like impurity concentration distribution refers to the formation of low-temperature, sharp-transformed filaments that are adjacent to each other in the vicinity of μ6. A state in which the impurity diffusion is small and has a steep concentration distribution, which is a miscellaneous cloth which cannot be obtained by the m solid phase diffusion method or the ion implantation method. As, p, B, Sb, etc. of the impurities in the 2 ΐ ίίΓ, they are suspended in the boot The number is below 1G2°cm2/SA. In this environment, the square root of the time and the product of the expanded n is defined as the diffusion distance, and the spur distance is 1 hour for the diffusion of the product. Low temperature, miscellaneous The embodiment of the present invention will be described in detail with reference to the drawings. 1355090 (Embodiment 1) = The following is a semiconductor substrate of Example I of the present invention. The structure and the method of fabrication. The conductivity type described below refers to the n-type and the conductor in the semiconductor, and the difference in the conductivity type also includes the change in the concentration of the impurity f. @@3 is the cross-sectional structure of the crystal substrate. The epipolar crystal substrate is composed of the following: The Si layer 101 has a conductivity type for forming an emitter layer, and a conductive core layer 103' having a filament layer is used. a third conductivity type constituting the collector layer; a Si layer 1 〇 4, a fourth conductivity type of the contact region; and a metal substrate 1 曰〇 8 contacting the Si layer having the fourth conductivity type and forming a collector electrode; Bonding the semiconductor layer to the metal substrate. The metal substrate 108 illustrated by the germanium layer is composed of a metal (for example, ===/_娜细梅2 rhyme, for example, Ni) - a crystal substrate Since a conductive Si layer having a large amount is formed on the metal substrate in advance, and the fourth conductivity type is provided The series resistance of the t element can be easily formed into a high-speed operation element. In addition, there is a (11G) plane orientation (10) single crystal, which has a large diffusion constant and can be improved compared to the conventional (10) plane orientation substrate. The speed of the operation. In addition, the "high-temperature element can be easily produced by the growth of the low-temperature crystals below the c-layer, and the low-temperature crystal crystals below c". The bipolar transistor substrate can be described as shown in Fig. 4 The manufacturing method. Fig. 4 is a very good use of the substrate as an example of the bipolar electrode body according to the first embodiment, and ', the member does not make the k method, which is formed by subtracting the following. First, 'using anodizing In the method, on the Shishi substrate 201 having the (1)0) plane, the U porous layer 202, the porous layer 2Q2 is used as the substrate for the growth of the silk crystal, (® 4 (a)), 1200t ^ in the body environment The micropores used to seal the surface are processed. At the temperature of the shed t 1355090, the epitaxial growth of the n-type germanium 203 as the emitter layer was performed by a sputtering method. Then, using the same technique, the 基-type base layer 204, the η-type collector layer 2〇5, and the ni!j still concentration collector 206 are grown in accordance with the epitaxial growth (Fig. 4(b)). The thickness of each layer is set to 〇 (10) / zm, 0·5 ", 0· Um; the impurity concentrations are respectively set to lxl 〇 2 〇 cm - 3, 5 >< 1 〇 18 coffee _3, 2X1017cnT3, 1 Χ 102 ΰ αη_3. These values can be adjusted with the purpose of the component and the voltage. However, it is preferable that the high-concentration collector layer 2〇6 is sufficiently thin in terms of low resistance and is preferably 20/m or less. This is because, as shown in Fig. 2, the electric resistance of the collector electrode rises in the case of a high concentration collector layer having a thickness of 20/m or more, and the f-charging time of S1 becomes A. The collector charging time is defined by the product of the collector resistance and the collector capacitance of the collector electrode, and the blocking frequency indicating the operating speed is lowered. Next, as shown in Fig. 4(c), a metal substrate 208, which will be described later, which is a support substrate of the element, is bonded to the above-mentioned stone substrate. A film formed of Ni is bonded to the bonding interface of the metal substrate and the Shi Xiji product, and is formed and bonded by a deuteration reaction at a temperature of about 5 ° C or lower by an RTA method or the like. A shihua layer 207 in which a metal substrate and a semiconductor layer are bonded together. The above metal substrate is formed as follows. First, a Cu substrate as a substrate of a metal substrate is prepared. The thickness of the Cu substrate is 20 〇vm which does not cause a problem in mechanical strength. Then, on the surface of the Cu substrate, TaN is formed on the surface of the substrate by, for example, a usual sputtering method in order to prevent Cu from diffusing toward the layer. Ni is formed by electroplating on the entire surface of the Cu substrate on which the sputtering of the TaN film has been completed, and the adhesion may be in the range of 400 to 500. (The passivation of the surface of the metal substrate is performed at a low temperature of about right and left, and the substrate is bonded to the substrate by Si. The metal substrate is formed in this manner. The material of the substrate of the metal substrate is not limited to Cu, and is a substrate. The electric resistance can be more sufficiently reduced than the still-concentration collector layer, and the conductive metal or metal compound having a resistivity of about 1 VVcm or less can be used. The g-a diffusion preventing layer is not limited to TaN. In addition, TaSiN, TiN, TiSiN, etc. may be used to prevent the elements constituting the metal substrate from diffusing into the Si. Further, the Mi which connects the metal layers is used as a bonding material which is bonded by deuteration, and is used for 12 1355090, but It is not limited to Ni', and Ti, Co, and the like may be a material which can be bonded to Si by a ruthenium reaction at a temperature of about 5 〇 (r). Next, the porous dream layer 202 formed in advance is formed. At the interface of the .2〇 grown by the insect crystal, the separation is performed (Fig. 4 (d)) » 6 to form the semiconductor substrate according to the first embodiment, and the crystal is crystallized at a low temperature of 6 Å. Grow up, let the impurities become a matter of conventional knowledge The problem of scattering does not occur. Therefore, it is possible to precisely control the thickness of each layer and the degree of impurity. In addition, it is made up of continuous faces; the silk layer has a Wei layer, so it does not require the use of techniques, and can be formed extremely simply and with high quality as ^ A substrate for forming a substrate. Each method for producing a bipolar transistor using the above-described semiconductor substrate will be described. The money is used to view the above-mentioned process and the semi-conductor plate (Fig. 5, coated for masking the emitter) The photoresist of the region is 3〇7, and the anti-cracking agent is patterned, and the opening is provided on the emitter layer other than the portion serving as the emitter region (Fig. 5(b) > The ERA method or the like removes the emitter layer under the anti-plating opening portion. The substrate layer is ion-implanted in a state where the residual photoresist is not removed, and the metal and the layer formed on the base electrode are used. The base contact of the electrical contact is not implanted due to the presence of anti-_ in the emitter region. The human m τ acts as an ion species' and uses the ion implants used in semiconductor fabrication = dense 3' The pole is directly below the secret layer and is utilized at the temperature of the fiber in the nitrogen The problem of heat in the gas can be recrystallized. The taste of the raw material is diffused, f 'peeling the photoresist, and is used as the interlayer insulating film on the whole surface of the stage by the method of (10), for example, (10) 2311. The interlayer insulating film is not Two W and so on === The s lake used in the manufacturing of Zhao, the test, the poly-resistance, the coated ribs formed the photoresist, and the base and emitter contact 13 1355090 area was patterned and formed by RIE. Then, in order to prevent the occurrence of a spike in which A1 is infiltrated into Si as an electrode material, a film of A1 having an atomic composition of about 1% of Si is applied by sputtering, and patterning is used. The base electrode 309 and the emitter electrode 310 are formed (Fig. 5 (d)). For the above-mentioned electrodes, film formation of Co, Ni, or the like may be performed in advance by sputtering, and the RTA method and Self-Aligned Silicide using self-alignment deuteration may be used. = Salicide)' for low contact resistance.

Thus, a bipolar transistor was produced using the substrate shown in the first embodiment. By performing the ion implantation process once and performing the entire process at a low temperature of 600 ° C or lower without causing the problem of impurity diffusion, it is possible to easily manufacture the impurity concentration of each functional layer that has been correctly controlled. Semiconductor substrate and semiconductor element. Again. Since the base layer does not use an ion implantation method or an impurity diffusion method, and a low temperature epitaxial growth method of 6 Å or less is used, a thin base layer can be easily formed, and the cost can be easily reduced at a low cost. Manufacturing high performance semiconductor components. Further, since the (110) plane having a large diffusion constant is used as the crystal plane orientation, a semiconductor element which is faster than the conventional one can be manufactured. Since the high-concentration collector layer is thin and has a thickness of 2 V m and is sufficiently low-resistance, the element characteristics are not deteriorated by the substrate resistance as in the past. The blocking frequency indicating the idling property of the element is η6 GHz in the present embodiment with respect to the conventional 50 GHz substrate of the (1 〇〇) plane.

(Embodiment 2) A structure of a semiconductor substrate according to Embodiment 2 of the present invention will be described with reference to Fig. 6 . 6 is a substrate for a vertical MOSFET according to the second embodiment, and is configured to display a high-concentration drain layer of a third conductivity type on the metal substrate 4'1 by the same method as that of the first embodiment. 403. The main layer A of the second electrode-conducting electrode layer 4G4 having an impurity concentration different from the j-th conductivity type and the channel having the third-conducting MOSFET of the third conductivity type is formed on the ((10)) plane. _ Substrate d, ?T type, impurity concentration and thickness, high-concentration dislocation layer is set to n layer is set to p, 0. The present invention _ two-body 14 1355090 substrate is pre-formed on the metal substrate with a majority The Si layer 403 of the first conductivity type is formed of a conductive Si layer, and its impurity concentration is lxio2. Cm ―3 or more; thickness is 20 ym or less, and the series resistance of the formed element can be reduced, and a high-speed operation element can be easily formed. Further, the Si layer is a Si single crystal having a (11 Å) plane orientation, and the diffusion constant is large and the operation speed can be improved as compared with the case of the conventional (100) plane orientation substrate. In addition, since the Si layer is formed by 6 〇 (low-temperature epitaxial growth of Tc or less and the impurity concentration distribution is precisely controlled, a high-performance element can be easily manufactured. The use of such a vertical type will be described using FIG. Fig. 7 is a view showing a method of manufacturing a vertical NMOS MOSFET. The manufacturing method о uses the substrate for MOSFET according to the second embodiment, which will be described below. In order to form a source region, ion implantation is performed by forming As+ of ions of a conductivity type opposite to that of the body region, forming a source region 506 (FIG. 7(a)). Then, 'in order to form an interlayer insulating film, CVD. 5wm - deposited by CVD

Si〇2 507 (Fig. 7(b)). Thereby, the capacitance overlapping the gate electrode and the source region can be reduced. In order to form a gate electrode, a trench hole 508 is formed at a place where the gate electrode is formed (Fig. 7(c)). This is done as follows. A photoresist is applied to one surface of the substrate, the photoresist is patterned, and an opening is provided in the resist of the groove forming portion. The opening is disposed in the source region. Next, the trench holes are formed by the RIE method generally used. The bottom of the trench hole 508 is formed to reach the drain-region 504. In the present embodiment, the depth is set to 〇. 8 in m, the width is set to 〇. 3, and the length is set to 20//m. This value can be changed depending on the purpose of use of the component. Next, the gate oxide film is formed after the photoresist is removed. The gate oxide film was formed by electropolymerization oxidation at a temperature of 4 〇〇 C using a mixed gas of Kr and 〇2, and an oxide film having a film thickness of 5 nm was formed on the inner wall of the trench hole. Thereby, in the inner and the walls of the trench hole 5Q, a favorable oxide film which is uniform and withstand voltages of 1 OMV/αη or more can be formed (Fig. 7 (4)). 15, the gate electrode 510 is formed in the same manner as described above. 400 〇 Ca product, for example, i. i ^ polycrystalline Si as the ρ·electrode material, the _ lin method is in the atomic composition. The Ah of the left and right Si applies the photoresist to the entire surface of the substrate, and the gate pole portion is patterned. The gate is completed. In order to form an interlayer insulating film, the entire surface of the substrate is deposited by a CVD method at a temperature of 4 〇〇C. In order to form a source electrode coating contact, patterning of the source electrode 09 is performed. When the source portion 5()9 is patterned, a photoresist opening portion is formed so as to straddle both the source layer n+5G6 and the p-layer 5〇5 of the body. By using the above method, the source electrode can obtain the source. Both the potential and the body potential.

Si 〇 2 in the photoresist opening portion is etched by the RIE method to form a contact hole, and the bismuth method is formed by M, 5 〇 9 containing about 1% of Si in the atomic region (Fig. 7(e)). The vertical MOSFET using the substrate according to Embodiment 2 of the present invention is completed by the above process. It is not necessary to enter the cultivator to form the material as is conventional, and the quality concentration can be properly controlled. Furthermore, since the necessary energy layers of the constituent elements are fabricated into the substrate, the component manufacturing process can be simplified. Furthermore, since the agricultural collector layer is formed thin to 〇. 2/zm ' and sufficiently low-resistance, the series resistance of this element is low, and the resulting vertical M〇SFET does not It is known that the speed performance of the element is deteriorated due to the substrate resistance.

Further, even in the case of, for example, a high-concentration collector region, the same effect can be obtained by alternately arranging the 汲-bend short-circuit type elements. On the other hand, a vertical p-channel MOSFET in which the conductivity type of each layer is set to the opposite conductivity type can also be fabricated by the same process. An example of this is shown below. An embodiment in which the present invention is applied to a trench-type vertical p-channel power M 〇 (p-channel power MOS) transistor will be described again using FIG. In this case, a substrate for a p-channel M〇SFET having the structure shown in Fig. 6 can also be used. (Fig. 7 (a)) shows a structure in which a high-concentration drain layer 5〇3 exhibiting a first conductivity type and impurity concentration are formed on a germanium substrate (not shown) having a (?1) plane. The body layer 505 of the layer 503 is different and has the same conductivity type as the layer 5〇3, and the body layer 505 having the second conductivity type opposite to the 1355090 first conductivity type and forming a channel of the p-channel M〇SFET. And come to get it. Regarding the conductivity type, impurity concentration and thickness of each layer, high concentration, the drain layer is p-type lxl〇2°cm-3, 〇·; the drain layer is p-type 2xi〇17cm, O.jym; It is η type 5xl〇18cm-3, 〇·. In the embodiment, the impurity concentration 503 has an impurity concentration of about ixi 〇 2Dcm-3 or more; the thickness is 2 Å. Hereinafter, the series resistance of the formed element can be reduced, and a high-speed operation element can be easily formed. Further, the layer 503 is a Si single crystal having a (110) plane orientation, which is superior to the case of using a conventional (100) plane orientation substrate, and has a large diffusion constant and can increase the operation speed. Further, since the Si layer is formed by low-temperature epitaxy growth of about 600 t or less, and the impurity concentration distribution is precisely controlled, it is possible to easily manufacture a device having a performance. Specifically, according to the embodiment, the vertical channel structure ρ-channel M〇SFET is formed using the substrate shown in FIG. 6, and as shown in FIG. 7(a), ion implantation is used to form the source region. In the method of implantation, in order to form a conductivity type opposite to that of the body region 5〇5, the source region 506 is formed by the introduced BF/'. The impurity concentration is p type 2 xi 〇 ncm ' Next, in order to form an interlayer insulating film, 〇 5 is deposited by CVD with & 2 507 (Fig. 7(b)). Thereby, the capacitance of the gate electrode overlapping the source region can be reduced. Next, as shown in Fig. 7(c), in order to form a gate electrode, a trench hole 508 is formed at a position where the gate electrode is formed. This is done as follows. A photoresist is applied to the entire surface of the substrate, the photoresist is patterned, and an opening is provided in the trench to form a portion of the resist. The opening is disposed in the source region. Next, the trench holes are formed by the RIE method generally used. The bottom portion of the trench hole 508 is formed to reach the drain region 504. In the present embodiment, the depth is set to 〇·8, the width is set to 〇.3βπι, and the length is set to 20. This value can be changed depending on the purpose of use of the component. Since the surface of the crucible 505 is the (110) plane, the inner side wall surface of the trench hole 5〇8 of the ring 也 505 is also formed into a (110) plane. Next, as shown in FIG. 7(d), the gate oxide film 511 is formed after the photoresist is removed. The formation of the gate oxide film is performed by plasma oxidation using a mixed gas of Kr and 〇2 at a temperature of 4 〇〇π, and an oxide film having a film thickness of 20 nm is formed on the inner wall of the groove, whereby the channel is at 17 1355090 The inner wall of the (110) plane of the trench hole 508 can form a good oxide film 511 of uniform and pass/cm. The withstand voltage between the gate and the source having the gate oxide film 5 ^ transistor is 1 〇 v. P encounters MUb and then forms a gate electrode _ as shown in Fig. 7 (4). After 4 (TC deposition of, for example, 0.1 μ polycrystalline Si柞A: υνυ/ίΓ for ice (4)/shr w as the gate electrode material, use minus The film is formed into a film containing about 1% of Si in the atomic composition, and the surface of the gate (four) is patterned, and the gate electrode is completed. The soil plate is finished, as shown in Fig. 7 (e) In order to form the interlayer insulating film 512, the source electrode 509 is formed by CVD at 40 (the temperature of TC is formed on the entire surface of the substrate). The source electrode is formed by first applying a photoresist and performing source. The electrode portion 5〇9 is used for the opening of the port. When the source electrode is opened, the wire opening portion is formed so as to straddle the source layer P+ 506 and the 11 layers 5〇5 of the body. The source electrode and the body potential can be obtained by the source electrode 5〇9. In order to form the opening, the film 5〇7, 512 of the photoresist opening portion is side-by-side by the RIE method to form a navigation method. Lai Yuxuan consists of A1 containing about 5% of Si, and is etched to form the source electrode 5〇9 by etching technique. The trench structure of the present embodiment is a vertical p-channel power MOS electric field effect transistor. Since the high-concentration collector layer 503 is formed thin to 〇.2_ and sufficiently low-resistance, the series connection of components The electric resistance is low, and a high-speed transistor can be obtained. • Further, even in the high-concentration collector region, the same effect can be obtained by alternately disposing the n + and p + 矽 汲 短路 short-circuit type elements. (Example 3) The structure of the semiconductor substrate according to the third embodiment of the present invention will be described with reference to Fig. 8. Fig. 8 is a substrate for a vertical IGBT according to the third embodiment, and is configured to be used on the metal substrate 6〇1 as shown in the first embodiment. In the same method, the anode layer 603 having the first conductivity type, the buffer layer 604 having the second conductivity type opposite to the first conductivity type, and the conductivity modulation layer 6 are formed on the tantalum substrate having the U1 surface. 〇5, and a third conductivity type gate layer 606 having the same polarity as the anode layer. In this embodiment, regarding the conductivity of each layer, the impurity concentration and the thickness, the anode layer is set to p-type lxl02°cnr? 〇. 2//m; buffer layer is set to η-type lxl02°cnT3 0.2#m; conductivity modulation layer η type 2xl〇17cnT3, 〇.2 "m; gate layer is set to p type 5xlOI8cnT3, 0. 2/zm, but these can be used according to the purpose of the component, withstand voltage However, it is preferable that the anode layer 603 is sufficiently thin for the purpose of lowering the resistance, and it is preferable that it is 2 〇em or less. The IGBT substrate of the third embodiment of the present invention is made of metal. The Si layer having a plurality of conductivity types is formed in advance on the substrate, and the Si layer 6〇3 having the first conductivity type has an impurity gradient of lx10. It is about cm-3 or more; the thickness is 20/zm or less, and the series resistance of the formed element can be reduced, and a high-speed operation element can be easily formed. Further, the Si layer is a Si single crystal having a (11 Å) plane orientation, and the diffusion constant is large as compared with the case of using a conventional (100) plane orientation substrate, and the operation speed can be improved. In addition, since the Si layer is formed by low-temperature epitaxial growth of about 60 TC or less, and the impurity concentration distribution is precisely controlled, a high-performance element can be easily manufactured. The use of such an igBT will be described with reference to FIG. Fig. 9 is a view showing a method of forming an n-channel gate type IGBT element on the above-described semiconductor substrate, which is formed as follows. First, by ion implantation, the implantation system is As is formed to form ions opposite to the gate layer, forming a cathode region 7〇7 (Fig. 9(a)). Then, SiO 2 is used to deposit 0·5"m of Si〇2 708 (Fig. 9 (b) Therefore, the capacitance overlapping the gate electrode and the source region can be reduced. Next, the trench hole 7〇9 is formed in the place where the gate electrode is formed. The photoresist is applied to the entire surface of the substrate to be patterned. The opening of the groove forming portion is provided with an opening portion. The RIE method is generally used to form a trench hole. The depth of the trench hole is adjusted to 7G5 in conductivity, and the depth is set to G. ί 0·3 ^, the length is set to 2〇' (Fig. 5 (c)). This value is It can be changed according to the purpose of use of the component. In the station field, after the photoresist is removed, the formation of the anaerobic tilt gate oxide film is formed, and the plasma of the electrocardiogram excited by the mixed gas of the core is 1,02, at 4〇〇. The temperature of t>c is oxidized by the lamp plasma, and an oxide film having a film thickness of 5 nm is formed. Thus, in the trench 1355090: forming a uniform and durable voltage with a voltage of more than /cm or more, the above-mentioned gate electrode is formed. 71 〇. The CVD method is used to deposit, for example, _, ^ right in the 4 〇〇〇c as the _ electric hoof bottle, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Parallel to the patterning of the gate portion, the gate electrode 710 is completed. In order to form the interlayer insulating film, the CVD method is applied to the entire surface of the substrate in order to form a cathode electrode, and the photoresist is coated and diffracted. In the case of rr 711, the photoresist opening portion is formed, and the original pole η | is the same as the p-genus of the body. The contact hole is formed by the above method, and the 组成1 of the atomic composition of Si is formed in the atomic composition of the country. Source electrode 711 (Fig. 9(e)). The vertical shape of the substrate according to Embodiment 3 of the present invention does not need to be known as & The ion implants used to form the well, and the JL can be controlled by the impurity. Since the structure is first, the device must be in the middle, and the component manufacturing process can be simplified. Moreover, since the extremely short = element: the effect is configured... The nano-conductor type can also be set to the opposite conductivity type p-channel, (Example 4) The semiconductor device of the present embodiment is based on the present embodiment. Complementary (_plementary) is a complementary inverter device using a bipolar transistor. == Inter-use::;=r device. The complementary type of Figure ι〇(4) is reversed. Each of the 20 semi-conductor elements placed in the opposite direction of the matte surface constitutes a structure in which the conductive type is reversed, and the piece 'is thus constituted the structure of the element wire (4) through the base (4), and in the technique of knowing A large number of elements having different polarities cannot be formed on the relevant semiconductor substrate. Therefore, since the element made of the different semiconductor substrate is mounted as a side element, it is not possible to increase the size of the element, and the wiring between the connection elements is long-distance. Since the inductance cannot be reduced, there is a problem that a surge voltage or the like occurs due to the inductance component. Further, as is conventionally, a ρηρ-type bipolar transistor formed in a (100) plane orientation is due to its electrons and electricity. The diffusion constant is small, the operation speed is delayed, and it is difficult to realize the complementary element as shown in FIG. According to the semiconductor device of the fourth embodiment, the semiconductor element is formed on the semiconductor substrate by forming a semiconductor element in a single semiconductor, and the semiconductor element wiring is formed on the semiconductor substrate, and the movable conductor element conductor is used as an integrated circuit. Since the layer has a (110) plane orientation, the diffusion constant of electrons and holes is large, and even if a JM1P type bipolar transistor is used, it has the same performance as an n-type bipolar transistor, and thus can constitute a complementary structure. Since a plurality of elements that can be reversed in polarity are mixed on a single semiconductor substrate, the semiconductor device such as an inverter and the wiring between the short-distance elements can be patterned. Therefore, the parasitic capacitance and parasitic inductance of the wiring can be reduced. It is possible to reduce the occurrence of the operation delay and the occurrence of the surge voltage, thereby providing a semiconductor device with high-cost operation at a low cost. Next, a method of forming the semiconductor device according to the fourth embodiment will be described with reference to Fig. 11 . Fig. 11 is a view showing a complementary inverter device formed by using a 叩n-type and a type of bipolar transistor in the semiconductor device according to the fourth embodiment. The symbols in the figure correspond to Figs. 12 and 13 to form an ηρη-type bipolar transistor and a ρηρ-type bipolar transistor 1022 on the metal substrate 1015, and separate the elements in the element isolation region 1〇23. The collector electrodes of the two are electrically connected to the metal substrate, thereby realizing the circuit structure shown by the circle 1 (a). Since it is possible to form a structure in which a plurality of elements having different polarities are mixed on a single substrate, in the past, only a vertical type semiconductor element in which individual elements are mounted can be realized. 21 1355090 Its densification can now be performed by using the semiconductor substrate according to the present embodiment. achieve. Since the collector electrode is not connected to the external wiring as is conventionally known, the parasitic capacitance and the parasitic inductance can be reduced, and the conventional problem, that is, the operation delay-, the problem of the dog wave voltage, can be solved, thereby providing high speed. The patent of the operation will be described with reference to Fig. 12 and Fig. 13 for a semi-conducting (fourth) manufacturing method in which a plurality of elements having such different polarities are formed on a single-substrate. The diagram will use the bipolar electro-crystal system to reverse the reversal as an example, and outline the method of its fabrication. First, as shown in FIG. 12(a), anodizing, on the surface of the substrate, the paste is a matrix of the growth of the crystal, and the porous layer 1002 is cut away from the substrate after bonding. . The micropores of the surface are sealed by treating them in an atmosphere. Next, the surface of the 质 ^ 夕 ' ' 蠢 蠢 蠢 蠢 蠢 蠢 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 At the time of the buffer layer, the buffer layer 1〇〇3 is obtained. As shown in Fig. 3, for example, you can use the splatter method to form, for example, you as the Shishi layer 1_, which is used to shape the shape. 7, m ri ri, the temperature of the method, and form the (4) layer 5: _ light Engraving the pattern and the office, and biased. L 赖 留 p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p a film of n+Si and P+Si ° ^ is formed, and the film is grown as an emitter electrode of the second element ^ 1007 (® 12 (c)) 〇1, an oxide film. As amorphous or polycrystalline 22 1355090, n + Si 10 which is grown on the oxide film is removed (r^ is removed, for example, a mixed solution of iodic acid, hydrofluoric acid, or acetic acid which generates less heat is used. The non-single crystal n+Si blue grown in the oxide film is faster than the crystal growth of the single crystal, and the engraving speed is fast and has a sufficient selection ratio, so that the film of the single crystal n+si may not be made. Thickness change and only non-single-crystal n+Si cis is removed. Next, the hydrofluoric acid is dissolved in the P+Si table to form _, which is completed as shown in Fig. 12 (4), and then formed by, for example, sputtering. The layer of the second type of the second element is shown as a layer 1GQ8 showing the third conductivity type, and the layer is the base electrode of the second element. In this embodiment, the structure is provided. difficult P-type Si. Next, on the surface of the p-type Si layer 1〇〇8, Si〇21〇〇5 is formed by a CVD method at a temperature of 4 Å. Patterning is performed by photolithography. In the saioos and the p-type Si layer 1_, for example, an RIE method is used, except for an oxide film and a p-type & (Fig. /, followed by sputtering method, except for the portion where the second element is formed, A layer having a display and the j-th element=reverse conductivity type is formed as a layer for forming a base electrode pattern of the i-th element. In the present embodiment, n-type & (10) (iv) thickness is formed. ^Type Si' grows on the pSi film 1GG4, and grows as a wormhole surface: on the oxide film 1GG5 of the p-type, & 88)_^, as an amorphous yarn or a polycrystalline coffee (Fig. In addition, the p-type Si which is grown on the oxide film is removed, for example, the heat-generating machinery, hydrogen, and the age of the acetic acid are grown, and the single-crystal P-type Si layer is used, and she is (4) single mg 1009, the side thereof. The speed is fast and has a sufficient selection ratio, and the film thickness of the 曰-type Si layer is changed, and only the non-single-crystal p-type Si layer P^SiM 1008 sw2 : is removed, and the semiconductor layers are adjacent to each other. The electric type is formed by repeatedly using the above method to form a residual semiconductor layer, and the high-intensity set 23 1355090 '*1 is 〇.5 (10), and the magnetic pole collector layer is divided into 0.2 a (1), so that the Shishi substrate and the The metal substrate 1015 is attached with a shovel; for example, to diffuse the surface of the Cu substrate, for example, a Ni layer is formed by electroplating on the entire surface of the substrate, for example. 2. The metal substrate is bonded to a temperature of 5 利用 using rta* or the like. The lower 3 reacts with the Si _ to form the _ brain, and the material of the base of the iiif ΐf ΐ 不 is not limited to Cu, as long as the substrate resistance is smaller than the ί, as long as it has a core of Au, Ag, etc. The resistivity of the right and left can be made of an electrical metal or a metal compound.

Further, the diffusion preventing layer is not limited to TaN, and any of TaSiN, TiN, and TiSiN may be used to prevent the elements constituting the metal substrate from diffusing toward the Si towel. The bonding material to be bonded is not limited to Ni, and may be a material having a low temperature of about Ti, Co ^ , or -00 C or less, and may be bonded to the substrate by Si-deuteration. At the interface between the porous stone portion 1〇〇2 and the buffer layer 1〇〇3, the patch substrate was cut and the buffer layer was removed by RIE, whereby the structure shown in Fig. 12(J) was obtained. ΐ 'In order to separate the elements of the first element and the second element, a photoresist is applied on the surface opposite to the base = metal substrate, and a photolithography method is applied to the boundary between the # element and the second 7L element of the photoresist. The opening 1〇17 is provided (Fig. 13(4)). The drain hole is formed in the opening by the method of (4). The bottom surface of the trench hole is bonded to the metal substrate by flattening from the surface of the semiconductor to the surface. He, f·surface', forms the structure shown in Fig. 13 (8). The photoresist is removed, and then the interface characteristics I of the crucible region and the material ride are good, and the Kr and 〇2 are used by the *: The inner wall of the groove hole is formed at about 10 nm (10) "Fig. 13 (〇). The oxide film may be insulative, for example, using NHa plasma to form 24 1355090 ί. After that, the CVD method is at 4G (the temperature of rc, and the Si 〇 21018 ΐ ί ί (Fig. 13 (4)). The Si 〇 2 formed by the CVD method may be formed by ίίϋ: τ, for example, by forming 3 and SiH4 (10). The ^L IE method removes Si〇2 on the surface of the substrate to obtain the structure shown in Fig. 13(e), thereby ending the separation of the elements of the first element and the second element. According to the method described above, the base electrode electrode 1020 is formed, and the inverter device shown in Fig. 13 (1) is completed. The collector _ pole of the first element second τ 件 is connected to the metal substrate 1 〇 15 and is not wired.

The complementary inverter device formed by the bipolar transistor thus obtained is obtained by using the semiconductor elements constituting the inverter device on the single semiconductor substrate of f to obtain the thin line formed by the word conductor. The conductor substrate is provided with an integrated circuit for operation. Since the semiconductor layer forming the semiconductor element has a 110 of (110) plane orientation, the diffusion constant of electrons and holes is large, and even if the fnp type bipolar transistor is used, it has the same performance as the npn type bipolar transistor. It is sufficient to form a complementary structure, and the elements of the polarity can be mixed with the majority of the semiconductor substrate. Therefore, the inverter can be shortened and the wiring between the components can be shortened. Therefore, the line can be reduced by (four) lines. With parasitic capacitance, parasitic inductance,

However, the reduction of the action depends on the spurt of the electric power, and the _ provides a low-cost semiconductor device with a low speed. According to the method of the present embodiment, it is possible to form an integrated circuit in which the collector electrodes are common, and a semiconductor device such as an inverter composed of a vertical semiconductor element formed by combining individual elements in the prior art is densely packed with good efficiency. The formation is performed on a single substrate, and the operation speed can be improved and the power consumption can be reduced. Since Wang Hao's process is carried out at a low temperature of 5 〇〇c or less, there is no problem of impurity diffusion between semiconductors of different conductivity types, so that it is possible to easily control impurities which are important in the characteristics of the element. The distribution of concentrations. In the present embodiment, although an example of a bipolar transistor has been shown, if the method shown in this embodiment is used, even if a vertical MOSFET or IGBT is used as the vertical half 25 if, the second is wrong. Further, it is also possible to form the integrated circuit structure in which the same i-piece is densely formed on the t-handle t to form the lateral semiconductor element and the vertical semiconductor on the substrate. Miscellaneous i knee ϊ ίί ί Before the board is fitted, 'pre-wiring the shape ^* on the collector side, the basin Ϊ Ϊ if if the ί plate is a power supply substrate, and can be used as an ECL (emitter face. read). _ A variety of integrated circuits are implemented. (Embodiment 5) A seatway!! In the fifth embodiment, a method of forming a vertical type of wiring circuit in which a wiring layer is formed on both surfaces of a semiconductor layer is used, and as shown in Fig. 14, the metal substrate side of the semiconductor layer is used. A method of forming a wiring layer. _ First 'in the method shown in Example 4, the majority of the vertical semiconductor ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ For example, Si〇2^06' is formed as an insulating film for the interlayer insulating film, and as shown in Fig. 14(a), a layer-by-layer material is present on the surface of the semiconductor layer. The semiconductor layer 1 ΐ ρ4 ' of ® Ma) shows a case where a large number of bipolar electro-crystals are formed on a single substrate, but as in the case of obtaining a vertical M 〇 SFET or an IGBT, even if there is no flaw, The layer structure of the display is not changed, and the essence of the embodiment is not changed. Next, in order to extract the lead wiring of the collector electrode, as shown in Fig. 14 (8), an opening is provided in the collector portion of the bipolar transistor of the interlayer insulating film 11?6 by a usual photolithography method. At this time, L is bonded to the boundary between the first element and the second element so that the interlayer insulating film remains. This is because, after the element is separated from the surface on the opposite side of the metal substrate of the semiconductor substrate by the method described in the fourth embodiment, the interlayer insulating film on the element boundary is brought into the RJE etching stop layer. Features. For example, 'A1 which contains about 1% of Si in an atomic composition is formed as a wiring metal by a sputtering method', and the photoresist is patterned by photolithography, and the collector electrode 1107 is formed by a technique such as RIE, for example, The film formation of Si〇2 at a temperature of 400 ° C as the interlayer insulating film 1108 is performed by repeating the above process to form the 26 1355090 collector-side wiring shown in Fig. 14 (c). In the interlayer insulating film 1108, vias 11〇9 for electrically connecting the collector electrode 11〇7 to the wiring layer or the metal substrate of the second and subsequent layers may be formed. Next, in order to bond the metal substrate serving as the support substrate and the power supply substrate to the semiconductor substrate formed as described above, the entire surface of the collector side surface of the semiconductor substrate is deposited by, for example, sputtering. After the left and right, for example, n + Si 1110 ', the metal substrate 11 is bonded to the n + Si layer. The metal substrate may be, for example, a substrate having the Ni surface shown in Example 4, and a uniformity of about 5 rc (the ratio of the nSi layer to the Ni layer is used to form a dream layer m2 to obtain a strong bond. .

After forming the wiring on the collector side in this manner, bonding to the metal substrate is performed, and then the emitter side wiring is formed by the method shown in the fourth embodiment, whereby the vertical type having wiring on both sides of the semiconductor layer can be obtained. Semiconductor integrated circuit. Since it can be (10) on the single-substrate having the alignment on both sides of the recording-semiconductor-transfer phase, it is necessary to form ECL (emitter-coupled logic) or the like of the wiring of the set-up, which is simply formed on a single substrate. According to the present invention, the controlled enthalpy of the φ (110) plane orientation crystal is superimposed on the low temperature of the left and right sides of the team, and the semiconductor layer can be formed on the metal substrate in advance, so that the original solution becomes a The problem of the substrate breaking during surface grinding

f 2 This lining makes the parasitic electricity _ less, can rotate the component at high speed, and makes the conventional conductor less to the heart (4), the view can be reduced, and it is only parallel to the surface of the substrate (11. == mask or The diffusion constant of the hole is increased, and the conduction or separation is performed at a high speed: Ut is formed on the single-soil plate from the elements of the plurality of semiconductor elements formed, and a plurality of vertical semiconductor elements are formed. Wiring is formed on both sides to intensively read and distribute the parasitic capacitance and turn of the wiring, and it can be used to delay or cause a surge (4) problem. Furthermore, according to the present board, it can be used in the vertical type. a wiring layer is formed on both sides of the semiconductor layer,

By installing the side tree on the _substrate to make the _ _ I inverter or ECL (emitter light Logic) can now be used on these simple terrain single-substrate, can be used _ semi-conductive _ various In the case of forming a semiconductor layer on a metal substrate, it is possible to sufficiently reduce the (four) remaining of the element which is a problem in the longitudinal direction, or to conduct a high-speed or surface current due to the use of a metal substrate. To increase the thermal conductivity of the substrate, so

= "heat" inhibits the thermal runaway of the component caused by the heat. J goes to = Qiaoming semiconductor substrate, because it is in the sun. . The semiconductor layer below and below, and can be precision = ^Nan and /7 cloth', so that the base layer can be manufactured with a short thickness and high performance. Shen The following describes the symbols used in this manual. 101 is a Si layer having a first conductivity type. 102 is a Si layer having a second conductivity type. 103 is a Si layer having a third conductivity type. 104 is a Si layer having a fourth conductivity type.

108 is a metal substrate composed of a metal substrate and a continuous metal layer. 107 is a bonding layer. [Simple description of the drawing] = is a sectional view showing the structure of a conventional pure crystal substrate. When the thickness of the semiconductor layer is invented by the drag reduction. According to the first embodiment of the present invention, the configuration of the bipolar transistor crystal conductor substrate is described in the first embodiment of the present invention. The paste side 1 bipolar method (4) is displayed according to the process sequence. The manufacturing process sequence of the semiconductor substrate of the present invention is not shown in the second embodiment of the present invention. The semiconductor device of the fourth embodiment of the present invention is shown in FIG. An example of a section is formed. The semiconductor device for manufacturing a vertical conductor component on a substrate to display a semiconductor device according to the present invention is used in a single-semiconductor semiconductor, as intended, the semiconductor device is The vertical semiconductor rings 14 (a) to 14 (d) are formed on a substrate formed by a single 29 1355090 device, which is formed by a vertical semiconductor device in accordance with a method for manufacturing a lane conductor device. Description of the component symbols: 1001 : 矽 substrate 1002 : porous ruthenium layer 1003 : buffer layer 1004 : pfSi layer, shoal layer 1005 : Si 〇 2 layer, oxide film 1006 : η + Si, epitaxial film 1007 : η + Si Amorphous or polycrystalline stone 1008 : p-type Si layer 1009 : single crystal p-type Si layer, epitaxial film 101 : Si layer 1010 having the first conductivity type: Si layer 1015 : metal substrate 1017 : opening 1018 : Si〇 2 1019 : base electrode 102 : Si layer 1020 having the second conductivity type: emitter electrode 1021 : npn-type bipolar transistor 1022 : pnp-type bipolar transistor 1023 : element isolation region 1024 : deuterated layer 103 Si layer 104 having a third conductivity type: Si layer having a fourth conductivity type 1355090 107: bonding layer 108: metal substrate 1104: semiconductor layer 1106: interlayer insulating film 1107: collector electrode 1108: interlayer insulating film 1109: Hole 1110 : nSi 1111 : Metal substrate 1112 : Deuterated layer 1301 : High concentration n-type semiconductor germanium layer 1302 : Low concentration n-type semiconductor germanium layer 201 : germanium substrate 202 : porous germanium layer 203 : germanium layer 203 : n-type germanium 204 : p-type base layer 205 : n-type collector layer 206 : n-type high concentration collector 207 : deuterated layer 208 : metal substrate 305: base layer 307: photoresist 308: base contact layer 309: base electrode 310: emitter electrode 311: Si〇2 401: metal substrate 403: high concentration drain layer 31 1355090 404 drain layer 405 bulk layer 503 layer 503 high concentration collector layer 504 no pole layer, drain region 505 broken, body region 506 source region 507 Si〇2 film 508 trench hole 509 source electrode portion, source electrode 510 gate electrode 511 oxide film 512 interlayer insulating film 601 metal substrate 603 anode layer 604 buffer layer 605 conductivity modulation layer 606 gate layer 705 conductivity modulation layer 707 cathode region 708 Si〇2 709 channel hole 710 gate electrode 711 cathode electrode portion 32

Claims (1)

1355090 year f !. September 2, 100 revised replacement page 093129836 (no underline) Ten, application of the benefits of the benefit If! · ιι: τ£^ connected 苐 2 metal Ni. Package 1 will be a semiconductor device with a range of 帛1, including the semiconductor layer, Γ, f2 Γ31), (321)®, (531)*, (231)*, (351) The semiconductor device of item 1 or 2, wherein the semiconductor layer is composed of a conductively different layer having a township number. A manufacturing method of a plurality of devices is a method for manufacturing a semiconductor layer having a plurality of different conductivity types on a metal substrate, comprising: a process of forming a porous germanium on a germanium substrate; and growing a potential semiconductor layer on the layer a process of bonding the ceramsite layer to the metal substrate as a stupid crystal stone, and a semi-conductive layer of a bismuth plate and a semiconductor substrate having the crystallite layer. At the interface between the screen, the screen includes: a metal substrate composed of a first metal Cu; diffusion prevention t is diffused from the metal substrate_first metal-semiconductor layer, and is formed on the surface of the metal substrate TaN or secret composition; and connection gold 33 September 100 < 2 曰 correction replacement page genus 'by the shape of silk 彡 该 该 缝 缝 缝 缝 —— ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;; a process in which a cat's day-to-day layer is bonded to the metal substrate, and a metal layer of the metal substrate is formed by bonding the bonding layer formed by the second metal layer, and the layer is joined by the stone layer金属 the metal substrate and the semiconductor The fit between the body layers. The manufacturing method of the two kinds of f-conductor devices, the method for manufacturing the semiconductor layer of the plurality of different conductivity types, including: the process of forming a porous stone on the substrate of the Xixi; (4) 'Processing a plurality of conductive semiconductor layers adjacent to each other in the horizontal direction, and performing a process of epitaxial growth by the parent; _ making the epitaxial growth _ crystal (4) and having the metal substrate And the process of forming the electrically separated insulating layer of the semiconductor substrate f. In the method of manufacturing a semiconductor device of 4 or 5 items, the "degree of growth" is less than 6 〇〇〇c. XI. Schema: