TWI355065B - Method and device of multi-chip stack to halve wir - Google Patents

Abstract

Disclosed are a method and a device of multi-chip stack to halve wire-bonding processes. According to the method, initially, a carrier substrate having a plurality of fingers is provided. At least a first chip is disposed on the substrate. Next, a plurality of bonding wires are formed by wire-bonding to connect the first electrodes of the first chip to the fingers. At least a second chip is face-to-face disposed on the first chip. During mounting the second chip, the second electrodes of the second chip are bonded to the ends of the bonding wires on the first electrodes so that the second chip is electrically connected with the substrate through the bonding wires. In one embodiment, the second electrodes of the second chip are bonded with the first electrodes. Accordingly, half of wire-bonding processes and the amount of the bonding wires can be reduced to shorten production cycle time and to save costs. Additionally, the ends of the bonding wires on the first chip can be re-bonded to the first electrodes to solve the problems of wire broken and wire-sweep. In a preferred embodiment, the bonding wires are formed by reverse bonding.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-wafer stacking technique applicable to a semiconductor device, and more particularly to a wafer stacking method in which a wire bonding process is halved and a configuration thereof. [Prior Art] In order to improve the performance and capacity of a single semiconductor device, in order to meet the trend of miniaturization, large capacity, and high speed of electronic products, a plurality of wafers are generally stacked on a carrier to save space. However, the number of wire-bonding connections in the process corresponds to the number of wafer stacks. As the number of wafer stacks increases, the number of wire-bonded electrical connections increases, making the process complicated and susceptible to wire-breaking problems. Referring to FIG. 1 and referring to FIG. 2, a conventional multi-wafer stacking method includes the following steps: "providing a carrier" step 1, "first setting a wafer" step 2, "first wire bonding" Connection Step 3, "Set a spacer" Step 4, "Second Setup Wafer" Step 5, "Second Wire Connection" Step 6, "Form a Gel" Step 7, "Set Multiple External Connections Terminal" step 8. First, in the "providing a carrier" step 1, as shown in Fig. 2A, a carrier 1 1 〇 is provided which has a plurality of fingers 1 1 1 . Next, in the "first setting wafer" step 2, as shown in FIG. 2B, a first wafer 120 is disposed on the carrier 110 by using a wafer nozzle 20, and the first wafer 120 has a plurality of An electrode 121 (as shown in Figure 3). In step 3 of the "first wire bonding" step, as shown in FIG. 2C and FIG. 3, reference numeral 13135565, the wire is formed into a plurality of first bonding wires 131, which are formed by a soldering pin 3 The first end i31A of the front line 131 is connected to the first electrodes 121' and the first end 131B is connected to the connecting fingers 111. Next, in the step of "setting a spacer", as shown in Fig. 2D, a spacer 180 is provided on the first wafer 12A. As shown in FIG. 3, the spacer 180 has a size smaller than the size of the first wafer ,2〇 to expose the first electrodes 121 and does not overstress the first bonding wires 13 in the second In the step 5, as shown in FIG. 2E, a second wafer 140 is disposed on the spacer 180 by the crystal chip suction nozzle 20, and the second wafer 140 has a plurality of second electrodes 141 ( As shown in Figure 3). Next, in the "second wire bonding" step 6, as shown in FIG. 2F and FIG. 3, a plurality of second bonding wires 132 are formed by wire bonding, and the second bonding wires 132 are used to form the second wires. The first end 132A of the bonding wire 132 is connected to the second electrodes i41, and the second end 132B is connected to the connecting fingers 111», in the step of forming a colloid, in step 7, such as φ, FIG. As shown, a gel 150 is formed on the carrier 11 to seal the wafers 12 and 140 and the bonding wires 131 and 132 (as shown in FIG. 3). Finally, in the step 8 of "setting a plurality of external terminals", as shown in Fig. 2, a plurality of external terminals I70 are provided on the surface of the sealing body 15A. Thanks to this first wafer! 20 and the second wafer 140 are respectively connected to the carrier 110 by a dedicated first bonding wire 131 and a second bonding wire 132, so that the wire bonding process of two times in the process corresponds to the number of wafer stacks. A 1355065 electrical interconnection between the wafers 12A, 14A and the carrier 11 is achieved, so that the multi-pass wiring process cannot be omitted. Moreover, the excessive number of bonding wires in the crowded sealing space is prone to the problem of punching. In addition, it is known that the soldering wires 131 and 132 are forward-wired to prevent the solder joints on the wafer from being soldered or soldered, but the maximum arc height of the solder wires 131 is On the first wafer 120. In order to prevent the second wafer 140 from contacting the first bonding wires 131 to cause an electrical short circuit, the thickness of the spacer 180 needs to be greater than the arc height of the first bonding wires 131, and the second bonding wires 132 are prevented from being exposed. Because of the encapsulant 150, the thickness of the encapsulant 150 must be increased, resulting in an inability to reduce the thickness of the overall multi-wafer stack construction. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method and a structure for halving a plurality of wafer winding processes, which can reduce the number of wire bonding processes and the number of bonding wires by half, thereby shortening the multi-wafer stacking process and saving the consumption of the bonding wires. When the upper layer wafer is disposed face to face, the electrode of one end of the bonding wire and the electrode of the lower layer wafer are re-engaged, so that the bonding force of the wire bonding end between the wires can be enhanced, and there is no problem of wire breakage and punching, and can be controlled in a thinner Stack thickness. A second object of the present invention is to provide a method and a structure for stacking a plurality of wafers in which the wire bonding process is halved. Since the tail end of the reverse bonding wire is rejoined by the electrodes of the upper wafer, the first wafer and the second can be reduced. The gap between the wafers reduces the stack height of the wafer. Another object of the present invention is to provide a method and structure for stacking a plurality of wafers in which the wire bonding process is halved to ensure effective bonding of one end of the bonding wire 8 1355065 between the upper and lower wafers to the electrodes of the wafer. Another object of the present invention is to provide a method and structure for stacking multiple wafers in which the wire bonding process is halved, and to solve the problem that the sealing body cannot fill the gap of the small wafer. Another object of the present invention is to provide a method and structure for stacking multiple wafers in which the wire bonding process is halved, so that the fingers can be shared by wires, and the number of fingers can be reduced to reduce the cost of the carrier. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. In accordance with a multi-wafer stacking method disclosed herein, first, a carrier is provided having a plurality of fingers. Thereafter, at least one first wafer is disposed on the carrier, the first wafer having a plurality of first electrodes. Then, the wire is formed into a plurality of first bonding wires, which connect the first electrodes to the fingers. Finally, at least one second wafer is disposed on the first wafer, the second wafer has a plurality of second electrodes, and the second electrodes are bonded to the first bonding wires at the same time One end of an electrode to electrically connect the second wafer to the carrier via the first bonding wires. A multi-wafer stack construction is also disclosed. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing multi-wafer stacking method, the first bonding wires may be reverse bonding wires, and the first bonding wires are terminated at one end of the first electrodes to make the wires The maximum arc height of the first bonding wire is away from the first wafer and does not exceed the second wafer. 9 1355065 In the foregoing multi-wafer stacking method, the second electrode systems may be gold bumps and gold-gold bonded to the first bonding wires. In the foregoing multi-wafer stacking method, the second electrode systems may be solder bumps and re-sold to the first bonding wires. In the foregoing multi-wafer stacking method, the second electrodes may coat the first bonding wires on one of the first electrodes and solder them to the first electrodes. In the foregoing multi-wafer stacking method, the first electrode systems may be bumps. In the foregoing multi-wafer stacking method, the first electrode systems may be solder bumps. In the foregoing multi-wafer stacking method, the method further comprises the steps of: forming a gel on the carrier to seal the first wafer, the second wafer, and the first bonding wires. In the foregoing multi-wafer stacking method, the encapsulation system can fill the gap between the first wafer and the second wafer. In the foregoing multi-wafer stacking method, the method further includes the steps of: forming a filling glue on the first wafer after the forming of the first bonding wires; and baking and curing the filling after the second wafer is disposed a glue to fill the gap between the first wafer and the second wafer. In the foregoing multi-wafer stacking method, the method further comprises the steps of: providing a plurality of external terminals on the surface of the carrier to be exposed on the surface of the sealing body. In the foregoing multi-wafer stacking method, the first wafer system may be plural, and the connecting fingers are located between the first wafers. 10 1355065 In the foregoing multi-wafer stacking method, the first electrodes and the second electrodes may be peripherally arranged. In the foregoing multi-wafer stacking method, the first electrodes and the second electrodes may all be centrally disposed. In the foregoing multi-wafer stacking method, the method further includes the step of: disposing a third wafer on the second wafer, the third wafer having a plurality of third electrodes. In the foregoing multi-wafer stacking method, the method further comprises the steps of: forming a plurality of second bonding wires by wire bonding, and connecting the third electrodes to the contacts. In the foregoing multi-wafer stacking method, the method further includes the steps of: disposing a fourth wafer on the third wafer, the fourth wafer has a plurality of fourth electrodes, and at the same time, the fourth electrodes are disposed Bonding to the one ends of the second bonding wires on the third electrodes to electrically connect the fourth wafer to the carrier via the second bonding wires. [Embodiment] According to the first embodiment of the present invention, with reference to Figures 4 and 5, a method for stacking wafers in which the wire bonding process is halved is specifically disclosed. Referring to FIG. 3, a multi-wafer stacking method mainly comprises the following steps: "providing a carrier board" step 11, "first setting a wafer" step 12, "wire bonding electrical connection" step 13, "forming a filling" Glue Step 1 4, "Set the wafer and electrically connect the second time" Step 1 5, "Form a gel" Step 16. "Set a plurality of external terminals" Step 17. Among them, the step of forming a filling glue step 14 is an unnecessary step, so 11

In the same embodiment as X, the step of forming a filling glue step 14, "forming a package * body J step 16 and "setting a plurality of external terminals" step 17 can be omitted or replaced. Refer to Figure 5 for the component composition relationship in each step. The sequence of steps is detailed below. First, in the "providing a carrier J step U, as shown in FIG. 5A, the carrier plate 21 is provided". The carrier 210 has a plurality of fingers 211. Generally, the carrier 210 is a circuit substrate. Or a multi-layer printed circuit board, which may be a lead frame or a pre-mode lead frame, depending on the application product. Specifically, the carrier 210 has a die-bonding surface 21 2 and a relative The exposed surface 2 1 3 is formed on the side of the die surface 2 1 2 , and in this embodiment is arranged on two opposite parallel sides of the die surface 212. In the step 12 of "setting the wafer for the first time", as shown in FIG. 5B and FIG. 6, 'providing at least one first wafer 22 on the carrier 210', the first wafer 220 has a plurality of first electrodes 221 (as shown in FIG. 6), the first electrodes 221 may be arranged on the side of the first wafer 22, such as two corresponding sides or four sides. The active surface of the first wafer 220 is adsorbed by a wafer nozzle 40, and the back surface of the first wafer 220 is attached to the die surface 212 of the carrier 210, and is bonded by an adhesive. After the step 12, the first wafer 220 is disposed on the carrier 210 with the first electrodes 221 facing away from the carrier 21〇. In an embodiment, as shown in Fig. 6, the first electrodes 221 may be solder pads such as aluminum pads or steel pads. In another embodiment, as shown in FIG. 7, another first wafer 220, the plurality of first electrodes 12

< S 1355065 22p can be a bump, such as gold bumps, copper bumps or other composite bumps of conductive material.

• Next, in the “wire-to-wire electrical connection” step 13, as shown in FIG. 5C and FIG. 6 , a plurality of first bonding wires 231 are formed, which are connected to the first electrodes 221 to the connections. Means 211. The first bonding wires 231 are elongated flexible metal wires. Preferably, the first bonding wires 23 are reversed bonding wires. One end of each of the first bonding wires 231 can be connected to the corresponding fingers 211 by a bonding wire 50, and then the soldering pins 50 are moved upward, and the first bonding wires 231 are further One end is wired to the first electrode 22 1 corresponding to the finger 2 1 1 to electrically interconnect the first wafer 220 and the carrier 210. After the repeated wire bonding, all of the first bonding wires 23 1 can be formed. The above-mentioned wire bonding method may be selected from the group consisting of Ultrasonic Bonding (U/S), Thermocompression Bonding (T/C) or Thermosonic Bonding (T/S). One. As shown in FIG. 6 φ, one of the first ends 231A of each of the first bonding wires 231 is connected to one of the fingers 211 of the carrier 210, and is a ball bond. The second end 231B of each of the first bonding wires 231 is connected to one of the first electrodes 221 of the first wafer 220, and is a wire tail end (^丨1匕011 (1, or For 忱111)〇11£1). Therefore, the maximum arc height of the first bonding wires 23 1 is away from the first wafer 22 且 and does not exceed the second wafer 240 (as shown in Fig. 6). If necessary, in the present embodiment, as shown in Fig. 5D, after the "wire-to-wire electrical connection" step 13, a "formation of a filling" 13 1355065 step 14 can be performed. After the first bonding wires 231 are formed, a filling paste 2 60 is formed on the first wafer 220. In this embodiment, a still liquid filling glue 260 can be applied to the central portion of the first wafer 220 by a dispensing technique using a dispensing technique. The filler 260 is available as an underfill material 260 (underfill material), a non-conductive paste (NCP), an anisotropic conductive paste (ACP, ACF). After the step 15 of "setting the wafer and electrically connecting for the second time", the filling adhesive 260 is baked and cured, so that the filling adhesive 260 fills the gap between the first wafer 220 and the second wafer 240 (eg, the sixth As shown in the figure, it can solve the problem that the wafer gap is too small to fill the encapsulant 250 to form pores and bubbles. In another non-limiting embodiment, the "forming a filler" step 14 may be omitted. As shown in FIG. 9, the filler 260 may not be used between the first wafer 220 and the second wafer 240. The encapsulant 250 directly fills the gap between the first wafer 220 and the second wafer 240. Then, in step 15 of "Second setting and electrically connecting", at least one second wafer 240 or 240' is disposed on the first wafer 220 as shown in FIG. 5E, F and FIG. The second wafer 240 has a plurality of second electrodes 241 on the active surface thereof, and the second electrodes 241 are bonded to the first bonding wires 23 1 on the first electrodes 221 while being disposed. The second end 23 1B is electrically connected to the carrier 210 via the first bonding wires 231 . Specifically, the wafer nozzle 40 can be used to adsorb the back surface of the second wafer 240 and press the active surface of the second wafer 240 onto the active surface of the second wafer 240. 14 1355065 Therefore, the second wafer 24 〇 丨 丨 丨 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 冲 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二The electrode 221 is disposed on the first sheet 220. The method of joining the second electrode 231 of the first buckle 2 to the second end 231 of the first buckle 2 may be ultrasonic bonding or back welding. In the embodiment t, the first wafer 22q and the second wafer 24 can be the same size. The first electric S 221 and the second electrodes (4) may be peripherally arranged. Referring to FIG. 6 , in the specific example, the second electrodes 241 may be gold bumps and gold and gold are bonded to the first bonding wires 231 so that the second crystal moon is disposed. The second end Bn of the first bonding wire 231 may be re-bonded to the first electrodes 221. Preferably, the second electrodes 241 are further bonded to the first electrode electrodes 221. In another embodiment, as shown in FIG. 7, the second plurality of second electrodes 241 of the second type 曰w-day 240 240' may be embossed and pulled back. Some first bonding wires 231. As shown in FIG. 7 , the first electrode 241 ′ can cover the second ends 231B of the first bonding wires 231 on the first electrodes 21 and solder them to the first electrodes. 221,, buckled from

Only the second ends 231B of the first bonding wires 23 1 are effectively joined to the second electrodes 241 by the first φ w- * 221'. Therefore, the present invention only needs one wire bonding process, and the two stacked chips are electrically connected to the board, and the second wafer 240 can be simultaneously provided to achieve the first-s-b-day film 2 4 0 and the electrical interconnection between the carrier 2 1 0 'exemption from the conventional; ^ 士 + & v > 孜 在 在 在 在 设置 设置 设置 设置 设置 设置 设置 设置 设置 设置 设置 设置 第二 第二 第二 第二 第二 第二 第二 第二 第一 第一 第一 第一 第一 第一The connection step can reduce the Φ & half of the wire and save the wire to shorten the process compared to the conventional wafer multi-wafer stacking method. Since the second electrodes 241 of the second wafer 240 are coupled to the second ends 231B of the first bonding wires 231, the first bonding wires 231 are electrically shared, and are electrically connected to the carrier. The plate 210 can significantly reduce the number of bonding wires required for wire bonding to reduce manufacturing costs. Moreover, the second electrode 241 is bonded to the first bonding wires 23 1 , so that the bonding force of the first bonding wires 231 on the second end 231B of the first wafer 220 can be enhanced without disconnection. The problem with the line. In addition, in the above multi-wafer stacking process, it is not necessary to provide a conventional spacer between the first wafer 220 and the second wafer 240, which can reduce the number of processing steps and reduce the multi-wafer stack height. Specifically, as shown in FIG. 5G and FIG. 6, the multi-wafer stacking method may further include a “forming a gel” step 16 by forming a gel 250 by using a method such as molding or printing. The first wafer 22, the second wafer 24, and the first bonding wires 231' are sealed on the board 210 to protect the first wafer 220 and the second wafer 240 and the first bonding wires 231. It is polluted by outside dust and water. Since the number of bonding wires to be sealed by the encapsulant 250 is reduced, and the unit density of the bonding wires is lowered, the possibility of occurrence of the punching is reduced when the encapsulant 250 is formed. In addition, there is no need to reserve a wire arc height on the second wafer 240 to prevent the wire from being exposed and the package size from being thinned. In this embodiment, the multi-wafer stacking method may further include a step of "setting a plurality of external terminals". As shown in FIG. 5 and FIG. 6, a plurality of external terminals 210 are disposed on the carrier 210 to expose the exposed surface 213 of the package body 250. The external terminals 270 may be solder balls, or may be replaced by solder paste, metal balls, metal plugs or 16 1355065 anisotropic conductive paste (ACF) as the outer 4 270 ° in order to cope with Other functional requirements or stacking of wafers can be made up to increase the allowable thickness of the memory. The polycrystalline method can additionally include two sets of wafers and one wire bond between the wafer sets. Referring to FIG. 8, in the third crystal step, a third wafer is disposed back to back on the second crystal, and the third wafer 280 has a plurality of third electrodes 281. The third electrodes 281 are disposed on the second wafer 240 with the third electrodes 281 facing away from the sheet 240. The 280th line can be substantially identical to the first wafer 220. In a single tapping step, a plurality of second bonding wires 23 2 are formed which connect the poles 281 to the fingers 211. The second bonding wires 232 are connected to the connecting fingers 211, and the second bonding wires 232 are connected to the third electrodes 28 in a fourth wafer setting, and a fourth wafer 290 is connected. The fourth wafer 290 is disposed on the third surface of the third electrode 291, and the fourth electrode 291 is bonded to the third electrode 281 on the third electrode 281. The two ends 232B are electrically connected to the wafer 290 via the second bonding wires 232. Therefore, a sheet stacking structure according to the foregoing multi-wafer stacking method can be referred to FIG. 6, and the carrier board is mainly included. A wafer 220, the first bonding wires 231, and the second wafer 220 are disposed on the carrier 210. And by the 妾 terminal amount, the sheet is disposed in the sheet stacking step, and the second crystal second wafer is formed into the third electric first end, the second end step sheet 28 0 » the second soldering line is disposed on the fourth board The polysilicon of 2 1 0 、, the 240th portion of the 173505505, a bonding wire 23 1 is connected to the first electrodes 221 of the first wafer 220 to the fingers 211 of the carrier 210. The second wafers 240 are disposed face to face on the first wafer 22, and the second electrodes 241 of the second wafer 240 are bonded to the first bonding wires 23 1 on the first electrodes 221 The two ends 231B are electrically connected to the carrier 210 via the first bonding wires 231. In the embodiment, the first electrodes 221 may be solder pads. The second electrodes 241 may be gold bumps and may be gold-gold bonded to the second ends 231B of the first bonding wires 231 by ultrasonic or thermocompression, and a portion of the second electrodes 241 More bonding to the first electrodes 221 is possible. A gel 25 can be formed on the carrier? The viscous surface 212 of the 10 is sealed to seal the first wafer 220, the second wafer 240, and the first bonding wires 23A and cover the contacts 2U. The external terminals 27 can be disposed on the exposed surface 213 of the carrier 210. Force

The stack structure can be referred to in Fig. 7' except for the first wafer 22'' and the second cover 240', and the remaining main components are the same. The first wafer 22, the inferior first electrode 22 can be a bump, and the second electrode 241' of the second wafer 240' can be a solder material & The return welding is combined with the continuous bonding wire 231. The second electrodes 241, the rear π system may cover the first electrodes 231 on the first electrodes 221' and further solder the first electrodes 22A. The multi-wafer stack configuration taught in accordance with the foregoing multi-wafer stacking method can stack more wafers θ ° in a limited thickness. As shown in FIG. 8, the third wafer can be further stacked on the 18 1355065 second wafer 240. 280 and the fourth wafer 290 form a plurality of second bonding wires 232, and the wafer stacking and wire bonding method may be the first step of "setting the wafer" step 12, "wire bonding" step 13 and "second time". Repeat the operation of step 15 of setting up the wafer and electrically connecting. As shown in FIG. 9, the "forming a filler" step 14 may be omitted in different embodiments, and the encapsulant 250 may be more filled in the multi-wafer stack construction fabricated according to the multi-wafer stacking method described above. A gap between the wafer 220 and the second wafer 240. In accordance with a second embodiment of the present invention, another method and construction of halving a plurality of wafer stacking processes is disclosed. First, referring to Fig. 10A, a carrier 310 is provided, which has a plurality of fingers 31. In this embodiment, the fingers 311 can be formed in a central region of the carrier 310. Then, as shown in FIG. 10B and FIG. 11, at least one first wafer 32 is disposed on the carrier 310 by using a wafer nozzle 4, in the embodiment, the first wafer 3 The number of the fingers may be reduced between the first wafers 320, so that the fingers 3 1 1 can be shared by wires. Therefore, the number of the fingers 311 can be reduced. The cost of the carrier 310 is reduced. As shown in Fig. u, each of the first wafers 32 has a plurality of first electrodes 321 . The first electrodes 321 can be arranged in a central region of the associated first wafer 320. In this embodiment, the first electrodes 321 can be solder pads. In another embodiment, as shown in Fig. 12, the plurality of first electrodes 321' / 19 1355065 of the other first wafer 320' may be bumps. Next, as shown in Fig. 10C and Fig. 11, a plurality of bonding wires 33A are formed by the left-hand pin 50, which connects the first poles 321 to the fingers 311. As shown in FIG. 2, the first end 331 of the circuit 2 3 0 0 is connected to the fingers 311, and the first 3 3 2 is connected to the first electrodes 32 The end 331 can be a ball end, and the second end 332 can be a wire tail. ’

Optionally, in an embodiment, as in the first embodiment, the multi-wafer stacking method may further include a step of forming a filling adhesive. After the bonding wires 330 are formed, a point is utilized. The glue head 6 〇 forms a filling glue 360 on the active surface of the first wafer 320. Then, as shown in FIG. 10 and FIG. 1 , at least one second wafer 340 or 340 is disposed on the wafer nozzle 40, and the active surface of the second wafer 340 is disposed on the first wafer 320. The active surface faces the first wafer 320. The second wafer 340 has a plurality of second electrodes 341 ′ disposed on the active surface thereof, and the second electrodes 341 are coupled to the second ends of the solder wires 330 on the first electrodes 321 . 332, the second electrode 340 is electrically connected to the carrier 310 via the bonding wires 330. In this embodiment, the first electrodes 321 and the second electrodes 341 can be centrally disposed. In this embodiment, as shown in FIG. 11, the second electrodes 341 may be gold bumps and gold/gold bonds to the second ends 332 of the bonding wires 330. In another embodiment, as shown in FIG. 12, 'the other second wafer 340, the plurality of second electrodes 34 can be solder bumps and soldered back to the bonding wires /r·», 20 1355065 330. Further, as shown in FIG. 12, the second electrodes 341' may be coated with the second ends 332 of the bonding wires 330 on the first electrodes 32 and soldered to the first electrodes 32A. Therefore, by the above process, the number of wire bonding processes and the number of bonding wires can be reduced by half, the process can be shortened and the bonding wires can be saved, and the bonding wires 330 can be reinforced on the first wafer 320 or 320' (ie, the second end 33). 2) The joint force does not have the problem of disconnection and punching. As shown in FIG. 10F, after the second wafer 340 is disposed, the filler 360 may be baked and cured to fill the gap between the first wafer 320 and the second wafer 340. More specifically, as shown in FIG. 10G and FIG. 11 , the multi-wafer stacking method may further include a “forming a gel” step, and a gel 350 is formed on the carrier 310 to seal the same. The first wafer 320, the second wafer 340, and the bonding wires 340. The multi-wafer stacking method described above can be used to form a card-type or brick-like multi-wafer stack structure, such as various memory cards or planar array package structures (LGA). Another multi-wafer stack construction made in accordance with the foregoing method is disclosed. Referring to FIG. 13 , in the variation of the second embodiment, the main components of the multi-wafer stack structure are still the basic example of the second embodiment except that the first wafer and the second wafer are different. The same, so the same figure number is used. The multi-wafer stack configuration includes at least a first wafer 320A and at least a second wafer 340A. The plurality of first electrodes 321A of the first wafer 320A and the plurality of second electrodes 341A of the second wafer 340A may all be unilaterally arranged. The carrier 310 has a plurality of contacts 21 1355065 fingers 3 11 . The first wafer 320 A is disposed on the carrier 310. The first ends 331 of the bonding wires 330 are connected to the fingers 311, and the second ends 332 are connected to the first electrodes 321A. The second wafer 340A is disposed on the first wafer 320A, and the second electrodes 341A of the second wafer 340A are bonded to the second ends 332 of the bonding wires 330 on the first electrodes 321A. The second wafer 340A is electrically connected to the carrier 3 10 via the bonding wires 330. A fillant 360 fills the gap between the first wafer 320A and the second wafer 340A. The encapsulant 350 is formed on the carrier 310 to seal the first wafer 320A, the second wafer 340A, and the bonding wires 330. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention. [Simple Description of the Drawing] Fig. 1: A flow chart of a conventional multi-wafer stacking method. Figure 2: A perspective view of the components in a conventional multi-wafer stacking process. Fig. 3 is a cross-sectional view showing a polycrystalline wafer stack structure constructed in accordance with a conventional multi-wafer stacking method. Figure 4 is a flow chart showing a method for stacking wafers by half of the wire bonding process 22 1355065 in accordance with a first embodiment of the present invention. Figure 5 is a perspective view of the components in a multi-wafer stacking method in accordance with a first embodiment of the present invention. Figure 6 is a schematic view showing the wearing of a multi-wafer stacking structure in accordance with the multi-wafer stacking method in accordance with a first embodiment of the present invention. Figure 7 is a cross-sectional view showing another multi-wafer stack structure fabricated in accordance with the multi-wafer stacking method in accordance with a first embodiment of the present invention. Figure 8 is a cross-sectional view showing a multi-wafer stack configuration in which a plurality of wafers are formed and stacked in accordance with the multi-wafer stacking method in accordance with a first embodiment of the present invention. Figure 9 is a cross-sectional view showing a multi-wafer stack configuration which is made in accordance with the multi-wafer stacking method and which does not use a filler, in accordance with a first embodiment of the present invention. Fig. 10 is a perspective view of the components in another method of stacking wafers halved in accordance with a second embodiment of the present invention. Figure 11 is a schematic view showing a multi-wafer stack structure constructed in accordance with the multi-wafer stacking method in accordance with a second embodiment of the present invention. Fig. 2 is a cross-sectional view showing another multi-wafer stack structure fabricated in accordance with the multi-wafer stacking method in accordance with a second embodiment of the present invention. 23 1355065 FIG. 1 3 is a cross-sectional view showing another multi-wafer stack structure fabricated in accordance with the multi-wafer stacking method in accordance with a second embodiment of the present invention. [Main component symbol description] 1 Provide a carrier board 2 Set the wafer for the first time 3 Connect the first time to the electrical connection 4 Set a spacer

5 Set the wafer for the second time. 6 The second wire is electrically connected. 7 Form a gel. 8 Set a plurality of external terminals.

11 Providing a carrier 12 First setting the wafer 13 Bonding the electrical connection 14 Forming a filling glue 15 Second setting the wafer and electrically connecting 16 Forming a gel 17 Setting a plurality of external terminals 20 Wafer nozzle 30 Solder pin 40 Wafer nozzle 50 solder pin 110 carrier plate 111 finger 120 first wafer 121 first electrode 131 first bonding wire 131A first end 60 dispensing needle head 131B second end 24 1355065

132 second bonding wire 132A first end 140 second wafer 141 second electrode 150 encapsulant 170 external terminal 210 carrier 211 finger 213 exposed surface 220 first wafer 221 first electrode 220, first • wafer 221 ' first • electrode 231 first bonding wire 231A first end 232 second bonding wire 232A first end 240 second wafer 241 second electrode 240, second wafer 241, second electrode 250 encapsulant 260 filling 280 third wafer 281 third electrode 290 fourth wafer 291 fourth electrode 310 carrier 311 finger 320 first wafer 321 first electrode 320' first-wafer 321, first electrode 320A first-die 321A first--electrode 330 solder Line 331 first end 340 second wafer 341 second electrode 340, second-wafer 341, second-electrode 340A second-second wafer 341A first-second electrode 350 encapsulant 360 filling glue 132B second end 180 spacer 2 1 2 the second end 232B of the second end 232B of the viscous surface 231B is externally connected to the second end 25 of the terminal 332

Claims (1)

1355065 X. Patent application scope: 1. A multi-wafer stacking method comprising: providing a carrier board having a plurality of fingers; a plurality of first electrodes; The first bonding wires are electrically connected to the carrier via the first bonding wires. On the corona piece, the second wafer is simultaneously "the second electrode is connected to one end of the electrode" to make the second, as claimed in the patent scope! The multi-wafer stacking method, wherein the first bonding wires are reverse bonding wires, and the first bonding wires are terminated at one end of the first electrodes to make the wires The maximum arc of the first bond wire is further away from the first wafer and does not exceed the second wafer. 3. The multi-wafer stacking method of claim i, wherein the two first electrodes are gold bumps and gold-gold bonds to the first wire bonds. 4. The multi-wafer stacking method of claim 2, wherein the second electrodes are solder bumps and are soldered back to the first bonding wires. 5. The multi-wafer stacking method of claim 4, wherein the second electrodes cover one end of the first bonding wires on the first electrodes and are further soldered to the first electrodes . 6. The multi-wafer stacking method of claim 1 or 5, wherein the first electrodes are convex. 26 13 1355065 7. The multi-wafer stacking method of claim 1, wherein the first electrodes are solder pads. The multi-wafer stacking method of claim 1, further comprising the steps of: forming a body on the carrier to seal the first wafer, the second wafer, and the first Welding wire. 9. The multi-wafer stacking method of claim 8, wherein the encapsulant further fills a gap between the first wafer and the second wafer. / 1. The multi-wafer stacking method of claim U8, further comprising the steps of: after the forming of the first bonding wires, forming a filling on the first wafer; After the second wafer, the filler is cured to fill the gap between the wafer and the wafer. — 11 — The multi-wafer stacking method as described in claim 8 (4), further comprising the steps of: setting a plurality of external terminals exposed on the carrier plate: a surface of the colloid β, 12. The multi-wafer stacking method of claim 1, wherein the first-crystal system is plural, and the fingers are located between the first ones. The multi-wafer stacking method described in the above-mentioned Patent No. 1 is a peripheral configuration of the first electrode and the second electrodes. 14. The multi-wafer stacking method described in the first item of the fourth (4), the first electrode discs, the first electrode, the first electrodes are centrally arranged. 15. The multi-wafer stacking method of claim 1, wherein the step of: placing a third wafer on the second wafer 27 has a plurality of third electrodes. 16. The multi-wafer stacking method of claim 15, wherein the method comprises the steps of: forming a plurality of second bonding wires by wire bonding, and connecting the two electrodes to the fingers. The multi-wafer stacking method of claim 16, wherein the step of: providing a fourth wafer on the third wafer has a plurality of fourth electrodes, and at the same time, The fourth electrode is bonded to one end of the second bonding wires on the third electrodes 18 so that the fourth wafer is electrically connected to the carrier via the second bonding wires. a multi-wafer stack structure comprising: a carrier board having a plurality of fingers; at least one first wafer is disposed on the carrier, the first wafer having a plurality of first electrodes; a first bonding wire formed by a plurality of wires, connecting a plurality of fingers, and an electrode to the φ at least a second wafer, the signal is even from the u ** W system - placed on the first wafer, the flute The 曰 system has a plurality of: electrodes, wherein the first wire-bonding wires are at one end of the first electrodes, and the wires are electrically connected to the carrier by the two first wires. 19. The multi-wafer stack according to claim 18, wherein the first bonding wires are reversed and each of the first electrodes has a ___ line at the large arc height. Far from the most positive piece of the first a ~ line and no more than the second wafer. 20. The multi-wafer stack construction of claim 1, wherein 28 1355065 The second electrodes are gold bumps and gold-bonded to the first fresh lines. The multi-wafer stack structure of claim 18, wherein the first electrode system is a solder bump and is reflow-bonded to the first-weld wires. The multi-wafer stack structure of claim 21, wherein the first electrode is coated on one of the first electrode and further soldered to the first electrode. The multi-wafer stack structure of claim 18 or 22, wherein the first electrodes are bumps. The multi-wafer stack construction of claim 18, wherein the first electrodes are solder pads. 25. The multi-wafer stack construction of claim 18, further comprising a gel formed on the carrier to seal the second wafer and the first bonding wires. 26. The multi-wafer stack construction of claim 25, wherein: the encapsulant further fills a gap between the first wafer and the second wafer. 27. The multi-wafer stack construction of claim i or claim 25, further comprising a filler layer formed on the first wafer to fill a gap between the first wafer and the second wafer. 28. The multi-wafer stack structure as described in claim 25, further comprising a plurality of external terminals disposed on the surface of the carrier. 29. The multi-wafer stack structure of claim 1, wherein the first wafer is plural, and the fingers are located between the first wafers < S 29 1355065. The multi-wafer stack structure of claim 18, wherein the first electrodes and the second electrodes are both peripherally disposed. The multi-wafer stack structure of claim 18, wherein the first electrodes and the second electrodes are centrally disposed. 32. The multi-wafer stack structure of claim 18, further comprising a third wafer disposed on the carrier, the third wafer having a plurality of third electrodes. 33. The multi-wafer stack structure of claim 32, further comprising a plurality of second wire formed by wire bonding, connecting the third electrodes to the fingers. 34. The multi-wafer stack structure of claim 33, further comprising a fourth wafer disposed on the third wafer, the fourth wafer having a plurality of fourth electrodes, wherein the fourth The electrode is bonded to one end of the second bonding wires on the third electrodes, so that the fourth wafer is electrically connected to the carrier via the second bonding wires. 30